Nick: Th3Fanbus
E-mail: none
Board: Asrock Z97 Extreme6
Contents: 


coreboot-25.12-538-g142ae8491ce9-dirty Fri Feb 20 20:25:24 UTC 2026 x86_32 bootblock starting (log level: 7)...
Starting cbfs_boot_device
Starting cbfs_boot_device
FMAP: Found "FLASH" version 1.1 at 0x590000.
FMAP: base = 0x0 size = 0x800000 #areas = 5
FMAP: area COREBOOT found @ 591000 (2551808 bytes)
Booting from COREBOOT region
CBFS: mcache @0xff7e0e00 built for 13 files, used 0x2c8 of 0x4000 bytes
CBFS: Found 'fallback/romstage' @0xf980 size 0x1bde0 in mcache @0xff7e0e8c
BS: bootblock times (exec / console): total (unknown) / 44 ms


coreboot-25.12-538-g142ae8491ce9-dirty Fri Feb 20 20:25:24 UTC 2026 x86_32 romstage starting (log level: 7)...
Disabling Watchdog reboot... done.
SMBus controller enabled
Setting up static northbridge registers... done.
Started PEG10 link training.
Initializing IGD...
IGD is disabled.
Back from haswell_early_initialization()
CPU id(306c3) ucode:00000028 Intel(R) Core(TM) i7-4770S CPU @ 3.10GHz
AES supported, TXT supported, VT supported
PCH type: Z97, device id: 8cc4, rev id 0
Starting native platform initialisation
Intel ME early init
Intel ME firmware is ready
ME: Checking whether CPU was replaced... warm reset needed for dynamic fusing
system_reset() called!


coreboot-25.12-538-g142ae8491ce9-dirty Fri Feb 20 20:25:24 UTC 2026 x86_32 bootblock starting (log level: 7)...
Starting cbfs_boot_device
Starting cbfs_boot_device
FMAP: Found "FLASH" version 1.1 at 0x590000.
FMAP: base = 0x0 size = 0x800000 #areas = 5
FMAP: area COREBOOT found @ 591000 (2551808 bytes)
Booting from COREBOOT region
CBFS: mcache @0xff7e0e00 built for 13 files, used 0x2c8 of 0x4000 bytes
CBFS: Found 'fallback/romstage' @0xf980 size 0x1bde0 in mcache @0xff7e0e8c
BS: bootblock times (exec / console): total (unknown) / 44 ms


coreboot-25.12-538-g142ae8491ce9-dirty Fri Feb 20 20:25:24 UTC 2026 x86_32 romstage starting (log level: 7)...
Disabling Watchdog reboot... done.
SMBus controller enabled
Setting up static northbridge registers... done.
Started PEG10 link training.
Initializing IGD...
Back from haswell_early_initialization()
CPU id(306c3) ucode:00000028 Intel(R) Core(TM) i7-4770S CPU @ 3.10GHz
AES supported, TXT supported, VT supported
PCH type: Z97, device id: 8cc4, rev id 0
Starting native platform initialisation
Intel ME early init
Intel ME firmware is ready
ME: Checking whether CPU was replaced... replaced
HSIO lane owner: 0x06
SATA port enables: 0x3f
warm_reset_usb3_ports: took 5 usecs
USB2 port 0 => not mapped to OC pin
USB2 port 1 => not mapped to OC pin
USB2 port 2 => not mapped to OC pin
USB2 port 3 => not mapped to OC pin
USB2 port 4 => not mapped to OC pin
USB2 port 5 => not mapped to OC pin
USB2 port 6 => not mapped to OC pin
USB2 port 7 => not mapped to OC pin
USB2 port 8 => not mapped to OC pin
USB2 port 9 => not mapped to OC pin
USB2 port 10 => not mapped to OC pin
USB2 port 11 => disabled
USB2 port 12 => not mapped to OC pin
USB2 port 13 => not mapped to OC pin

USB3 port 0 => not mapped to OC pin
USB3 port 1 => not mapped to OC pin
USB3 port 2 => not mapped to OC pin
USB3 port 3 => not mapped to OC pin
USB3 port 4 => not mapped to OC pin
USB3 port 5 => disabled

Retraining DMI at Gen2 speeds...
DMI: Running at Gen1 x4
DMI: Running at Gen1 x4
DMI: Running at Gen2 x4
Programming SA  DMI VC/TC mappings...
Programming PCH DMI VC/TC mappings...
Waiting for PCH DMI VC negotiation... done!
Waiting for SA  DMI VC negotiation... done!
FMAP: area RW_MRC_CACHE found @ 500000 (65536 bytes)
MRC: no data in 'RW_MRC_CACHE'
CPU was replaced, forcing a cold boot
Initial bootmode: BOOTMODE_COLD
Current bootmode: BOOTMODE_COLD

Starting native raminit

Executing raminit task PROCSPD
CH0S0 is slotted and DDR3
CH0S1 is slotted and DDR3
CH1S0 is slotted and DDR3
CH1S1 is slotted and DDR3

CH0S0 SPD:
  Revision           : 11
  Type               : b
  Key                : 2
  Banks              : 8
  Capacity           : 4 Gb
  Supported voltages : 1.5V
  SDRAM width        : 8
  Bus extension      : 0 bits
  Bus width          : 64
  FTB timings        : yes
  Optional features  : DLL-Off_mode RZQ/7 RZQ/6
  Thermal features   : ext_temp_range
  Thermal sensor     : no
  Standard SDRAM     : yes
  Rank1 Address bits : normal
  DIMM Reference card: A
  Manufacturer ID    : 9801
  Part number        : KHX1600C9D3/4GX 
  Row    addr bits  : 16
  Column addr bits  : 10
  Number of ranks   : 1
  DIMM Capacity     : 4096 MB
  Vdd Min           : 1500 mV
  Vdd Max           : 1500 mV
  CAS latencies     : 6 7 8 9 10 11
  tCKmin            :   1.250 ns
  tAAmin            :  13.125 ns
  tWRmin            :  15.000 ns
  tRCDmin           :  13.125 ns
  tRRDmin           :   6.000 ns
  tRPmin            :  13.125 ns
  tRASmin           :  35.000 ns
  tRCmin            :  48.125 ns
  tRFCmin           : 260.000 ns
  tWTRmin           :   7.500 ns
  tRTPmin           :   7.500 ns
  tFAWmin           :  30.000 ns

CH0S1 SPD:
  Revision           : 11
  Type               : b
  Key                : 2
  Banks              : 8
  Capacity           : 2 Gb
  Supported voltages : 1.5V
  SDRAM width        : 8
  Bus extension      : 0 bits
  Bus width          : 64
  FTB timings        : yes
  Optional features  : DLL-Off_mode RZQ/7 RZQ/6
  Thermal features   : ASR ext_temp_range
  Thermal sensor     : no
  Standard SDRAM     : yes
  Rank1 Address bits : mirrored
  DIMM Reference card: B
  Manufacturer ID    : cd04
  Part number        : F3-2400C10-4GTX
  Row    addr bits  : 15
  Column addr bits  : 10
  Number of ranks   : 2
  DIMM Capacity     : 4096 MB
  Vdd Min           : 1500 mV
  Vdd Max           : 1500 mV
  CAS latencies     : 6 7 8 9 10 11
  tCKmin            :   1.250 ns
  tAAmin            :  13.125 ns
  tWRmin            :  15.000 ns
  tRCDmin           :  13.125 ns
  tRRDmin           :   6.000 ns
  tRPmin            :  13.125 ns
  tRASmin           :  35.000 ns
  tRCmin            :  48.125 ns
  tRFCmin           : 160.000 ns
  tWTRmin           :   7.500 ns
  tRTPmin           :   7.500 ns
  tFAWmin           :  30.000 ns

CH1S0 SPD:
  Revision           : 11
  Type               : b
  Key                : 2
  Banks              : 8
  Capacity           : 4 Gb
  Supported voltages : 1.5V
  SDRAM width        : 8
  Bus extension      : 0 bits
  Bus width          : 64
  FTB timings        : yes
  Optional features  : DLL-Off_mode RZQ/7 RZQ/6
  Thermal features   : ext_temp_range
  Thermal sensor     : no
  Standard SDRAM     : yes
  Rank1 Address bits : normal
  DIMM Reference card: A
  Manufacturer ID    : 9801
  Part number        : KHX1600C9D3/4GX 
  Row    addr bits  : 16
  Column addr bits  : 10
  Number of ranks   : 1
  DIMM Capacity     : 4096 MB
  Vdd Min           : 1500 mV
  Vdd Max           : 1500 mV
  CAS latencies     : 6 7 8 9 10 11
  tCKmin            :   1.250 ns
  tAAmin            :  13.125 ns
  tWRmin            :  15.000 ns
  tRCDmin           :  13.125 ns
  tRRDmin           :   6.000 ns
  tRPmin            :  13.125 ns
  tRASmin           :  35.000 ns
  tRCmin            :  48.125 ns
  tRFCmin           : 260.000 ns
  tWTRmin           :   7.500 ns
  tRTPmin           :   7.500 ns
  tFAWmin           :  30.000 ns

CH1S1 SPD:
  Revision           : 11
  Type               : b
  Key                : 2
  Banks              : 8
  Capacity           : 2 Gb
  Supported voltages : 1.5V
  SDRAM width        : 8
  Bus extension      : 0 bits
  Bus width          : 64
  FTB timings        : yes
  Optional features  : DLL-Off_mode RZQ/7 RZQ/6
  Thermal features   : ASR ext_temp_range
  Thermal sensor     : no
  Standard SDRAM     : yes
  Rank1 Address bits : mirrored
  DIMM Reference card: B
  Manufacturer ID    : cd04
  Part number        : F3-2400C10-4GTX
  Row    addr bits  : 15
  Column addr bits  : 10
  Number of ranks   : 2
  DIMM Capacity     : 4096 MB
  Vdd Min           : 1500 mV
  Vdd Max           : 1500 mV
  CAS latencies     : 6 7 8 9 10 11
  tCKmin            :   1.250 ns
  tAAmin            :  13.125 ns
  tWRmin            :  15.000 ns
  tRCDmin           :  13.125 ns
  tRRDmin           :   6.000 ns
  tRPmin            :  13.125 ns
  tRASmin           :  35.000 ns
  tRCmin            :  48.125 ns
  tRFCmin           : 160.000 ns
  tWTRmin           :   7.500 ns
  tRTPmin           :   7.500 ns
  tFAWmin           :  30.000 ns


Executing raminit task INITMPLL
PLL_REF100_CFG value: 0x2
100MHz reference clock support: yes
With tCK 320, try CAS: 11 OK
Found compatible clock / CAS settings
Selected DRAM frequency: 800 MHz
Selected CAS latency   : 11T
MC_BIOS_REQ = 0x80000006
MPLL busy... done in 11 us
MC_BIOS_DATA = 0x00000006
MPLL frequency is set to: 800 MHz (period: 1250000 femtoseconds)
Quadrature clock period: 625 picoseconds


Executing raminit task CONVTIM
tCMD was zero, picking a guesstimate value
Selected tCK          : 1250 ps
Selected tAA          : 11T
Selected tWR          : 12T
Selected tRCD         : 11T
Selected tRRD         : 5T
Selected tRP          : 11T
Selected tRAS         : 28T
Selected tRC          : 39T
Selected tRFC         : 208T
Selected tWTR         : 6T
Selected tRTP         : 6T
Selected tFAW         : 24T
Selected tCWL         : 8T
Selected tCMD         : 2T
Selected tREFI        : 6240T
Selected tXP          : 5T


Executing raminit task CONFMC


Executing raminit task MEMMAP
ME: Requested 16MB UMA
============ MEMORY MAP ============

dpr_size       = 0 MiB
tseg_size      = 8 MiB
gtt_size       = 2 MiB
gms_size       = 64 MiB
me_stolen_size = 16 MiB

touud          = 18350 MiB
remaplimit     = 18349 MiB
remapbase      = 16368 MiB
tom            = 16384 MiB
tom_minus_me   = 16368 MiB
tolud          = 2114 MiB
bdsm_base      = 2050 MiB
gtt_base       = 2048 MiB
tseg_base      = 2040 MiB

reclaim_possible = Yes


Executing raminit task JEDECINIT


Executing raminit task PRETRAIN
C0S0:
	MR0: 0x0d70
	MR1: 0x0006
	MR2: 0x0298
	MR3: 0x0000

C0S1:
	MR0: 0x0d70
	MR1: 0x0006
	MR2: 0x0298
	MR3: 0x0000

C1S0:
	MR0: 0x0d70
	MR1: 0x0006
	MR2: 0x0298
	MR3: 0x0000

C1S1:
	MR0: 0x0d70
	MR1: 0x0006
	MR2: 0x0298
	MR3: 0x0000



Executing raminit task SOT
Stage 1: Vref offset training
Plot of sum_bits across Vref settings
Channel	0			1		
Byte	0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
1/2 Vref
-15	0 0 0 0 0 0 0 0 	0 0 0 0 0 0 0 0 
-14	0 0 0 0 0 0 0 0 	0 0 0 0 0 0 0 0 
-13	0 0 0 0 0 0 0 0 	0 0 0 0 0 0 0 0 
-12	0 0 0 0 0 0 0 0 	0 0 0 0 0 0 0 0 
-11	0 0 0 0 0 0 0 0 	0 0 0 0 0 0 0 0 
-10	0 0 0 0 0 0 0 0 	0 0 0 0 0 0 0 0 
 -9	0 0 0 0 0 0 0 0 	0 0 0 0 0 0 0 0 
 -8	0 0 0 0 0 1 0 0 	0 0 0 0 0 0 0 0 
 -7	0 0 2 0 0 1 1 0 	0 0 0 2 0 0 0 0 
 -6	2 0 3 1 1 2 1 4 	3 3 3 2 0 0 1 1 
 -5	5 3 6 5 2 4 6 6 	3 4 5 7 1 3 4 6 
 -4	8 7 8 8 4 8 6 8 	6 7 7 8 3 7 7 7 
 -3	8 8 8 8 7 8 8 8 	8 8 7 8 8 8 8 8 
 -2	8 8 8 8 8 8 8 8 	8 8 8 8 8 8 8 8 
 -1	8 8 8 8 8 8 8 8 	8 8 8 8 8 8 8 8 
  0	8 8 8 8 8 8 8 8 	8 8 8 8 8 8 8 8 
  1	8 8 8 8 8 8 8 8 	8 8 8 8 8 8 8 8 
  2	8 8 8 8 8 8 8 8 	8 8 8 8 8 8 8 8 
  3	8 8 8 8 8 8 8 8 	8 8 8 8 8 8 8 8 
  4	8 8 8 8 8 8 8 8 	8 8 8 8 8 8 8 8 
  5	8 8 8 8 8 8 8 8 	8 8 8 8 8 8 8 8 
  6	8 8 8 8 8 8 8 8 	8 8 8 8 8 8 8 8 
  7	8 8 8 8 8 8 7 8 	8 8 7 6 8 8 8 8 
  8	5 8 8 7 8 6 5 6 	5 4 6 6 8 7 8 8 
  9	2 5 1 5 7 6 2 3 	4 4 4 5 7 5 8 6 
 10	0 2 0 0 4 4 2 2 	1 1 1 0 6 1 3 2 
 11	0 0 0 0 1 1 0 1 	0 1 1 0 2 0 0 0 
 12	0 0 0 0 1 0 0 0 	0 0 0 0 0 0 0 0 
 13	0 0 0 0 0 0 0 0 	0 0 0 0 0 0 0 0 
 14	0 0 0 0 0 0 0 0 	0 0 0 0 0 0 0 0 
 15	0 0 0 0 0 0 0 0 	0 0 0 0 0 0 0 0 

Hi-Lo (XOR):
  C0:	0xff	0xff	0xff	0xff	0xff	0xff	0xff	0xff
  C1:	0xff	0xff	0xff	0xff	0xff	0xff	0xff	0xff

RdVref:
  C0:	   1	   1	   1	   1	   2	   1	   1	   1
  C1:	   1	   1	   1	   1	   1	   1	   2	   1

Stage 2: Samp offset training
Channel 0                                                                         1                                                                         
Byte    0        1        2        3        4        5        6        7          0        1        2        3        4        5        6        7          
Bits    01234567 01234567 01234567 01234567 01234567 01234567 01234567 01234567   01234567 01234567 01234567 01234567 01234567 01234567 01234567 01234567   
 SAmp
    1	........ ........ ........ ........ ........ ........ ........ ........   ........ ........ ........ ........ ........ ........ ........ ........   
    2	........ ........ ........ ........ ........ ........ ........ ........   ........ ........ ........ ........ ........ ........ ........ ........   
    3	........ ........ ........ ........ ........ ........ ........ ........   ........ ........ ........ ........ ........ ........ ........ ........   
    4	........ ........ ........ ........ ........ ........ ........ ........   ........ ........ ........ ........ ........ ........ ........ ........   
    5	........ ........ ........ ........ .#...... ........ ........ ........   ........ ........ ........ ........ ........ ........ ........ ........   
    6	........ ........ ........ ........ .##....# ....#... .....#.. ........   ........ #....... .#...... .#...#.. ........ ........ .#...#.. ........   
    7	##....#. ........ ##...### .....#.# ###....# .#..#... ..#..#.# .#...#.#   #....... #.....## .#...... .#..##.. ........ ........ .#####.# ........   
    8	####..## ....###. ##.##### ##...### ###.#### .#..#... ..###### .##.##.#   #...##.. #..#..## .##..### .####### #....... ..##.#.. ######## #..#..##   
    9	######## #.###### ######## ######## ######## ######## ..###### ######.#   #######. ####.### ###.#### ######## #..####. ######## ######## ########   
   10	######## ######## ######## ######## ######## ######## ######## ########   ######## ######## ###.#### ######## ######## ######## ######## ########   
   11	######## ######## ######## ######## ######## ######## ######## ########   ######## ######## ######## ######## ######## ######## ######## ########   
   12	######## ######## ######## ######## ######## ######## ######## ########   ######## ######## ######## ######## ######## ######## ######## ########   
   13	######## ######## ######## ######## ######## ######## ######## ########   ######## ######## ######## ######## ######## ######## ######## ########   
   14	######## ######## ######## ######## ######## ######## ######## ########   ######## ######## ######## ######## ######## ######## ######## ########   
   15	######## ######## ######## ######## ######## ######## ######## ########   ######## ######## ######## ######## ######## ######## ######## ########   

BitSAmp 66778867 89887778 66877666 77888676 64587775 86885888 99677576 86787696   68887789 58879866 857a8777 85776577 79988889 88778788 75666576 78878877   


Executing raminit task RCVET
Rank 0
Steps 1 and 2: Find middle of high region
Byte	0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
RcvEn
  280	. . . # # # # . 	# # # # . . . # 
  288	. . . # # # # . 	# # # # . . . . 
  296	. . . . # # # # 	# # # # # . . . 
  304	. . . . . # # # 	# # # # # . . . 
  312	. . . . . # # # 	. # # # # # . . 
  320	# . . . . # # # 	. # # # # # . . 
  328	# . . . . . # # 	. . # # # # . . 
  336	# # . . . . . # 	. . . # # # # . 
  344	# # # . . . . # 	. . . . # # # . 
  352	# # # . . . . # 	. . . . # # # # 
  360	# # # # . . . . 	. . . . . # # # 
  368	# # # # # . . . 	. . . . . # # # 
  376	# # # # # . . . 	# . . . . . # # 
  384	. # # # # . . . 	# . . . . . # # 
  392	. # # # # # . . 	# # . . . . # # 
  400	. . # # # # # . 	# # # . . . . # 

Update RcvEn timing to be in the center of high region
C0.R0: 	Left	Right	Width	Center
   B0: 	256	312	56	284
   B1: 	272	328	56	300
   B2: 	280	336	56	308
   B3: 	296	352	56	324
   B4: 	304	360	56	332
   B5: 	328	384	56	356
   B6: 	336	392	56	364
   B7: 	232	288	56	260

C1.R0: 	Left	Right	Width	Center
   B0: 	312	368	56	340
   B1: 	328	384	56	356
   B2: 	336	392	56	364
   B3: 	344	400	56	372
   B4: 	232	288	56	260
   B5: 	248	304	56	276
   B6: 	272	328	56	300
   B7: 	288	344	56	316

Step 3: Quarter preamble - Walk backwards
Byte	0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
IOLAT
   0	H H H H H H H H    0	H H H H H H H H 
   2	H H H H H H H H    2	H H H H H H H H 
   4	H H H H H H H H    4	H H H H H H H H 
   6	H H H H H H H L    6	H H H H L L L L 
   6	L L L L L L L L    6	L L L L L L L L 

C0:  Preamble
 B0: 156
 B1: 172
 B2: 180
 B3: 196
 B4: 204
 B5: 228
 B6: 236
 B7: 260

C1:  Preamble
 B0: 212
 B1: 228
 B2: 236
 B3: 244
 B4: 260
 B5: 276
 B6: 300
 B7: 316

Step 4: Add 1 qclk

Step 5: Walk forward to find rising edge
Byte	0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
 inc
  0	# # # # # # # # 	# # # # # # # # 	
  1	# # # # # # # # 	# # # # # # # # 	
  2	# # # # # # # # 	# # # # # # # # 	
  3	# # # # # # # # 	# # # # # # # # 	
  4	# # # # # # # # 	# # # # # # # # 	
  5	# # # # # # # # 	# # # # # # # # 	
  6	# # # # # # # # 	# # # # # # # # 	
  7	# # # # # # # # 	# # # # # # # # 	
  8	# # # # # # # # 	# # # # # # # # 	
  9	# # # # # # # # 	# # # # # # # # 	
 10	# # # # # # # # 	# # # # # # # # 	
 11	# # # # # # # # 	# # # # # # # # 	
 12	# # # # # # # # 	# # # # # # # # 	
 13	# # # # # # # # 	# # # # # # # # 	
 14	# # # # # # # # 	# # # # # # # # 	
 15	# # # # # # # # 	# # # # # # # # 	
 16	# # # # # # # # 	# # # # # # # # 	
 17	# # # # # # # # 	# # # # # # # # 	
 18	# # # # # # # # 	# # # # # # # # 	
 19	# # # # # # # # 	# # # # # # # # 	
 20	# # # # # # # # 	# # # # # # # # 	
 21	# # # # # # # # 	# # # # # # # # 	
 22	# # # # # # # # 	# # # # # # # # 	
 23	# # # # # # # # 	# # # # # # # # 	
 24	# # # # # # # # 	# # # # # # # # 	
 25	# # # # # # # # 	# # # # # # # # 	
 26	# # # # # # # # 	# # # # # # # # 	
 27	# # # # # # # # 	# # # # # # # # 	
 28	# # # # # # # # 	# # # # # # # # 	
 29	# # # # # # # # 	# # # # # # # # 	
 30	# # # # # # # # 	# # # # # # # # 	
 31	# # # # # # # # 	# # # # # # # # 	
 32	# # # # # # # # 	. # # # # # # # 	
 33	# # # . # # # # 	. # # # # # # # 	
 34	. # # . # . # # 	. # # # # # . # 	
 35	. . # . # . # # 	. . . # # # . . 	
 36	. . # . # . # # 	. . . . # . . . 	
 37	. . . . # . # # 	. . . . # . . . 	
 38	. . . . . . . # 	. . . . # . . . 	
 39	. . . . . . . # 	. . . . . . . . 	
 40	. . . . . . . . 	. . . . . . . . 	

Step 6: center on preamble and clean up rank
C0:  Preamble increment
 B0: 190      33
 B1: 207      34
 B2: 217      36
 B3: 229      32
 B4: 242      37
 B5: 262      33
 B6: 274      37
 B7: 300      39

C1:  Preamble increment
 B0: 244      31
 B1: 263      34
 B2: 271      34
 B3: 280      35
 B4: 299      38
 B5: 312      35
 B6: 334      33
 B7: 351      34


Rank 2
Steps 1 and 2: Find middle of high region
Byte	0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
RcvEn
  280	. # # # # # . . 	# # . . . . . # 
  288	. . # # # # # . 	# # # . . . . # 
  296	. . # # # # # . 	# # # # . . . . 
  304	. . . # # # # . 	# # # # # . . . 
  312	. . . . # # # # 	# # # # # . . . 
  320	. . . . . # # # 	. # # # # # . . 
  328	. . . . . # # # 	. # # # # # . . 
  336	# . . . . . # # 	. # # # # # . . 
  344	# . . . . . # # 	. . # # # # # . 
  352	# # . . . . . # 	. . . # # # # . 
  360	# # . . . . . # 	. . . . # # # # 
  368	# # # . . . . # 	. . . . # # # # 
  376	# # # # . . . . 	. . . . . # # # 
  384	# # # # # . . . 	# . . . . . # # 
  392	# # # # # . . . 	# . . . . . # # 
  400	# # # # # # . . 	# . . . . . # # 

Update RcvEn timing to be in the center of high region
C0.R2: 	Left	Right	Width	Center
   B0: 	280	328	48	304
   B1: 	288	344	56	316
   B2: 	304	360	56	332
   B3: 	312	368	56	340
   B4: 	320	376	56	348
   B5: 	336	392	56	364
   B6: 	224	280	56	252
   B7: 	248	304	56	276

C1.R2: 	Left	Right	Width	Center
   B0: 	320	376	56	348
   B1: 	344	400	56	372
   B2: 	224	280	56	252
   B3: 	232	288	56	260
   B4: 	248	296	48	272
   B5: 	256	312	56	284
   B6: 	280	336	56	308
   B7: 	296	352	56	324

Step 3: Quarter preamble - Walk backwards
Byte	0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
IOLAT
   0	H H H H H H H H    0	H H H H H H H H 
   2	H H H H H H H H    2	H H H H H H H H 
   4	H H H H H H H H    4	H H H H H H H H 
   6	H H H H H H L L    6	H H L L L L L L 
   6	L L L L L L L L    6	L L L L L L L L 

C0:  Preamble
 B0: 176
 B1: 188
 B2: 204
 B3: 212
 B4: 220
 B5: 236
 B6: 252
 B7: 276

C1:  Preamble
 B0: 220
 B1: 244
 B2: 252
 B3: 260
 B4: 272
 B5: 284
 B6: 308
 B7: 324

Step 4: Add 1 qclk

Step 5: Walk forward to find rising edge
Byte	0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
 inc
  0	# # # # # # # # 	# # # # # # # # 	
  1	# # # # # # # # 	# # # # # # # # 	
  2	# # # # # # # # 	# # # # # # # # 	
  3	# # # # # # # # 	# # # # # # # # 	
  4	# # # # # # # # 	# # # # # # # # 	
  5	# # # # # # # # 	# # # # # # # # 	
  6	# # # # # # # # 	# # # # # # # # 	
  7	# # # # # # # # 	# # # # # # # # 	
  8	# # # # # # # # 	# # # # # # # # 	
  9	# # # # # # # # 	# # # # # # # # 	
 10	# # # # # # # # 	# # # # # # # # 	
 11	# # # # # # # # 	# # # # # # # # 	
 12	# # # # # # # # 	# # # # # # # # 	
 13	# # # # # # # # 	# # # # # # # # 	
 14	# # # # # # # # 	# # # # # # # # 	
 15	# # # # # # # # 	# # # # # # # # 	
 16	# # # # # # # # 	# # # # # # # # 	
 17	# # # # # # # # 	# # # # # # # # 	
 18	# # # # # # # # 	# # # # # # # # 	
 19	# # # # # # # # 	# # # # # # # # 	
 20	# # # # # # # # 	# # # # # # # # 	
 21	# # # # # # # # 	# # # # # # # # 	
 22	# # # # # # # # 	# # # # # # # # 	
 23	# # # # # # # # 	# # # # # # # # 	
 24	# # # # # # # # 	# # # # # # # # 	
 25	# # # # # # # # 	# # # # # # # # 	
 26	# # # # # # # # 	# # # # # # # # 	
 27	# # # # # # # # 	# # # # # # # # 	
 28	# # # # # # # # 	# # # # # # # # 	
 29	# # # # # # # # 	# # # # # # # # 	
 30	# # # # # # # # 	# # # # # # # # 	
 31	# # # # # # # # 	# # # # # # # # 	
 32	# . . # # # # # 	# . # # # # # # 	
 33	. . . # # # . . 	# . . # # # # # 	
 34	. . . . . # . . 	# . . # # # # . 	
 35	. . . . . # . . 	# . . # # # . . 	
 36	. . . . . . . . 	# . . . . # . . 	
 37	. . . . . . . . 	# . . . . # . . 	
 38	. . . . . . . . 	. . . . . . . . 	

Step 6: center on preamble and clean up rank
C0:  Preamble increment
 B0: 209      32
 B1: 220      31
 B2: 236      31
 B3: 246      33
 B4: 254      33
 B5: 272      35
 B6: 285      32
 B7: 309      32

C1:  Preamble increment
 B0: 258      37
 B1: 276      31
 B2: 285      32
 B3: 296      35
 B4: 308      35
 B5: 322      37
 B6: 343      34
 B7: 358      33


Rank 3
Steps 1 and 2: Find middle of high region
Byte	0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
RcvEn
  280	. # # # # # . . 	# # . . . . . # 
  288	. . # # # # # . 	# # # . . . . # 
  296	. . # # # # # . 	# # # . . . . # 
  304	. . . # # # # # 	# # # # . . . . 
  312	. . . . # # # # 	# # # # # . . . 
  320	. . . . . # # # 	# # # # # . . . 
  328	. . . . . # # # 	. # # # # # . . 
  336	# . . . . # # # 	. # # # # # . . 
  344	# . . . . . # # 	. . # # # # # . 
  352	# # . . . . . # 	. . . # # # # . 
  360	# # . . . . . # 	. . . . # # # # 
  368	# # # . . . . # 	. . . . # # # # 
  376	# # # # . . . . 	. . . . . # # # 
  384	# # # # # . . . 	# . . . . # # # 
  392	# # # # # . . . 	# . . . . . # # 
  400	# # # # # . . . 	# . . . . . # # 

Update RcvEn timing to be in the center of high region
C0.R3: 	Left	Right	Width	Center
   B0: 	280	328	48	304
   B1: 	288	344	56	316
   B2: 	304	360	56	332
   B3: 	312	368	56	340
   B4: 	320	376	56	348
   B5: 	344	400	56	372
   B6: 	224	280	56	252
   B7: 	248	296	48	272

C1.R3: 	Left	Right	Width	Center
   B0: 	328	376	48	352
   B1: 	344	400	56	372
   B2: 	224	280	56	252
   B3: 	232	296	64	264
   B4: 	248	304	56	276
   B5: 	264	320	56	292
   B6: 	280	336	56	308
   B7: 	304	352	48	328

Step 3: Quarter preamble - Walk backwards
Byte	0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
IOLAT
   0	H H H H H H H H    0	H H H H H H H H 
   2	H H H H H H H H    2	H H H H H H H H 
   4	H H H H H H H H    4	H H H H H H H H 
   6	H H H H H H L L    6	H H L L L L L L 
   6	L L L L L L L L    6	L L L L L L L L 

C0:  Preamble
 B0: 176
 B1: 188
 B2: 204
 B3: 212
 B4: 220
 B5: 244
 B6: 252
 B7: 272

C1:  Preamble
 B0: 224
 B1: 244
 B2: 252
 B3: 264
 B4: 276
 B5: 292
 B6: 308
 B7: 328

Step 4: Add 1 qclk

Step 5: Walk forward to find rising edge
Byte	0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
 inc
  0	# # # # # # # # 	# # # # # # # # 	
  1	# # # # # # # # 	# # # # # # # # 	
  2	# # # # # # # # 	# # # # # # # # 	
  3	# # # # # # # # 	# # # # # # # # 	
  4	# # # # # # # # 	# # # # # # # # 	
  5	# # # # # # # # 	# # # # # # # # 	
  6	# # # # # # # # 	# # # # # # # # 	
  7	# # # # # # # # 	# # # # # # # # 	
  8	# # # # # # # # 	# # # # # # # # 	
  9	# # # # # # # # 	# # # # # # # # 	
 10	# # # # # # # # 	# # # # # # # # 	
 11	# # # # # # # # 	# # # # # # # # 	
 12	# # # # # # # # 	# # # # # # # # 	
 13	# # # # # # # # 	# # # # # # # # 	
 14	# # # # # # # # 	# # # # # # # # 	
 15	# # # # # # # # 	# # # # # # # # 	
 16	# # # # # # # # 	# # # # # # # # 	
 17	# # # # # # # # 	# # # # # # # # 	
 18	# # # # # # # # 	# # # # # # # # 	
 19	# # # # # # # # 	# # # # # # # # 	
 20	# # # # # # # # 	# # # # # # # # 	
 21	# # # # # # # # 	# # # # # # # # 	
 22	# # # # # # # # 	# # # # # # # # 	
 23	# # # # # # # # 	# # # # # # # # 	
 24	# # # # # # # # 	# # # # # # # # 	
 25	# # # # # # # # 	# # # # # # # # 	
 26	# # # # # # # # 	# # # # # # # # 	
 27	# # # # # # # # 	# # # # # # # # 	
 28	# # # # # # # # 	# # # # # # # # 	
 29	# # # # # # # # 	# # # # # # # # 	
 30	# # # # # . # # 	# # # # # # # # 	
 31	# # . # # . # # 	# # # # # . # # 	
 32	# . . # # . # # 	# . # # # . # # 	
 33	# . . # # . # # 	. . # . . . # # 	
 34	. . . . # . . # 	. . # . . . # . 	
 35	. . . . . . . # 	. . # . . . . . 	
 36	. . . . . . . # 	. . . . . . . . 	
 37	. . . . . . . . 	. . . . . . . . 	

Step 6: center on preamble and clean up rank
C0:  Preamble increment
 B0: 210      33
 B1: 220      31
 B2: 235      30
 B3: 246      33
 B4: 255      34
 B5: 274      29
 B6: 286      33
 B7: 309      36

C1:  Preamble increment
 B0: 257      32
 B1: 276      31
 B2: 288      35
 B3: 297      32
 B4: 309      32
 B5: 323      30
 B6: 343      34
 B7: 362      33


Step 7: Sync IO latency across all ranks

Final Receive Enable and IO latency settings:
  C0.R0: IOLAT = 7  rt_iocomp = 23
   B0:   254
   B1:   271
   B2:   281
   B3:   293
   B4:   306
   B5:   326
   B6:   338
   B7:   364

  C0.R2: IOLAT = 7  rt_iocomp = 23
   B0:   273
   B1:   284
   B2:   300
   B3:   310
   B4:   318
   B5:   336
   B6:   349
   B7:   373

  C0.R3: IOLAT = 7  rt_iocomp = 23
   B0:   274
   B1:   284
   B2:   299
   B3:   310
   B4:   319
   B5:   338
   B6:   350
   B7:   373

  C1.R0: IOLAT = 6  rt_iocomp = 23
   B0:   244
   B1:   263
   B2:   271
   B3:   280
   B4:   299
   B5:   312
   B6:   334
   B7:   351

  C1.R2: IOLAT = 6  rt_iocomp = 23
   B0:   258
   B1:   276
   B2:   285
   B3:   296
   B4:   308
   B5:   322
   B6:   343
   B7:   358

  C1.R3: IOLAT = 6  rt_iocomp = 23
   B0:   257
   B1:   276
   B2:   288
   B3:   297
   B4:   309
   B5:   323
   B6:   343
   B7:   362



Executing raminit task RDMPRT
Rank 0
Channel	0			1		
Byte	0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
DqsDelay
  -32	# # # # # # # # 	# # # # # # # # 
  -31	# # # # # # # # 	# # # # # # # # 
  -30	# # # # # # # # 	# # # # # # # # 
  -29	# # # # # # # # 	# # # # # # # # 
  -28	# # # # # # # # 	# # # # # # # # 
  -27	# # # # # # # # 	# # # # # # # # 
  -26	# # # # # # # # 	# # # # # # # # 
  -25	# # # # # # # # 	# # # # # # # # 
  -24	# # # # # # # # 	# # # # # # # # 
  -23	# # # # # # # # 	# # # # # # # # 
  -22	# # # # # # # # 	# # # # # # # # 
  -21	# # # # # # # # 	# # # # # # # # 
  -20	# # # # # # # # 	# # # # # # # # 
  -19	# # # # # # # # 	# # # # # # # # 
  -18	# # # # # # # # 	# # # # # # # # 
  -17	# # # # # # # # 	. # # . # # # # 
  -16	# # # # # # # # 	. . # . # # . # 
  -15	# # # # # # # # 	. . # . . # . . 
  -14	# # # # # # # # 	. . . . . # . . 
  -13	# # # # # # # # 	. . . . . # . . 
  -12	# # # . . # . # 	. . . . . . . . 
  -11	# # # . . # . # 	. . . . . . . . 
  -10	# # . . . . . # 	. . . . . . . . 
   -9	# # . . . . . # 	. . . . . . . . 
   -8	# . . . . . . . 	. . . . . . . . 
   -7	# . . . . . . . 	. . . . . . . . 
   -6	. . . . . . . . 	. . . . . . . . 
   -5	. . . . . . . . 	. . . . . . . . 
   -4	. . . . . . . . 	. . . . . . . . 
   -3	. . . . . . . . 	. . . . . . . . 
   -2	. . . . . . . . 	. . . . . . . . 
   -1	. . . . . . . . 	. . . . . . . . 
    0	. . . . . . . . 	. . . . . . . . 
    1	. . . . . . . . 	. . . . . . . . 
    2	. . . . . . . . 	. . . . . . . . 
    3	. . . . . . . . 	. . . . . . . . 
    4	. . . . . . . . 	. . . . . . . . 
    5	. . . . . . . . 	. . . . . . . . 
    6	. . . . . . . . 	. . . . . . . . 
    7	. . . . . . . . 	. . . . . . . . 
    8	. . . . . . . . 	. . . . . . . . 
    9	. . . . . . . . 	. . . . . . . . 
   10	. . . . . . . . 	. . . . . . . . 
   11	. . . . . . . . 	. . . . . . . . 
   12	. . . . . . . . 	. . . . . . . . 
   13	. . . . . . . . 	. . . . . . . . 
   14	. . . . . . . . 	. . . . . . . . 
   15	. . . . . . . . 	. . . . . . . . 
   16	. . . . . . . . 	. . . . . . . . 
   17	. . . . . . . . 	. . . . . . . . 
   18	. . . . . . . . 	. . . . . . . . 
   19	. . . . . . . . 	. . . . . . . . 
   20	. . . . . . . . 	. . . . . . . . 
   21	. . . . . . . . 	. . . . . . . . 
   22	. . . . . . . . 	. . . . . . . . 
   23	. . . . . . . . 	. . . . . . . . 
   24	. . . . . . . . 	. . . . . . . . 
   25	. . . . . . . . 	. . . . . . . . 
   26	. . . . . . . . 	. . . . . . . . 
   27	. . . . . . . . 	. . . . . . . . 
   28	. . . . . . . . 	. . . . . . . . 
   29	. . . . . . . . 	. . . . . . . . 
   30	. . . . . . . . 	. . . . . . . . 
   31	. . . . . . . . 	. . . . . . . . 

C0.R0: 	Left	Right	Width	Center	RxDqsPN
  B0: 	-6	31	37	12	44
  B1: 	-8	31	39	11	43
  B2: 	-10	31	41	10	42
  B3: 	-12	31	43	9	41
  B4: 	-12	31	43	9	41
  B5: 	-10	31	41	10	42
  B6: 	-12	31	43	9	41
  B7: 	-8	31	39	11	43

C1.R0: 	Left	Right	Width	Center	RxDqsPN
  B0: 	-17	31	48	7	39
  B1: 	-16	31	47	7	39
  B2: 	-14	31	45	8	40
  B3: 	-17	31	48	7	39
  B4: 	-15	31	46	8	40
  B5: 	-12	31	43	9	41
  B6: 	-16	31	47	7	39
  B7: 	-15	31	46	8	40

Rank 2
Channel	0			1		
Byte	0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
DqsDelay
  -32	# # # # # # # # 	# # # # # # # # 
  -31	# # # # # # # # 	# # # # # # # # 
  -30	# # # # # # # # 	# # # # # # # # 
  -29	# # # # # # # # 	# # # # # # # # 
  -28	# # # # # # # # 	# # # # # # # # 
  -27	# # # # # # # # 	# # # # # # # # 
  -26	# # # # # # # # 	# # # # # # # # 
  -25	# # # # # # # # 	# # # # # # # # 
  -24	# # # # # # # # 	# # # # # # # # 
  -23	# # # # # # # # 	# # # # # # # # 
  -22	# # # # # # # # 	# # # # # # # # 
  -21	# # # # # # # # 	# # # # # # # # 
  -20	# # # # # # # # 	# # # # # # # # 
  -19	# # # # # # # # 	# # # # # # # # 
  -18	# # # # # # # # 	# # # # # # # # 
  -17	# # # # # # # # 	# # # # # # # # 
  -16	# # # . . # . # 	# # # # # # # # 
  -15	. # . . . . . . 	# # # # # # # # 
  -14	. # . . . . . . 	. # # . # # # # 
  -13	. . . . . . . . 	. . # . # # # # 
  -12	. . . . . . . . 	. . . . # # # # 
  -11	. . . . . . . . 	. . . . . # . # 
  -10	. . . . . . . . 	. . . . . . . . 
   -9	. . . . . . . . 	. . . . . . . . 
   -8	. . . . . . . . 	. . . . . . . . 
   -7	. . . . . . . . 	. . . . . . . . 
   -6	. . . . . . . . 	. . . . . . . . 
   -5	. . . . . . . . 	. . . . . . . . 
   -4	. . . . . . . . 	. . . . . . . . 
   -3	. . . . . . . . 	. . . . . . . . 
   -2	. . . . . . . . 	. . . . . . . . 
   -1	. . . . . . . . 	. . . . . . . . 
    0	. . . . . . . . 	. . . . . . . . 
    1	. . . . . . . . 	. . . . . . . . 
    2	. . . . . . . . 	. . . . . . . . 
    3	. . . . . . . . 	. . . . . . . . 
    4	. . . . . . . . 	. . . . . . . . 
    5	. . . . . . . . 	. . . . . . . . 
    6	. . . . . . . . 	. . . . . . . . 
    7	. . . . . . . . 	. . . . . . . . 
    8	. . . . . . . . 	. . . . . . . . 
    9	. . . . . . . . 	. . . . . . . . 
   10	. . . . . . . . 	. . . . . . . . 
   11	. . . . . . . . 	. . . . . . . . 
   12	. . . . . . . . 	. . . . . . . . 
   13	. . . . . . . . 	. . . . . . . . 
   14	. . . . . . . . 	. . . . . . . . 
   15	. . . . . . . . 	. . . . . . . . 
   16	. . . . . . . . 	. . . . . . . . 
   17	. . . . . . . . 	. . . . . . . . 
   18	. . . . . . . . 	. . . . . . . . 
   19	. . . . . . . . 	. . . . . . . . 
   20	. . . . . . . . 	. . . . . . . . 
   21	. . . . . . . . 	. . . . . . . . 
   22	. . . . . . . . 	. . . . . . . . 
   23	. . . . . . . . 	. . . . . . . . 
   24	. . . . . . . . 	. . . . . . . . 
   25	. . . . . . . . 	. . . . . . . . 
   26	. . . . . . . . 	. . . . . . . . 
   27	. . . . . . . . 	. . . . . . . . 
   28	. . . . . . . . 	. . . . . . . . 
   29	. . . . . . . . 	. . . . . . . . 
   30	. . . . . . . . 	. . . . . . . . 
   31	. . . . . . . . 	. . . . . . . . 

C0.R2: 	Left	Right	Width	Center	RxDqsPN
  B0: 	-15	31	46	8	40
  B1: 	-13	31	44	9	41
  B2: 	-15	31	46	8	40
  B3: 	-16	31	47	7	39
  B4: 	-16	31	47	7	39
  B5: 	-15	31	46	8	40
  B6: 	-16	31	47	7	39
  B7: 	-15	31	46	8	40

C1.R2: 	Left	Right	Width	Center	RxDqsPN
  B0: 	-14	31	45	8	40
  B1: 	-13	31	44	9	41
  B2: 	-12	31	43	9	41
  B3: 	-14	31	45	8	40
  B4: 	-11	31	42	10	42
  B5: 	-10	31	41	10	42
  B6: 	-11	31	42	10	42
  B7: 	-10	31	41	10	42

Rank 3
Channel	0			1		
Byte	0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
DqsDelay
  -32	# # # # # # # # 	# # # # # # # # 
  -31	# # # # # # # # 	# # # # # # # # 
  -30	# # # # # # # # 	# # # # # # # # 
  -29	# # # # # # # # 	# # # # # # # # 
  -28	# # # # # # # # 	# # # # # # # # 
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C0.R3: 	Left	Right	Width	Center	RxDqsPN
  B0: 	-14	31	45	8	40
  B1: 	-12	31	43	9	41
  B2: 	-14	31	45	8	40
  B3: 	-16	31	47	7	39
  B4: 	-16	31	47	7	39
  B5: 	-15	31	46	8	40
  B6: 	-16	31	47	7	39
  B7: 	-15	31	46	8	40

C1.R3: 	Left	Right	Width	Center	RxDqsPN
  B0: 	-13	31	44	9	41
  B1: 	-14	31	45	8	40
  B2: 	-11	31	42	10	42
  B3: 	-14	31	45	8	40
  B4: 	-10	31	41	10	42
  B5: 	-10	31	41	10	42
  B6: 	-11	31	42	10	42
  B7: 	-12	31	43	9	41



Executing raminit task JWRL

Rank 0
Channel	0								1
Byte	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7
WlDelay
 192:	#1	#1	.31	.31	.32	.32	#0	#0	#1	#1	#1	.31	.32	.32	.32	.32
 194:	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	.32	.32
 196:	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	.32	.32
 198:	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	.32	.32
 200:	#0	#0	.32	.32	.32	.32	#0	.31	#0	#0	#0	.32	.32	.32	.32	.32
 202:	#0	#0	.31	.32	.32	.32	#0	.32	#0	#0	#0	.32	.32	.32	.32	.32
 204:	#0	#0	#1	.32	.32	.32	#0	.32	#0	#0	#0	.32	.32	.32	.32	.32
 206:	#0	#0	#0	.32	.32	.32	.23	.32	#0	#0	#0	#6	.32	.32	.32	.32
 208:	#0	#0	#0	.32	.32	.32	.31	.32	#0	#0	#0	#0	.32	.32	.32	.32
 210:	#0	#0	#0	#1	.32	.32	.32	.32	.31	#0	#0	#0	.32	.32	.32	.32
 212:	#0	#0	#0	#0	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32
 214:	#0	#0	#0	#0	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32
 216:	#0	#0	#0	#0	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32
 218:	#0	#0	#0	#0	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32
 220:	.31	#0	#0	#0	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32
 222:	.32	#0	#0	#0	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32
 224:	.32	#0	#0	#0	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32
 226:	.32	#0	#0	#0	.32	.32	.32	.32	.32	#1	#0	#0	.32	.32	.32	.32
 228:	.32	#0	#0	#0	.32	.32	.32	.32	.32	.31	#0	#0	.32	.32	.32	.32
 230:	.32	#0	#0	#0	.32	.32	.32	.32	.32	.32	#0	#0	#1	.32	.32	.32
 232:	.32	#0	#0	#0	.32	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32
 234:	.32	#0	#0	#0	.32	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32
 236:	.32	.31	#0	#0	.32	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32
 238:	.32	.32	#0	#0	.32	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32
 240:	.32	.32	#0	#0	.32	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32
 242:	.32	.32	#0	#0	#1	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32
 244:	.32	.32	#0	#0	#0	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32
 246:	.32	.32	#0	#0	#0	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32
 248:	.32	.32	#0	#0	#0	.32	.32	.32	.32	.32	#11	#0	#0	.32	.32	.32
 250:	.32	.32	#0	#0	#0	.32	.32	.32	.32	.32	.31	#0	#0	#1	.32	.32
 252:	.32	.32	#0	#0	#0	.32	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32
 254:	.32	.32	#0	#0	#0	#1	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32
 256:	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32	.32	#0	#0	#0	#1	.32
 258:	.32	.32	.31	#0	#0	#0	.32	.32	.32	.32	.32	#0	#0	#0	#0	.32
 260:	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32	.32	#0	#0	#0	#0	.32
 262:	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32	.32	.31	#0	#0	#0	.20
 264:	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32	.32	.32	#0	#0	#0	#1
 266:	.32	.32	.32	.31	#0	#0	.32	.32	.32	.32	.32	.32	#0	#0	#0	#0
 268:	.32	.32	.32	.32	#0	#0	.32	.32	.32	.32	.32	.32	#0	#0	#0	#0
 270:	.32	.32	.32	.32	#0	#0	.32	#1	.32	.32	.32	.32	#0	#0	#0	#0
 272:	.32	.32	.32	.32	#0	#0	.32	#0	.32	.32	.32	.32	#0	#0	#0	#0
 274:	.32	.32	.32	.32	#0	#0	.32	#0	.32	.32	.32	.32	#0	#0	#0	#0
 276:	.32	.32	.32	.32	#0	#0	.20	#0	.32	.32	.32	.32	#0	#0	#0	#0
 278:	.32	.32	.32	.32	#0	#0	#1	#0	.32	.32	.32	.32	#0	#0	#0	#0
 280:	.32	.32	.32	.32	#0	#0	#0	#0	#7	.32	.32	.32	#0	#0	#0	#0
 282:	.32	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0
 284:	.32	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0
 286:	.32	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0
 288:	.32	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#3	#0	#0	#0
 290:	.32	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	.31	#0	#0	#0
 292:	#1	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0
 294:	#0	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0
 296:	#0	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0
 298:	#0	.32	.32	.32	#0	#0	#0	#0	#0	#1	.32	.32	.32	#0	#0	#0
 300:	#0	.32	.32	.32	#0	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0
 302:	#0	.32	.32	.32	.31	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0
 304:	#0	.32	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#6	#0	#0
 306:	#0	#1	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	.31	#0	#0
 308:	#0	#0	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0
 310:	#0	#0	.32	.32	.32	.31	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0
 312:	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0
 314:	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32	.31	#0
 316:	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32	.32	#0
 318:	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	#1	.32	.32	.32	.32	#15

	InitSt	InitEn	CurrSt	CurrEn	LargSt	LargEn
C0
   B0:	190	190	220	290	220	290
   B1:	190	190	236	304	236	304
   B2:	192	202	258	330	258	330
   B3:	192	208	266	336	266	336
   B4:	192	240	302	368	302	368
   B5:	192	252	310	380	310	380
   B6:	190	190	206	276	206	276
   B7:	190	190	200	268	200	268
C1
   B0:	190	190	210	278	210	278
   B1:	190	190	228	296	228	296
   B2:	190	190	250	316	250	316
   B3:	192	204	262	332	262	332
   B4:	192	228	290	356	290	356
   B5:	192	248	306	376	306	376
   B6:	192	254	314	382	314	382
   B7:	192	262	192	262	192	262

C0.R0:  LftEdge Width
  B0:   220	70
  B1:   236	68
  B2:   258	72
  B3:   266	70
  B4:   302	66
  B5:   310	70
  B6:   206	70
  B7:   200	68

C1.R0:  LftEdge Width
  B0:   210	68
  B1:   228	68
  B2:   250	66
  B3:   262	70
  B4:   290	66
  B5:   306	70
  B6:   314	68
  B7:   192	70


Rank 2
Channel	0								1
Byte	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7
WlDelay
 192:	.31	#0	#0	#0	.31	.31	.31	.31	#0	#0	#0	#0	.31	.31	.31	.31
 194:	.32	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32
 196:	.32	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32
 198:	.32	#0	#0	#0	#13	.32	.32	.32	.31	#0	#0	#0	.32	.32	.32	.32
 200:	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32
 202:	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#2	.32	.32	.32
 204:	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32
 206:	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32
 208:	.32	#0	#0	#0	#0	#1	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32
 210:	.32	.31	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32
 212:	.32	.32	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32
 214:	.32	.32	#0	#0	#0	#0	.32	.32	.32	.31	#0	#0	#0	.32	.32	.32
 216:	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#4	.32	.32
 218:	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32
 220:	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32
 222:	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32
 224:	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32
 226:	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32
 228:	.32	.32	.31	#0	#0	#0	#1	.32	.32	.32	#0	#0	#0	#0	.32	.32
 230:	.32	.32	.32	#0	#0	#0	#0	#1	.32	.32	#0	#0	#0	#0	.30	.32
 232:	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	#0	#0	#0	#0	#1	.32
 234:	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	#0	#0	#0	#0	#0	.32
 236:	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	#0	#0	#0	#0	#0	.32
 238:	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.31	#0	#0	#0	#0	.32
 240:	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	#1
 242:	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	#0
 244:	#4	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	#0
 246:	#0	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	#0
 248:	#0	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	#0
 250:	#0	.32	.32	.31	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	#0
 252:	#0	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	#0
 254:	#0	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	#0
 256:	#0	.32	.32	.32	#0	#0	#0	#0	#1	.32	.32	.31	#0	#0	#0	#0
 258:	#0	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0
 260:	#0	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0
 262:	#0	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0
 264:	#0	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0
 266:	#0	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0
 268:	#0	#1	.32	.32	#8	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0
 270:	#0	#0	.32	.32	.31	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0
 272:	#0	#0	.32	.32	.32	#0	#0	#0	#0	.26	.32	.32	.18	#0	#0	#0
 274:	#0	#0	.32	.32	.32	#0	#0	#0	#0	#1	.32	.32	.31	#0	#0	#0
 276:	#0	#0	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0
 278:	#0	#0	.32	.32	.32	.31	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0
 280:	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0
 282:	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0
 284:	#0	#0	.19	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0
 286:	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0
 288:	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	.31	#0	#0
 290:	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0
 292:	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0
 294:	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0
 296:	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	#1	.32	.32	.32	#0	#0
 298:	#0	#0	#0	.32	.32	.32	.18	#0	#0	#0	#0	.32	.32	.32	#0	#0
 300:	#0	#0	#0	.32	.32	.32	.31	.31	#0	#0	#0	.32	.32	.32	.20	#0
 302:	#0	#0	#0	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.31	#0
 304:	#0	#0	#0	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32	#0
 306:	#0	#0	#0	#1	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32	#0
 308:	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32	.19
 310:	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32	.32
 312:	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32	.32
 314:	.27	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#1	.32	.32	.32	.32
 316:	.32	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32
 318:	.32	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32

	InitSt	InitEn	CurrSt	CurrEn	LargSt	LargEn
C0
   B0:	192	242	314	370	314	370
   B1:	190	190	210	266	210	266
   B2:	190	190	228	284	228	284
   B3:	190	190	250	304	250	304
   B4:	192	196	270	324	270	324
   B5:	192	206	278	334	278	334
   B6:	192	226	298	354	298	354
   B7:	192	228	300	356	300	356
C1
   B0:	190	190	198	254	198	254
   B1:	190	190	214	272	214	272
   B2:	190	190	238	294	238	294
   B3:	190	190	256	312	256	312
   B4:	192	200	272	328	272	328
   B5:	192	214	288	342	288	342
   B6:	192	230	300	358	300	358
   B7:	192	238	308	366	308	366

C0.R2:  LftEdge Width
  B0:   314	56
  B1:   210	56
  B2:   228	56
  B3:   250	54
  B4:   270	54
  B5:   278	56
  B6:   298	56
  B7:   300	56

C1.R2:  LftEdge Width
  B0:   198	56
  B1:   214	58
  B2:   238	56
  B3:   256	56
  B4:   272	56
  B5:   288	54
  B6:   300	58
  B7:   308	58


Rank 3
Channel	0								1
Byte	0	1	2	3	4	5	6	7	0	1	2	3	4	5	6	7
WlDelay
 192:	.31	#0	#0	#0	.31	.31	.31	.31	#0	#0	#0	#0	.31	.31	.31	.31
 194:	.32	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32
 196:	.32	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32
 198:	.32	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32
 200:	.32	#0	#0	#0	.32	.32	.32	.32	.31	#0	#0	#0	.32	.32	.32	.32
 202:	.32	#0	#0	#0	#1	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32
 204:	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#1	.32	.32	.32
 206:	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32
 208:	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32
 210:	.32	.31	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32
 212:	.32	.32	#0	#0	#0	#1	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32
 214:	.32	.32	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32
 216:	.32	.32	#0	#0	#0	#0	.32	.32	.32	.16	#0	#0	#0	.32	.32	.32
 218:	.32	.32	#0	#0	#0	#0	.32	.32	.32	.31	#0	#0	#0	.32	.32	.32
 220:	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32
 222:	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#1	.32	.32
 224:	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32
 226:	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32
 228:	.32	.32	#0	#0	#0	#0	.26	.32	.32	.32	#0	#0	#0	#0	.32	.32
 230:	.32	.32	.29	#0	#0	#0	#1	.32	.32	.32	#0	#0	#0	#0	.32	.32
 232:	.32	.32	.32	#0	#0	#0	#0	#1	.32	.32	#0	#0	#0	#0	#3	.32
 234:	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	#0	#0	#0	#0	#0	.32
 236:	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	#0	#0	#0	#0	#0	.32
 238:	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.31	#0	#0	#0	#0	.32
 240:	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	#11
 242:	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	#1
 244:	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	#0
 246:	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	#0
 248:	#1	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	#0
 250:	#0	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	#0
 252:	#0	.32	.32	.31	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	#0
 254:	#0	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	#0
 256:	#0	.32	.32	.32	#0	#0	#0	#0	#10	.32	.32	#0	#0	#0	#0	#0
 258:	#0	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.31	#0	#0	#0	#0
 260:	#0	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0
 262:	#0	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0
 264:	#0	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0
 266:	#0	.32	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0
 268:	#0	#1	.32	.32	#0	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0
 270:	#0	#0	.32	.32	.29	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0
 272:	#0	#0	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0
 274:	#0	#0	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	.31	#0	#0	#0
 276:	#0	#0	.32	.32	.32	#0	#0	#0	#0	#1	.32	.32	.32	#0	#0	#0
 278:	#0	#0	.32	.32	.32	#1	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0
 280:	#0	#0	.32	.32	.32	.31	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0
 282:	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0
 284:	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0
 286:	#0	#0	.32	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0
 288:	#0	#0	#1	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	#0	#0	#0
 290:	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	.31	#0	#0
 292:	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0
 294:	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0
 296:	#0	#0	#0	.32	.32	.32	#0	#0	#0	#0	#1	.32	.32	.32	#0	#0
 298:	#0	#0	#0	.32	.32	.32	.31	#0	#0	#0	#0	.32	.32	.32	#0	#0
 300:	#0	#0	#0	.32	.32	.32	.32	#8	#0	#0	#0	.32	.32	.32	#0	#0
 302:	#0	#0	#0	.32	.32	.32	.32	.31	#0	#0	#0	.32	.32	.32	.30	#0
 304:	#0	#0	#0	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.31	#0
 306:	#0	#0	#0	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32	#0
 308:	#0	#0	#0	.32	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32	#0
 310:	#0	#0	#0	#1	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32	.31
 312:	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32	.32
 314:	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32	.32
 316:	#0	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	.32	.32	.32	.32	.32
 318:	.31	#0	#0	#0	.32	.32	.32	.32	#0	#0	#0	#1	.32	.32	.32	.32

	InitSt	InitEn	CurrSt	CurrEn	LargSt	LargEn
C0
   B0:	192	246	318	374	318	374
   B1:	190	190	210	266	210	266
   B2:	190	190	230	286	230	286
   B3:	190	190	252	308	252	308
   B4:	192	200	270	328	270	328
   B5:	192	210	280	338	280	338
   B6:	192	228	298	356	298	356
   B7:	192	230	302	358	302	358
C1
   B0:	190	190	200	254	200	254
   B1:	190	190	216	274	216	274
   B2:	190	190	238	294	238	294
   B3:	190	190	258	316	258	316
   B4:	192	202	274	330	274	330
   B5:	192	220	290	348	290	348
   B6:	192	230	302	358	302	358
   B7:	192	238	310	366	310	366

C0.R3:  LftEdge Width
  B0:   318	56
  B1:   210	56
  B2:   230	56
  B3:   252	56
  B4:   270	58
  B5:   280	58
  B6:   298	58
  B7:   302	56

C1.R3:  LftEdge Width
  B0:   200	54
  B1:   216	58
  B2:   238	56
  B3:   258	58
  B4:   274	56
  B5:   290	58
  B6:   302	56
  B7:   310	56

Rank 0
Channel		0			1	
Byte		0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
Delay DqOffset
  0	  0	# # # # # # # # 	# # # # # # # # 
  0	-10	# # # # # # # # 	# # # # # # # # 
  0	 10	# # # # # # # # 	# # # # # # # # 
  0	 -5	# # # # # # # # 	# # # # # # # # 
  0	  5	# # # # # # # # 	# # # # # # # # 
  0	-15	# # # # # # # # 	# # # # # # # # 
  0	 15	# # # # # # # # 	# # # # # # # # 
  1	  0	. . . . . . # # 	. . . . . . . # 
  1	-10	. . . . . . # # 	. . . . . . . # 
  1	 10	. . . . . . # # 	. . . . . . . # 
  1	 -5	. . . . . . # # 	. . . . . . . # 
  1	  5	. . . . . . # # 	. . . . . . . # 
  1	-15	. . . . . . # # 	. . . . . . . # 
  1	 15	. . . . . . # # 	. . . . . . . # 
 -1	  0	# # # # # # # # 	# # # # # # # # 
 -1	-10	# # # # # # # # 	# # # # # # # # 
 -1	 10	# # # # # # # # 	# # # # # # # # 
 -1	 -5	# # # # # # # # 	# # # # # # # # 
 -1	  5	# # # # # # # # 	# # # # # # # # 
 -1	-15	# # # # # # # # 	# # # # # # # # 
 -1	 15	# # # # # # # # 	# # # # # # # # 
  2	  0	# # # # # # . . 	# # # # # # # . 

C0.R0:  Offset	FinalEdge
  B0:   0	220
  B1:   0	236
  B2:   0	258
  B3:   0	266
  B4:   0	302
  B5:   0	310
  B6:   128	334
  B7:   128	328

C1.R0:  Offset	FinalEdge
  B0:   0	210
  B1:   0	228
  B2:   0	250
  B3:   0	262
  B4:   0	290
  B5:   0	306
  B6:   0	314
  B7:   128	320


Rank 2
Channel		0			1	
Byte		0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
Delay DqOffset
  0	  0	. # # # # # # # 	# # # # # # # # 
  0	-10	. # # # # # # # 	# # # # # # # # 
  0	 10	. # # # # # # # 	# # # # # # # # 
  0	 -5	. # # # # # # # 	# # # # # # # # 
  0	  5	. # # # # # # # 	# # # # # # # # 
  0	-15	. # # # # # # # 	# # # # # # # # 
  0	 15	. # # # # # # # 	# # # # # # # # 
  1	  0	# . . . . . . . 	. . . . . . . . 

C0.R2:  Offset	FinalEdge
  B0:   -128	186
  B1:   0	210
  B2:   0	228
  B3:   0	250
  B4:   0	270
  B5:   0	278
  B6:   0	298
  B7:   0	300

C1.R2:  Offset	FinalEdge
  B0:   0	198
  B1:   0	214
  B2:   0	238
  B3:   0	256
  B4:   0	272
  B5:   0	288
  B6:   0	300
  B7:   0	308


Rank 3
Channel		0			1	
Byte		0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
Delay DqOffset
  0	  0	. # # # # # # # 	# # # # # # # # 
  0	-10	. # # # # # # # 	# # # # # # # # 
  0	 10	. # # # # # # # 	# # # # # # # # 
  0	 -5	. # # # # # # # 	# # # # # # # # 
  0	  5	. # # # # # # # 	# # # # # # # # 
  0	-15	. # # # # # # # 	# # # # # # # # 
  0	 15	. # # # # # # # 	# # # # # # # # 
  1	  0	# . . . . . . . 	. . . . . . . . 

C0.R3:  Offset	FinalEdge
  B0:   -128	190
  B1:   0	210
  B2:   0	230
  B3:   0	252
  B4:   0	270
  B5:   0	280
  B6:   0	298
  B7:   0	302

C1.R3:  Offset	FinalEdge
  B0:   0	200
  B1:   0	216
  B2:   0	238
  B3:   0	258
  B4:   0	274
  B5:   0	290
  B6:   0	302
  B7:   0	310




Executing raminit task WRTC1D
Rank 0
Channel	0			1		
Byte	0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
WrDqsDelay
  -31	. . . . . . . . 	# # # # # # # # 
  -30	. . . . . . . . 	# # # # # # # # 
  -29	. . . . . . . . 	# # # # # # # # 
  -28	. . . . . . . . 	# # # # # # # # 
  -27	. . . . . . . . 	# # # # # # # # 
  -26	. . . . . . . . 	# # # . # # # # 
  -25	. . . . . . . . 	. # . . . # # # 
  -24	. . . . . . . . 	. # . . . . # # 
  -23	. . . . . . . . 	. . . . . . . . 
  -22	. . . . . . . . 	. . . . . . . . 
  -21	. . . . . . . . 	. . . . . . . . 
  -20	. . . . . . . . 	. . . . . . . . 
  -19	. . . . . . . . 	. . . . . . . . 
  -18	. . . . . . . . 	. . . . . . . . 
  -17	. . . . . . . . 	. . . . . . . . 
  -16	. . . . . . . . 	. . . . . . . . 
  -15	. . . . . . . . 	. . . . . . . . 
  -14	. . . . . . . . 	. . . . . . . . 
  -13	. . . . . . . . 	. . . . . . . . 
  -12	. . . . . . . . 	. . . . . . . . 
  -11	. . . . . . . . 	. . . . . . . . 
  -10	. . . . . . . . 	. . . . . . . . 
   -9	. . . . . . . . 	. . . . . . . . 
   -8	. . . . . . . . 	. . . . . . . . 
   -7	. . . . . . . . 	. . . . . . . . 
   -6	. . . . . . . . 	. . . . . . . . 
   -5	. . . . . . . . 	. . . . . . . . 
   -4	. . . . . . . . 	. . . . . . . . 
   -3	. . . . . . . . 	. . . . . . . . 
   -2	. . . . . . . . 	. . . . . . . . 
   -1	. . . . . . . . 	. . . . . . . . 
    0	. . . . . . . . 	. . . . . . . . 
    1	. . . . . . . . 	. . . . . . . . 
    2	. . . . . . . . 	. . . . . . . . 
    3	. . . . . . . . 	. . . . . . . . 
    4	. . . . . . . . 	. . . . . . . . 
    5	. . . . . . . . 	. . . . . . . . 
    6	. . . . . . . . 	. . . . . . . . 
    7	. . . . . . . . 	. . . . . . . . 
    8	. . . . . . . . 	. . . . . . . . 
    9	. . . . . . . . 	. . . . . . . . 
   10	. . . . . . . . 	. . . . . . . . 
   11	. # . . . # # . 	. . . . . . . . 
   12	# # . . . # # . 	. . . . . . . . 
   13	# # # . # # # . 	. . . . . . . . 
   14	# # # # # # # # 	. . . . . # . . 
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Channel 0
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WrDqsDelay
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C0.R2:  Left	Right	Width	Center
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   22	....#.#.....#.##..###.##............#.##..#.##..##.#######.###.#
   23	##.##.###.#.#.##########.#.....#....####.##.##.###.#######.#####
   24	#########.################...#.#.###############################
   25	###########################.####.###############################
   26	################################################################
   27	################################################################
   28	################################################################
   29	################################################################
   30	################################################################
   31	################################################################

C0.R3:  Left	Right	Width	Center
  B0:   -24	24	48	0
  B1:   -24	22	46	-1
  B2:   -24	23	47	-1
  B3:   -27	21	48	-3
  B4:   -26	21	47	-3
  B5:   -24	22	46	-1
  B6:   -24	21	45	-2
  B7:   -22	22	44	0

C1.R3:  Left	Right	Width	Center
  B0:   -26	21	47	-3
  B1:   -25	19	44	-3
  B2:   -24	19	43	-3
  B3:   -28	22	50	-3
  B4:   -27	20	47	-4
  B5:   -27	21	48	-3
  B6:   -27	17	44	-5
  B7:   -26	19	45	-4



Executing raminit task RDTC1D
Rank 0
Channel	0			1		
Byte	0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
RdDqsDelay
  -31	# # # # # # # # 	# # # # # # # # 
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  -20	# # # # # # # # 	# # # # # # # # 
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   29	. . . . . . . . 	. . . . . . . # 
   30	. . . . . . . . 	# # . . . . . # 
   31	. . . . . . . . 	# # . . . . . # 

Bit lane information
Channel 0
Byte    0       1       2       3       4       5       6       7       
Bit     0123456701234567012345670123456701234567012345670123456701234567
RdDqsDelay
  -31	################################################################
  -30	################################################################
  -29	################################################################
  -28	################################################################
  -27	################################################################
  -26	################################################################
  -25	################################################################
  -24	################################################################
  -23	################################################################
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  -14	################################################################
  -13	################################################################
  -12	################################################################
  -11	################################################################
  -10	#################################.##############################
   -9	#################################.##..##########################
   -8	##############################..#.#.....########################
   -7	########################.#.#.#..........####.###################
   -6	################.###.###.#................##.##.###..###########
   -5	######.#######.#.##..#....................##..#.###.....########
   -4	###.##.#######.#.##..#....................#......##.....#######.
   -3	.##..#.#.###.#.#..#......................................######.
   -2	..#.......##..............................................#.###.
   -1	..#.......#...............................................#.....
    0	..........#.....................................................
    1	................................................................
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   31	................................................................

Channel 1
Byte    0       1       2       3       4       5       6       7       
Bit     0123456701234567012345670123456701234567012345670123456701234567
RdDqsDelay
  -31	################################################################
  -30	################################################################
  -29	################################################################
  -28	################################################################
  -27	################################################################
  -26	################################################################
  -25	################################################################
  -24	################################################################
  -23	################################################################
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  -20	################################################################
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  -18	################################################################
  -17	################################################################
  -16	################################################################
  -15	################################################################
  -14	####.########################.##################################
  -13	.###..#######################.#.########.##################..###
  -12	..#...#..####.##.#########..#.#..##..###.###############.##..###
  -11	..........#.#.##..##.###.........##..###.##########.#..........#
  -10	..............#...##.##...........#..###.#.#####..#.............
   -9	..............#...##..#...........#..###.#..###...#.............
   -8	......................#..............#...#..#.#...#.............
   -7	......................#..................#....#.................
   -6	......................#.........................................
   -5	................................................................
   -4	................................................................
   -3	................................................................
   -2	................................................................
   -1	................................................................
    0	................................................................
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   28	................................................................
   29	.........................................................#......
   30	...#..##.......#.........................................###.#.#
   31	.#.##.##.#..##.#.........................................###.###

C0.R0:  Left	Right	Width	Center
  B0:   0	31	31	15
  B1:   1	31	30	16
  B2:   -2	31	33	14
  B3:   -5	31	36	13
  B4:   -7	31	38	12
  B5:   -3	31	34	14
  B6:   -3	31	34	14
  B7:   0	31	31	15

C1.R0:  Left	Right	Width	Center
  B0:   -11	29	40	9
  B1:   -8	29	37	10
  B2:   -5	31	36	13
  B3:   -11	31	42	10
  B4:   -7	31	38	12
  B5:   -6	31	37	12
  B6:   -7	31	38	12
  B7:   -10	28	38	9

Rank 2
Channel	0			1		
Byte	0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
RdDqsDelay
  -31	# # # # # # # # 	# # # # # # # # 
  -30	# # # # # # # # 	# # # # # # # # 
  -29	# # # # # # # # 	# # # # # # # # 
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  -17	# # # # # # # # 	# # # # # # # # 
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  -12	. # # . . # . # 	# # # # # # # # 
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   30	. . . . . . . . 	. . . . . . . . 
   31	. # # . . # . . 	. . . . . . . . 

Bit lane information
Channel 0
Byte    0       1       2       3       4       5       6       7       
Bit     0123456701234567012345670123456701234567012345670123456701234567
RdDqsDelay
  -31	################################################################
  -30	################################################################
  -29	################################################################
  -28	################################################################
  -27	################################################################
  -26	################################################################
  -25	################################################################
  -24	################################################################
  -23	################################################################
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  -20	################################################################
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  -18	################################################################
  -17	################################################################
  -16	.###############################..######..######################
  -15	..#..###########.#########.#####....#.##..#..###.#.#####.#######
  -14	.....#.#..###..#.##..#####..####....#.##......##....#.##..#.####
  -13	...........##..#.....#.......#........##......##..........#.####
  -12	...............#.....#........................#.............#.#.
  -11	................................................................
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   31	.............#.......#.......................#..................

Channel 1
Byte    0       1       2       3       4       5       6       7       
Bit     0123456701234567012345670123456701234567012345670123456701234567
RdDqsDelay
  -31	################################################################
  -30	################################################################
  -29	################################################################
  -28	################################################################
  -27	################################################################
  -26	################################################################
  -25	################################################################
  -24	################################################################
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  -20	################################################################
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  -18	################################################################
  -17	################################################################
  -16	################################################################
  -15	.#######.#######################################################
  -14	.#.##.##..######################################################
  -13	.#....##..#.#.##################.###############################
  -12	......#.....#.##..###.##.##.#.##.#######.##.########.#####.#.###
  -11	............#..#..###.##.#..#....##.####.##.#####..#.##.##.#.#.#
  -10	...................#................#.##.##.###.#..........#....
   -9	...................#..................##....#.#.................
   -8	......................................#.........................
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   31	................................................................

C0.R2:  Left	Right	Width	Center
  B0:   -13	31	44	9
  B1:   -11	30	41	9
  B2:   -11	30	41	9
  B3:   -12	31	43	9
  B4:   -12	31	43	9
  B5:   -11	30	41	9
  B6:   -13	31	44	9
  B7:   -11	31	42	10

C1.R2:  Left	Right	Width	Center
  B0:   -11	31	42	10
  B1:   -10	31	41	10
  B2:   -8	31	39	11
  B3:   -10	31	41	10
  B4:   -6	31	37	12
  B5:   -8	31	39	11
  B6:   -9	31	40	11
  B7:   -9	31	40	11

Rank 3
Channel	0			1		
Byte	0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
RdDqsDelay
  -31	# # # # # # # # 	# # # # # # # # 
  -30	# # # # # # # # 	# # # # # # # # 
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   30	# . # . # . . . 	. . . . . . . . 
   31	# # # . # # . # 	. # . . . # . . 

Bit lane information
Channel 0
Byte    0       1       2       3       4       5       6       7       
Bit     0123456701234567012345670123456701234567012345670123456701234567
RdDqsDelay
  -31	################################################################
  -30	################################################################
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  -28	################################################################
  -27	################################################################
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  -17	################################################################
  -16	.#########################.#####.########.#.####.#.#############
  -15	.#############.#.#########..####.#.#####.....###.#..############
  -14	..#..#########.#.#..######..###.....#.##......##....#.#...#.####
  -13	.....#.#.##....#.#...#..##..........#.#.......#.............####
  -12	...............#.....#..#.....................................#.
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   29	..##.................#..........................................
   30	..#..#............####..........#...###.........................
   31	######.......#....####.#........#.#####......#..............##..

Channel 1
Byte    0       1       2       3       4       5       6       7       
Bit     0123456701234567012345670123456701234567012345670123456701234567
RdDqsDelay
  -31	################################################################
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  -15	##.#############################################################
  -14	.#.##.##.##.####################################################
  -13	.#..#.#.....####################################################
  -12	.#....#.....#.##..###.##########.##########.######.#.##.########
  -11	............#.....###..###.....#.##.####.##.###.#....##.##.#.#.#
  -10	..................##.............##..###.##.#.#......#..##.#....
   -9	...................#..................##.##...#..........#......
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   29	...............................................#................
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   31	.........###..#..............................###................

C0.R3:  Left	Right	Width	Center
  B0:   -12	28	40	8
  B1:   -11	30	41	9
  B2:   -11	28	39	8
  B3:   -11	31	42	10
  B4:   -12	29	41	8
  B5:   -12	30	42	9
  B6:   -13	31	44	9
  B7:   -11	30	41	9

C1.R3:  Left	Right	Width	Center
  B0:   -11	31	42	10
  B1:   -10	30	40	10
  B2:   -7	31	38	12
  B3:   -10	31	41	10
  B4:   -7	31	38	12
  B5:   -8	28	36	10
  B6:   -9	31	40	11
  B7:   -8	31	39	11



Executing raminit task RDVC1D
Rank 0
Channel	0			1		
Byte	0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
RdVoltage
  -54	# # # # # # # # 	# # # # # # # # 
  -53	# # # # # # # # 	# # # # # # # # 
  -52	# # # # # # # # 	# # # # # # # # 
  -51	# # # # # # # # 	# # # # # # # # 
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    0	. . . . . . . . 	. . . . . . . . 
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   40	# # # # . . # # 	# # . . # # . # 
   41	# # # # # # # # 	# # . . # # # # 
   42	# # # # # # # # 	# # # # # # # # 
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   53	# # # # # # # # 	# # # # # # # # 
   54	# # # # # # # # 	# # # # # # # # 

Bit lane information
Channel 0
Byte    0       1       2       3       4       5       6       7       
Bit     0123456701234567012345670123456701234567012345670123456701234567
RdVoltage
  -54	################################################################
  -53	################################################################
  -52	################################################################
  -51	################################################################
  -50	################################################################
  -49	################################################################
  -48	################################################################
  -47	################################################################
  -46	################################################################
  -45	################################################################
  -44	################################################################
  -43	################################################################
  -42	################################################################
  -41	################################################################
  -40	##############################.#########.#######################
  -39	##############################.#########.#######################
  -38	########################.#####..########.#######################
  -37	########################.#####..########.###############.#######
  -36	########.###############.#####...#######.###############.#######
  -35	########.#############.#.#####...#######.#######.#######.#######
  -34	########.#####.#.#####.#.##.##...######..###.###.#######.#######
  -33	########.#####.#.###.#.#..#..#...######...##.###.#######.#######
  -32	.#####.#.#####.#.##..#.......#....##......##.#...#####.#.#######
  -31	.#####.#.#####.#..#..#............#.......#..#...#####...###.##.
  -30	.#####.#.###.#.#..#..#............#.......#..#...##..#....##.##.
  -29	.##.##.#.###.#.#..#.......................#......##..#....##.##.
  -28	.##..#.#.##.......#.......................#...............##.##.
  -27	..#..#...##.......#.......................................#..#..
  -26	..#..#....#.......#.......................................#.....
  -25	..#..#....#...............................................#.....
  -24	..#.............................................................
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   29	#...............................................................
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   34	#...............................................................
   35	#.#.............................................................
   36	#.#.....#.......................................................
   37	#.#.....#.......................................#...............
   38	#.#.....#.......................................#.......#.......
   39	###.....#.......#.......#.......................#.......#.......
   40	###..#.##.......#.......#.......................#.#.....#.......
   41	####.####.......#.......#.......#.......#.......#.#.....#.......
   42	#########.......#.......#.......#.......#.......#.#.....#.#.....
   43	#########.......#.......#.......#.......#.......#.#.....#.#..#..
   44	#########.#.....#.......#.......#.......#.#.....#.#.....#.#..#..
   45	#########.##....#.......#.......#.......#.#.....#.#..#..###..#..
   46	#########.##.#..#.......#....#..#.......#.#.....#.#..#..####.#.#
   47	#########.##.#..#.#..#..#....#..#.#.....#.#.##..#.####.#######.#
   48	#########.##.#..###..#..#.#..#..#.#.....#.####..#.##############
   49	#########.##.#.####..#..###..#..#.#.....######..#.##############
   50	#########.#########..#..###..#..#.#.....#######.################
   51	####################.#.####..#..#.#..#..########################
   52	####################.#.####..#..###..#.#########################
   53	####################.#.####.##.####..###########################
   54	##############################.#####.###########################

Channel 1
Byte    0       1       2       3       4       5       6       7       
Bit     0123456701234567012345670123456701234567012345670123456701234567
RdVoltage
  -54	################################################################
  -53	################################################################
  -52	################################################################
  -51	################################################################
  -50	################################################################
  -49	################################################################
  -48	################################################################
  -47	################################################################
  -46	################################################################
  -45	################################################################
  -44	################################################################
  -43	################################################################
  -42	################################################################
  -41	################################################################
  -40	################################.###############################
  -39	################################.###############################
  -38	################.#######.#######.###############################
  -37	################.#######.#######.###############################
  -36	################.#######.#######.###.###################.#######
  -35	################.#######.##.####.##..###################.#######
  -34	################.#######.##.####.##..###################.#######
  -33	########.#######..######.##.###..##..###.#######.#####.#.#######
  -32	.##..#.#..#.####..##.##..#..#.#..##...#..#.#####.#####.#.#######
  -31	.##..#....#.#.....##..#.....#.#...#......#..####.#####.#.######.
  -30	.##.......#.#.....##..#.....#.#...#......#...###.#####....#..##.
  -29	..#.......#.......#...#.....#.#..........#...###.##.##....#.....
  -28	..........#.......#...#.....#.#..........#...###.##.............
  -27	......................#.....#............#...#.#................
  -26	............................#............#...#.#................
  -25	.........................................#.....#................
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   35	#...............................................................
   36	#.......................................#.......................
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   38	#.......#...............................#...............#.......
   39	#.......#...............................#...............#.......
   40	#.......#.......................#.......#...............#.......
   41	#.......#.......................#.......#.......#.......#.......
   42	#.......#.......#.......#.......#.......#.......#.......#.......
   43	#.......#.......#.....#.#.......#.......#.......#.......#.......
   44	#.......#.......#.....#.#.......#.......##...#..#.......#.......
   45	#....#..#.......#.....#.#.......#.......##...#..#.......#.....#.
   46	#....#..#.......#.....#.#...#...#.......##...#..#.......#.....#.
   47	##...#..#.##...##.....#.#...#...#.......##.#.#.##.......#.....#.
   48	###..#..#.##..###.....#.##..#.#.#.#...#.##.#.#####......#.....#.
   49	###.##..#.##..#####...#.##..#.#.#.#..##.##.#######......#..##.##
   50	###.##..#.##..#####..##.##..###.###..##.##.#######......#####.##
   51	###.##..#.#########..#####..###.###..#####.#######..##..########
   52	######..#.#########..#####..#######..##############.##..########
   53	##########################..#######..#################.#########
   54	####################################.#################.#########

C0.R0:  Left	Right	Width	Center
  B0:   -23	28	51	2
  B1:   -24	35	59	5
  B2:   -25	38	63	6
  B3:   -31	38	69	3
  B4:   -29	40	69	5
  B5:   -27	40	67	6
  B6:   -28	36	64	4
  B7:   -24	37	61	6

C1.R0:  Left	Right	Width	Center
  B0:   -28	34	62	3
  B1:   -27	37	64	5
  B2:   -26	41	67	7
  B3:   -25	41	66	8
  B4:   -29	39	68	5
  B5:   -22	35	57	6
  B6:   -27	40	67	6
  B7:   -28	36	64	4

Rank 2
Channel	0			1		
Byte	0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
RdVoltage
  -54	# # # # # # # # 	# # # # # # # # 
  -53	# # # # # # # # 	# # # # # # # # 
  -52	# # # # # # # # 	# # # # # # # # 
  -51	# # # # # # # # 	# # # # # # # # 
  -50	# # # # # # # # 	# # # # # # # # 
  -49	# # # # # # # # 	# # # # # # # # 
  -48	# # # # # # # # 	# # # # # # # # 
  -47	# # # # # # # # 	# # # # # # # # 
  -46	# # # # # # # # 	# # # # # # # # 
  -45	# # # . # # # # 	# # # # # # # # 
  -44	# # # . # # # # 	# # # # # # # # 
  -43	# # # . # # # # 	# # # # # # # # 
  -42	. # . . # # # # 	# # # # # # # # 
  -41	. # . . # # # # 	# # # # # # # # 
  -40	. # . . . . # # 	# # # # # # # # 
  -39	. # . . . . . # 	# # # # # # # # 
  -38	. # . . . . . . 	# # # # # # # # 
  -37	. # . . . . . . 	# # # # # # # # 
  -36	. . . . . . . . 	# # # # # # # # 
  -35	. . . . . . . . 	# # # # # # # . 
  -34	. . . . . . . . 	# # # # # # # . 
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  -12	. . . . . . . . 	. . . . . . . . 
  -11	. . . . . . . . 	. . . . . . . . 
  -10	. . . . . . . . 	. . . . . . . . 
   -9	. . . . . . . . 	. . . . . . . . 
   -8	. . . . . . . . 	. . . . . . . . 
   -7	. . . . . . . . 	. . . . . . . . 
   -6	. . . . . . . . 	. . . . . . . . 
   -5	. . . . . . . . 	. . . . . . . . 
   -4	. . . . . . . . 	. . . . . . . . 
   -3	. . . . . . . . 	. . . . . . . . 
   -2	. . . . . . . . 	. . . . . . . . 
   -1	. . . . . . . . 	. . . . . . . . 
    0	. . . . . . . . 	. . . . . . . . 
    1	. . . . . . . . 	. . . . . . . . 
    2	. . . . . . . . 	. . . . . . . . 
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    7	. . . . . . . . 	. . . . . . . . 
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    9	. . . . . . . . 	. . . . . . . . 
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   41	. . . . . . . . 	. . . . . . . . 
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   43	. . . . . . . . 	. . . . . . . . 
   44	. . . . . . . . 	. . . . . . . . 
   45	. . . . . . . . 	. . . . . . # # 
   46	. . . . . . . . 	. . . . . . # # 
   47	. . . . . . . . 	. . . . . # # # 
   48	. . . . . . . . 	. . . . . # # # 
   49	. . . . . . . . 	. # . . . # # # 
   50	. . . . . . . . 	. # . . . # # # 
   51	. . . . . . . . 	. # . . . # # # 
   52	# . . . . . . . 	# # # . . # # # 
   53	# # . . . . . . 	# # # # . # # # 
   54	# # . # . . . . 	# # # # # # # # 

Bit lane information
Channel 0
Byte    0       1       2       3       4       5       6       7       
Bit     0123456701234567012345670123456701234567012345670123456701234567
RdVoltage
  -54	.###############################.#######.###############.#######
  -53	.###############.###############.#######.###############.#######
  -52	.###############.###############.#######.#######.#######.#######
  -51	.#######.#######.###############.#######.#######.#######.#######
  -50	.#######.#######.#######.#.##.##..######.#######.#######.#######
  -49	..######.#######.#######...##.##..######.#######.#######.#######
  -48	..######.#######.#######....#.#...######.#######.#######.#######
  -47	..######.#######..######....#.#....#####.###.###.#######.#######
  -46	..######.#######...#####....#......#####.#...###.#######.#######
  -45	...#####.#######....####...........##.##.#....##.#.#####.#######
  -44	.....###.####.##....###...............##......##.#.#####.##.####
  -43	.......#..###.##....#.................#.......##...#####.#..###.
  -42	..........###..#......................#.......##....#.##....#.#.
  -41	...............#......................#.......#.....#.#.....#.#.
  -40	...............#....................................#.........#.
  -39	...............#..............................................#.
  -38	...............#................................................
  -37	...............#................................................
  -36	................................................................
  -35	................................................................
  -34	................................................................
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   -1	................................................................
    0	................................................................
    1	................................................................
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   50	................................................................
   51	................................................................
   52	#...............................................................
   53	#.......#.......................................................
   54	#.....#.#...............#.......................................

Channel 1
Byte    0       1       2       3       4       5       6       7       
Bit     0123456701234567012345670123456701234567012345670123456701234567
RdVoltage
  -54	################################################################
  -53	################################################################
  -52	################################################################
  -51	################################################################
  -50	################################.###############################
  -49	################.###############.###############################
  -48	################.#######.#######.###############################
  -47	.###############.#######.#######.###############################
  -46	.###############.#######.#######.###############################
  -45	.###############.#######.#######.#######.#######################
  -44	.###############.#######.#######.#######.#######################
  -43	.#######.#######.#######.#######.##.####.###############.#######
  -42	.#######.#######.#######.#######.##.####.###############.#######
  -41	.#.#####.#######..###.##.#######.#..####.##.############.#####.#
  -40	...#####....####..###.##.#####.#.....###.##.############.###...#
  -39	.....###....####..###.##.####..#......##.##.###.########.#.#...#
  -38	......##....#.##..###..#.#.##..#......##.##.###.########.#.#...#
  -37	......##....#.##...##..#.#.#...#......##.##.#.#.##.#####.#.#....
  -36	......##....#.##...##..#.#.....#......##.#..#.#.##.#####.#......
  -35	......#.....#..#...##....#............##.#..#.#..#.#..##........
  -34	......#.....#..#...##....#.............#.#..#.#..#.#..#.........
  -33	...................#..........................#..#.#............
  -32	................................................................
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   -1	................................................................
    0	................................................................
    1	................................................................
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   45	................................................#.......#.......
   46	................................................#.......#.......
   47	........................................#.......#.......#.......
   48	........................................#.......#.......#.......
   49	........#...............................#.......#.......#.......
   50	........#...............................#.......#.......#.......
   51	........#......#........................#.......#.......#.......
   52	#.......#......##.......................#.......#.......#.......
   53	#.......#......##.......#...............#.......#.......#.......
   54	#.......#.....###.......##......#.....#.##....#.#.......##......

C0.R2:  Left	Right	Width	Center
  B0:   -42	51	93	4
  B1:   -36	52	88	8
  B2:   -42	54	96	6
  B3:   -45	53	98	4
  B4:   -40	54	94	7
  B5:   -40	54	94	7
  B6:   -39	54	93	7
  B7:   -38	54	92	8

C1.R2:  Left	Right	Width	Center
  B0:   -33	51	84	9
  B1:   -33	48	81	7
  B2:   -32	51	83	9
  B3:   -33	52	85	9
  B4:   -33	53	86	10
  B5:   -32	46	78	7
  B6:   -32	44	76	6
  B7:   -35	44	79	4

Rank 3
Channel	0			1		
Byte	0 1 2 3 4 5 6 7 	0 1 2 3 4 5 6 7 
RdVoltage
  -54	# # # # # # # # 	# # # # # # # # 
  -53	# # # # # # # # 	# # # # # # # # 
  -52	# # # # # # # # 	# # # # # # # # 
  -51	# # # # # # # # 	# # # # # # # # 
  -50	# # # # # # # # 	# # # # # # # # 
  -49	# # # # # # # # 	# # # # # # # # 
  -48	# # # # # # # # 	# # # # # # # # 
  -47	# # # # # # # # 	# # # # # # # # 
  -46	# # # # # # # # 	# # # # # # # # 
  -45	# # # # # # # # 	# # # # # # # # 
  -44	# # . # # # # # 	# # # # # # # # 
  -43	# # . # # # # # 	# # # # # # # # 
  -42	# # . # # # # # 	# # # # # # # # 
  -41	# # . . . # # # 	# # # # # # # # 
  -40	# # . . . # . # 	# # # # # # # # 
  -39	# # . . . # . # 	# # # # # # # # 
  -38	# # . . . . . # 	# # # # # # # # 
  -37	. . . . . . . # 	# # # # # # # # 
  -36	. . . . . . . # 	# # # # # # # # 
  -35	. . . . . . . . 	# # # # # # # . 
  -34	. . . . . . . . 	# # # . # # # . 
  -33	. . . . . . . . 	# # # . # # # . 
  -32	. . . . . . . . 	. . # . # . . . 
  -31	. . . . . . . . 	. . . . # . . . 
  -30	. . . . . . . . 	. . . . . . . . 
  -29	. . . . . . . . 	. . . . . . . . 
  -28	. . . . . . . . 	. . . . . . . . 
  -27	. . . . . . . . 	. . . . . . . . 
  -26	. . . . . . . . 	. . . . . . . . 
  -25	. . . . . . . . 	. . . . . . . . 
  -24	. . . . . . . . 	. . . . . . . . 
  -23	. . . . . . . . 	. . . . . . . . 
  -22	. . . . . . . . 	. . . . . . . . 
  -21	. . . . . . . . 	. . . . . . . . 
  -20	. . . . . . . . 	. . . . . . . . 
  -19	. . . . . . . . 	. . . . . . . . 
  -18	. . . . . . . . 	. . . . . . . . 
  -17	. . . . . . . . 	. . . . . . . . 
  -16	. . . . . . . . 	. . . . . . . . 
  -15	. . . . . . . . 	. . . . . . . . 
  -14	. . . . . . . . 	. . . . . . . . 
  -13	. . . . . . . . 	. . . . . . . . 
  -12	. . . . . . . . 	. . . . . . . . 
  -11	. . . . . . . . 	. . . . . . . . 
  -10	. . . . . . . . 	. . . . . . . . 
   -9	. . . . . . . . 	. . . . . . . . 
   -8	. . . . . . . . 	. . . . . . . . 
   -7	. . . . . . . . 	. . . . . . . . 
   -6	. . . . . . . . 	. . . . . . . . 
   -5	. . . . . . . . 	. . . . . . . . 
   -4	. . . . . . . . 	. . . . . . . . 
   -3	. . . . . . . . 	. . . . . . . . 
   -2	. . . . . . . . 	. . . . . . . . 
   -1	. . . . . . . . 	. . . . . . . . 
    0	. . . . . . . . 	. . . . . . . . 
    1	. . . . . . . . 	. . . . . . . . 
    2	. . . . . . . . 	. . . . . . . . 
    3	. . . . . . . . 	. . . . . . . . 
    4	. . . . . . . . 	. . . . . . . . 
    5	. . . . . . . . 	. . . . . . . . 
    6	. . . . . . . . 	. . . . . . . . 
    7	. . . . . . . . 	. . . . . . . . 
    8	. . . . . . . . 	. . . . . . . . 
    9	. . . . . . . . 	. . . . . . . . 
   10	. . . . . . . . 	. . . . . . . . 
   11	. . . . . . . . 	. . . . . . . . 
   12	. . . . . . . . 	. . . . . . . . 
   13	. . . . . . . . 	. . . . . . . . 
   14	. . . . . . . . 	. . . . . . . . 
   15	. . . . . . . . 	. . . . . . . . 
   16	. . . . . . . . 	. . . . . . . . 
   17	. . . . . . . . 	. . . . . . . . 
   18	. . . . . . . . 	. . . . . . . . 
   19	. . . . . . . . 	. . . . . . . . 
   20	. . . . . . . . 	. . . . . . . . 
   21	. . . . . . . . 	. . . . . . . . 
   22	. . . . . . . . 	. . . . . . . . 
   23	. . . . . . . . 	. . . . . . . . 
   24	. . . . . . . . 	. . . . . . . . 
   25	. . . . . . . . 	. . . . . . . . 
   26	. . . . . . . . 	. . . . . . . . 
   27	. . . . . . . . 	. . . . . . . . 
   28	. . . . . . . . 	. . . . . . . . 
   29	. . . . . . . . 	. . . . . . . . 
   30	. . . . . . . . 	. . . . . . . . 
   31	. . . . . . . . 	. . . . . . . . 
   32	. . . . . . . . 	. . . . . . . . 
   33	. . . . . . . . 	. . . . . . . . 
   34	. . . . . . . . 	. . . . . . . . 
   35	. . . . . . . . 	. . . . . . . . 
   36	. . . . . . . . 	. . . . . . . . 
   37	. . . . . . . . 	. . . . . . . . 
   38	. . . . . . . . 	. . . . . . . . 
   39	. . . . . . . . 	. . . . . . . . 
   40	. . . . . . . . 	. . . . . . . . 
   41	. . . . . . . . 	. . . . . . . . 
   42	. . . . . . . . 	. . . . . . . . 
   43	. . . . . . . . 	. . . . . . . . 
   44	. . . . . . . . 	. . . . . # # # 
   45	. . . . . . . . 	. . . . . # # # 
   46	. . . . . . . . 	. . . . . # # # 
   47	. . . . . . . . 	. . . . . # # # 
   48	. . . . . . . . 	. . . . . # # # 
   49	. . . . . . . . 	. # . . . # # # 
   50	. . . . . . . . 	. # . # . # # # 
   51	. . . . . . . . 	# # . # . # # # 
   52	. # . . . . . . 	# # . # . # # # 
   53	. # . . . . . . 	# # . # . # # # 
   54	# # . # . . . . 	# # # # # # # # 

Bit lane information
Channel 0
Byte    0       1       2       3       4       5       6       7       
Bit     0123456701234567012345670123456701234567012345670123456701234567
RdVoltage
  -54	################.###############.###############################
  -53	################.###############.###############.###############
  -52	################.###############.###############.#######.#######
  -51	########.#######.###############.#######.#######.#######.#######
  -50	.#######.#######.###############.#######.#######.#######.#######
  -49	.#######.#######.###############..######.#######.#######.#######
  -48	.#######.#######...#############...#####.#######.#######.#######
  -47	.#######.#######....###.########...#####.#######.#.#####.#######
  -46	.#######.#######....###..##.#.##...#####.#######.#.#####.#######
  -45	.#######.####.##....###.....#.#....##.#..###.###.#.#####.#######
  -44	..######..###.##............#.#.......#..###.###...#####.#######
  -43	..######..###..#............#.........#..#...###...####..#######
  -42	..######.......#............#.........#..#...###....#.#..#######
  -41	...#####.......#..............................##....#.#..#..###.
  -40	.....###.......#..............................#..........#..###.
  -39	.....###.......#..............................#..........#..#.#.
  -38	.......#.......#............................................#.#.
  -37	..............................................................#.
  -36	..............................................................#.
  -35	................................................................
  -34	................................................................
  -33	................................................................
  -32	................................................................
  -31	................................................................
  -30	................................................................
  -29	................................................................
  -28	................................................................
  -27	................................................................
  -26	................................................................
  -25	................................................................
  -24	................................................................
  -23	................................................................
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  -21	................................................................
  -20	................................................................
  -19	................................................................
  -18	................................................................
  -17	................................................................
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  -14	................................................................
  -13	................................................................
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  -10	................................................................
   -9	................................................................
   -8	................................................................
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   -6	................................................................
   -5	................................................................
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   -3	................................................................
   -2	................................................................
   -1	................................................................
    0	................................................................
    1	................................................................
    2	................................................................
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   52	........#.......................................................
   53	........#.......................................................
   54	#.....#.#...............#.......................................

Channel 1
Byte    0       1       2       3       4       5       6       7       
Bit     0123456701234567012345670123456701234567012345670123456701234567
RdVoltage
  -54	################################################################
  -53	################################################################
  -52	################################################################
  -51	################################################################
  -50	################.###############################################
  -49	################.###############################################
  -48	################.###############.###############################
  -47	################.#######.#######.###############################
  -46	################.#######.#######.###############################
  -45	################.#######.#######.#######.#######################
  -44	.###############.#######.#######.#######.#######################
  -43	.###############.#######.#######.#######.###############.#######
  -42	.#######.#######.#######.#######.#######.###############.###.#.#
  -41	.#######.#######.####.##.#######.#######.##.############.###.#.#
  -40	.#######.#######..###.##.#####.#.##.####.##.###.########.#.#...#
  -39	.#.#####..#.####..###.##.###...#.##.####.##.###.########.#.#...#
  -38	.#.#####....####..###..#.#.#...#.##.####.##.#.#.########.#......
  -37	...#.###....####...##..#.#.#...#.#...###.##.#.#.##.#####.#......
  -36	......##....#.##...##....#.#...#......##.#..#.#.##.#####.#......
  -35	......##....#.##...##....#............##.#..#.#..#.#.##.........
  -34	......#.....#.##...##.................##.#..#.#..#.#..#.........
  -33	......#.....#..#...#..................##.#.......#.#............
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   50	........#......#........#...............#.......#.......#.......
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   54	#.......#.....###.......##............#.##..#.#.#.......#.......

C0.R3:  Left	Right	Width	Center
  B0:   -37	53	90	8
  B1:   -37	51	88	7
  B2:   -44	54	98	5
  B3:   -41	53	94	6
  B4:   -41	54	95	6
  B5:   -38	54	92	8
  B6:   -40	54	94	7
  B7:   -35	54	89	9

C1.R3:  Left	Right	Width	Center
  B0:   -32	50	82	9
  B1:   -32	48	80	8
  B2:   -31	53	84	11
  B3:   -34	49	83	7
  B4:   -30	53	83	11
  B5:   -32	43	75	5
  B6:   -32	43	75	5
  B7:   -35	43	78	4



Executing raminit task OPTCOMP


Executing raminit task POSTTRAIN


Executing raminit task ACTIVATE


Executing raminit task SAVE_TRAIN


Executing raminit task SAVE_NONT


Executing raminit task RAMINITEND
Waiting for mc_init_done acknowledgement... DONE!

+------------------+------------+
| Task             |      msecs |
+------------------+------------+
| PROCSPD          |        531 |
| INITMPLL         |         34 |
| CONVTIM          |         44 |
| CONFMC           |          1 |
| MEMMAP           |         40 |
| JEDECINIT        |          1 |
| PRETRAIN         |         24 |
| SOT              |        449 |
| RCVET            |       1156 |
| RDMPRT           |        889 |
| JWRL             |       1614 |
| WRTC1D           |       3790 |
| RDTC1D           |       3786 |
| RDVC1D           |       6380 |
| OPTCOMP          |          0 |
| POSTTRAIN        |          0 |
| ACTIVATE         |          0 |
| SAVE_TRAIN       |          0 |
| SAVE_NONT        |          0 |
| RAMINITEND       |          4 |
+------------------+------------+
| Total            |      18751 |
+------------------+------------+
memcfg DDR3 clock 1600 MHz
memcfg channel assignment: A: 0, B  1, C  2
memcfg channel[0] config (00641010):
   ECC inactive
   enhanced interleave mode on
   rank interleave on
   DIMMA 4096 MB width x8 or x32 single rank, selected
   DIMMB 4096 MB width x8 or x32 dual rank
memcfg channel[1] config (00641010):
   ECC inactive
   enhanced interleave mode on
   rank interleave on
   DIMMA 4096 MB width x8 or x32 single rank, selected
   DIMMB 4096 MB width x8 or x32 dual rank
ME: Requested 16MB UMA
ME: Sending Init Done with status: 0, UMA base: 0x3ff0
ME: Requested BIOS Action: Continue to boot
ME: FW Partition Table      : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : NO
ME: Manufacturing Mode      : NO
ME: Boot Options Present    : NO
ME: Update In Progress      : NO
ME: Current Working State   : Normal
ME: Current Operation State : Bring up
ME: Current Operation Mode  : Normal
ME: Error Code              : No Error
ME: Progress Phase          : BUP Phase
ME: Power Management Event  : Pseudo-global reset
ME: Progress Phase State    : 0x50
ME: FW Partition Table      : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : NO
ME: Manufacturing Mode      : NO
ME: Boot Options Present    : NO
ME: Update In Progress      : NO
ME: Current Working State   : Normal
ME: Current Operation State : M0 with UMA
ME: Current Operation Mode  : Normal
ME: Error Code              : No Error
ME: Progress Phase          : BUP Phase
ME: Power Management Event  : Pseudo-global reset
ME: Progress Phase State    : M0 kernel load
CBMEM:
IMD: root @ 0x7f7ff000 254 entries.
IMD: root @ 0x7f7fec00 62 entries.
Starting cbfs_boot_device
FMAP: area COREBOOT found @ 591000 (2551808 bytes)
Booting from COREBOOT region
External stage cache:
IMD: root @ 0x7fbff000 254 entries.
IMD: root @ 0x7fbfec00 62 entries.
FMAP: area RW_MRC_CACHE found @ 500000 (65536 bytes)
MRC: Checking cached data update for 'RW_MRC_CACHE'.
MRC: no data in 'RW_MRC_CACHE'
MRC: cache data 'RW_MRC_CACHE' needs update.
MRC: updated 'RW_MRC_CACHE'.
SMM Memory Map
SMRAM       : 0x7f800000 0x800000
 Subregion 0: 0x7f800000 0x300000
 Subregion 1: 0x7fb00000 0x100000
 Subregion 2: 0x7fc00000 0x400000
Normal boot
Starting cbfs_boot_device
CBFS: Found 'fallback/postcar' @0x4d880 size 0x9ee4 in mcache @0xff7e1014
Loading module at 0x7f7cb000 with entry 0x7f7cb031. filesize: 0x9708 memsize: 0xfb48
Processing 487 relocs. Offset value of 0x7d7cb000
BS: romstage times (exec / console): total (unknown) / 18946 ms


coreboot-25.12-538-g142ae8491ce9-dirty Fri Feb 20 20:25:24 UTC 2026 x86_32 postcar starting (log level: 7)...
Normal boot
Starting cbfs_boot_device
FMAP: area COREBOOT found @ 591000 (2551808 bytes)
Booting from COREBOOT region
CBFS: Found 'fallback/ramstage' @0x2b7c0 size 0x1e76c in mcache @0x7f7fea0c
Loading module at 0x7f67d000 with entry 0x7f67d000. filesize: 0x3d720 memsize: 0x14c990
Processing 4364 relocs. Offset value of 0x7b67d000
BS: postcar times (exec / console): total (unknown) / 40 ms


coreboot-25.12-538-g142ae8491ce9-dirty Fri Feb 20 20:25:24 UTC 2026 x86_32 ramstage starting (log level: 7)...
Normal boot
Enumerating buses...
Root Device scanning...
CPU_CLUSTER: 0 enabled
DOMAIN: 00000000 enabled
DOMAIN: 00000000 scanning...
PCI: pci_scan_bus for segment group 00 bus 00
PCI: 00:00:00.0 [8086/0c00] enabled
PCI: 00:00:01.0 [8086/0c01] enabled
PCI: Static device PCI: 00:00:01.1 not found, disabling it.
PCI: Static device PCI: 00:00:01.2 not found, disabling it.
PCI: 00:00:02.0 [8086/0412] enabled
PCI: 00:00:03.0 [8086/0c0c] enabled
PCI: 00:00:14.0 [8086/8cb1] enabled
PCI: 00:00:16.0 [8086/8cba] enabled
PCI: 00:00:16.1: Disabling device
PCI: 00:00:16.1 [8086/8cbb] disabled No operations
PCI: 00:00:19.0 [8086/15a1] enabled
PCI: 00:00:1a.0 [8086/8cad] enabled
PCI: 00:00:1b.0 [8086/8ca0] enabled
PCI: 00:00:1c.0 [8086/8c90] disabled
PCIe Root Port 3 ASPM is disabled
PCI: 00:00:1c.2 [8086/8c94] enabled
PCIe Root Port 4 ASPM is disabled
PCI: 00:00:1c.3 [8086/8c96] enabled
Adjusted number of PCIe root ports to 7 as per strpfusecfg2
PCIe Root Port 5 ASPM is disabled
PCI: 00:00:1c.4 [8086/8c98] enabled
PCIe Root Port 7 ASPM is disabled
PCI: 00:00:1c.0: Disabling device
Root Port 2 device is NULL?
Root Port 6 device is NULL?
PCH: PCIe map 1c.2 -> 1c.0
PCH: PCIe map 1c.3 -> 1c.1
PCH: PCIe map 1c.4 -> 1c.2
PCH: PCIe map 1c.6 -> 1c.3
PCH: PCIe map 1c.0 -> 1c.4
PCI: 00:00:1c.3 [8086/8c9c] enabled
PCI: 00:00:1d.0 [8086/8ca6] enabled
PCI: 00:00:1f.0 [8086/8cc4] enabled
PCI: 00:00:1f.2 [8086/8c80] enabled
PCI: 00:00:1f.3 [8086/8ca2] enabled
PCI: 00:00:1f.5: Disabling device
PCI: 00:00:1f.5 [8086/8c88] disabled
PCI: 00:00:1f.6 [8086/8ca4] enabled
PCI: 00:00:01.0 scanning...
PCI: pci_scan_bus for segment group 00 bus 01
PCI: 00:00:01.0: ASPM enabled L0s and L1 (no endpoint)
PCI: 00:00:01.0: Setting Max_Payload_Size to 256 for devices under this root port
scan_bus: bus PCI: 00:00:01.0 finished in 16 msecs
PCI: 00:00:1c.0 scanning...
PCI: pci_scan_bus for segment group 00 bus 02
PCI: 00:02:00.0 [10ec/8168] enabled
Enabling Common Clock Configuration
ASPM: Enabled L1
PCI: 00:02:00.0: Enabled LTR
PCI: 00:00:1c.0: Setting Max_Payload_Size to 128 for devices under this root port
scan_bus: bus PCI: 00:00:1c.0 finished in 22 msecs
PCI: 00:00:1c.1 scanning...
PCI: pci_scan_bus for segment group 00 bus 03
PCI: 00:03:00.0 subordinate bus PCI Express
PCI: 00:03:00.0 [1b21/1184] enabled
PCI: 00:03:00.0 scanning...
PCI: 00:03:00.0: No LTR support
PCI: pci_scan_bus for segment group 00 bus 04
PCI: 00:04:01.0 subordinate bus PCI Express
PCI: 00:04:01.0 [1b21/1184] enabled
PCI: 00:04:03.0 subordinate bus PCI Express
PCI: 00:04:03.0 [1b21/1184] enabled
PCI: 00:04:05.0 subordinate bus PCI Express
PCI: 00:04:05.0 [1b21/1184] enabled
PCI: 00:04:07.0 subordinate bus PCI Express
PCI: 00:04:07.0 [1b21/1184] enabled
PCI: 00:04:01.0 scanning...
PCI: 00:04:01.0: No LTR support
PCI: pci_scan_bus for segment group 00 bus 05
scan_bus: bus PCI: 00:04:01.0 finished in 7 msecs
PCI: 00:04:03.0 scanning...
PCI: 00:04:03.0: No LTR support
PCI: pci_scan_bus for segment group 00 bus 06
PCI: 00:06:00.0 [1b21/0611] enabled
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpoint
ASPM: Enabled None
PCI: 00:06:00.0: No LTR support
scan_bus: bus PCI: 00:04:03.0 finished in 22 msecs
PCI: 00:04:05.0 scanning...
PCI: 00:04:05.0: No LTR support
PCI: pci_scan_bus for segment group 00 bus 07
scan_bus: bus PCI: 00:04:05.0 finished in 7 msecs
PCI: 00:04:07.0 scanning...
PCI: 00:04:07.0: No LTR support
PCI: pci_scan_bus for segment group 00 bus 08
PCI: 00:08:00.0 [1b21/0611] enabled
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpoint
ASPM: Enabled None
PCI: 00:08:00.0: No LTR support
scan_bus: bus PCI: 00:04:07.0 finished in 22 msecs
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpoint
ASPM: Enabled None
PCI: 00:04:01.0: No LTR support
PCIe: Common Clock Configuration already enabled
PCIE CLK PM is not supported by endpoint
ASPM: Enabled None
PCI: 00:04:03.0: No LTR support
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpoint
ASPM: Enabled None
PCI: 00:04:05.0: No LTR support
PCIe: Common Clock Configuration already enabled
PCIE CLK PM is not supported by endpoint
ASPM: Enabled None
PCI: 00:04:07.0: No LTR support
scan_bus: bus PCI: 00:03:00.0 finished in 170 msecs
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpoint
ASPM: Enabled None
PCI: 00:03:00.0: No LTR support
PCI: 00:00:1c.1: Setting Max_Payload_Size to 128 for devices under this root port
scan_bus: bus PCI: 00:00:1c.1 finished in 208 msecs
PCI: 00:00:1c.2 scanning...
PCI: pci_scan_bus for segment group 00 bus 09
PCI: 00:00:1c.2: ASPM enabled L0s and L1 (no endpoint)
PCI: 00:00:1c.2: Setting Max_Payload_Size to 128 for devices under this root port
scan_bus: bus PCI: 00:00:1c.2 finished in 16 msecs
PCI: 00:00:1c.3 scanning...
PCI: pci_scan_bus for segment group 00 bus 0a
PCI: 00:0a:00.0 [1b21/1142] enabled
Enabling Common Clock Configuration
PCIE CLK PM is not supported by endpoint
ASPM: Enabled None
PCI: 00:0a:00.0: No LTR support
PCI: 00:00:1c.3: Setting Max_Payload_Size to 128 for devices under this root port
scan_bus: bus PCI: 00:00:1c.3 finished in 26 msecs
PCI: 00:00:1f.0 scanning...
PNP: 002e.0 enabled
PNP: 0c31.0 enabled
PNP: 002e.0 scanning...
PNP: 002e.1 disabled
PNP: 002e.2 enabled
PNP: 002e.3 disabled
PNP: 002e.5 enabled
PNP: 002e.6 disabled
PNP: 002e.7 disabled
PNP: 002e.107 enabled
PNP: 002e.207 disabled
PNP: 002e.8 disabled
PNP: 002e.108 disabled
PNP: 002e.308 disabled
PNP: 002e.408 disabled
PNP: 002e.708 enabled
PNP: 002e.9 enabled
PNP: 002e.109 enabled
PNP: 002e.209 enabled
PNP: 002e.309 enabled
PNP: 002e.a enabled
PNP: 002e.b enabled
PNP: 002e.d disabled
PNP: 002e.e disabled
PNP: 002e.f disabled
PNP: 002e.14 disabled
PNP: 002e.16 disabled
PNP: 002e.116 disabled
PNP: 002e.316 disabled
PNP: 002e.416 disabled
PNP: 002e.516 enabled
PNP: 002e.616 disabled
PNP: 002e.716 disabled
scan_bus: bus PNP: 002e.0 finished in 60 msecs
scan_bus: bus PCI: 00:00:1f.0 finished in 70 msecs
PCI: 00:00:1f.3 scanning...
scan_bus: bus PCI: 00:00:1f.3 finished in 0 msecs
scan_bus: bus DOMAIN: 00000000 finished in 536 msecs
scan_bus: bus Root Device finished in 547 msecs
done
BS: BS_DEV_ENUMERATE run times (exec / console): 4 / 553 ms
found VGA at PCI: 00:00:02.0
Setting up VGA for PCI: 00:00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 00000000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
mc_add_fixed_mmio_resources: Adding MCHBAR @ 48 0xfed10000-0xfed17fff.
mc_add_fixed_mmio_resources: Adding DMIBAR @ 68 0xfed18000-0xfed18fff.
mc_add_fixed_mmio_resources: Adding EPBAR @ 40 0xfed19000-0xfed19fff.
mc_add_fixed_mmio_resources: Adding GDXCBAR @ 5420 0xfed84000-0xfed84fff.
mc_add_fixed_mmio_resources: Adding EDRAMBAR @ 5408 0xfed80000-0xfed83fff.
Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
MC MAP: TOM: 0x400000000
MC MAP: TOUUD: 0x47ae00000
MC MAP: MESEG_BASE: 0x3ff000000
MC MAP: MESEG_LIMIT: 0x7fff0fffff
MC MAP: REMAP_BASE: 0x3ff000000
MC MAP: REMAP_LIMIT: 0x47adfffff
MC MAP: TOLUD: 0x84200000
MC MAP: BGSM: 0x80000000
MC MAP: BDSM: 0x80200000
MC MAP: TSEGMB: 0x7f800000
MC MAP: GGC: 0x211
MC MAP: DPR: 0x7f800001
Available memory above 4GB: 14254M
Done reading resources.
=== Resource allocator: DOMAIN: 00000000 - Pass 1 (relative placement) ===
 PCI: 00:00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
  PCI: 00:02:00.0 10 *  [0x0 - 0xff] io
 PCI: 00:00:1c.0 io: size: 1000 align: 12 gran: 12 limit: ffff done
 PCI: 00:00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  PCI: 00:02:00.0 18 *  [0x0 - 0xfff] mem
 PCI: 00:00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
 PCI: 00:00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
  PCI: 00:02:00.0 20 *  [0x0 - 0x3fff] prefmem
 PCI: 00:00:1c.0 prefmem: size: 100000 align: 20 gran: 20 limit: ffffffff done
   PCI: 00:04:03.0 io: size: 0 align: 12 gran: 12 limit: ffffffff
    PCI: 00:06:00.0 20 *  [0x0 - 0xf] io
    PCI: 00:06:00.0 10 *  [0x10 - 0x17] io
    PCI: 00:06:00.0 18 *  [0x18 - 0x1f] io
    PCI: 00:06:00.0 14 *  [0x20 - 0x23] io
    PCI: 00:06:00.0 1c *  [0x24 - 0x27] io
   PCI: 00:04:03.0 io: size: 1000 align: 12 gran: 12 limit: ffff done
   PCI: 00:04:07.0 io: size: 0 align: 12 gran: 12 limit: ffffffff
    PCI: 00:08:00.0 20 *  [0x0 - 0xf] io
    PCI: 00:08:00.0 10 *  [0x10 - 0x17] io
    PCI: 00:08:00.0 18 *  [0x18 - 0x1f] io
    PCI: 00:08:00.0 14 *  [0x20 - 0x23] io
    PCI: 00:08:00.0 1c *  [0x24 - 0x27] io
   PCI: 00:04:07.0 io: size: 1000 align: 12 gran: 12 limit: ffff done
  PCI: 00:03:00.0 io: size: 0 align: 12 gran: 12 limit: ffffffff
   PCI: 00:04:03.0 1c *  [0x0 - 0xfff] io
   PCI: 00:04:07.0 1c *  [0x1000 - 0x1fff] io
  PCI: 00:03:00.0 io: size: 2000 align: 12 gran: 12 limit: ffff done
 PCI: 00:00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff
  PCI: 00:03:00.0 1c *  [0x0 - 0x1fff] io
 PCI: 00:00:1c.1 io: size: 2000 align: 12 gran: 12 limit: ffff done
   PCI: 00:04:03.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
    PCI: 00:06:00.0 24 *  [0x0 - 0x1ff] mem
   PCI: 00:04:03.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
   PCI: 00:04:07.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
    PCI: 00:08:00.0 24 *  [0x0 - 0x1ff] mem
   PCI: 00:04:07.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
  PCI: 00:03:00.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
   PCI: 00:04:03.0 20 *  [0x0 - 0xfffff] mem
   PCI: 00:04:07.0 20 *  [0x100000 - 0x1fffff] mem
  PCI: 00:03:00.0 mem: size: 200000 align: 20 gran: 20 limit: ffffffff done
 PCI: 00:00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  PCI: 00:03:00.0 20 *  [0x0 - 0x1fffff] mem
 PCI: 00:00:1c.1 mem: size: 200000 align: 20 gran: 20 limit: ffffffff done
   PCI: 00:04:03.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
   PCI: 00:04:03.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
   PCI: 00:04:07.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
   PCI: 00:04:07.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
  PCI: 00:03:00.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
  PCI: 00:03:00.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
 PCI: 00:00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
 PCI: 00:00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
 PCI: 00:00:1c.3 io: size: 0 align: 12 gran: 12 limit: ffff
 PCI: 00:00:1c.3 io: size: 0 align: 12 gran: 12 limit: ffff done
 PCI: 00:00:1c.3 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  PCI: 00:0a:00.0 10 *  [0x0 - 0x7fff] mem
 PCI: 00:00:1c.3 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
 PCI: 00:00:1c.3 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
 PCI: 00:00:1c.3 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
=== Resource allocator: DOMAIN: 00000000 - Pass 2 (allocating resources) ===
DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
 avoid_fixed_resources: PCI: 00:00:1f.0 00 base 00000000 limit 00000fff io (fixed)
 avoid_fixed_resources: PNP: 002e.0 00 base 0000002e limit 0000002f io (fixed)
 avoid_fixed_resources: PNP: 002e.2 60 base 000003f8 limit 000003ff io (fixed)
 avoid_fixed_resources: PNP: 002e.5 60 base 00000060 limit 00000060 io (fixed)
 avoid_fixed_resources: PNP: 002e.5 62 base 00000064 limit 00000064 io (fixed)
 avoid_fixed_resources: PNP: 002e.b 60 base 00000290 limit 00000291 io (fixed)
 avoid_fixed_resources: PNP: 002e.b 62 base 00000000 limit 00000001 io (fixed)
 avoid_fixed_resources: PCI: 00:00:1f.3 20 base 00000400 limit 0000041f io (fixed)
 DOMAIN: 00000000: Resource ranges:
 * Base: 1000, Size: f000, Tag: 100
  PCI: 00:00:1c.1 1c *  [0xe000 - 0xffff] limit: ffff io
  PCI: 00:00:1c.0 1c *  [0xd000 - 0xdfff] limit: dfff io
  PCI: 00:00:02.0 20 *  [0xcfc0 - 0xcfff] limit: cfff io
  PCI: 00:00:19.0 18 *  [0xcfa0 - 0xcfbf] limit: cfbf io
  PCI: 00:00:1f.2 20 *  [0xcf80 - 0xcf9f] limit: cf9f io
  PCI: 00:00:1f.2 10 *  [0xcf78 - 0xcf7f] limit: cf7f io
  PCI: 00:00:1f.2 18 *  [0xcf70 - 0xcf77] limit: cf77 io
  PCI: 00:00:1f.2 14 *  [0xcf6c - 0xcf6f] limit: cf6f io
  PCI: 00:00:1f.2 1c *  [0xcf68 - 0xcf6b] limit: cf6b io
DOMAIN: 00000000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
DOMAIN: 00000000 mem: base: 7f800000 size: 0 align: 0 gran: 0 limit: efffffff
DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff
 avoid_fixed_resources: PCI: 00:00:00.0 48 base fed10000 limit fed17fff mem (fixed)
 avoid_fixed_resources: PCI: 00:00:00.0 68 base fed18000 limit fed18fff mem (fixed)
 avoid_fixed_resources: PCI: 00:00:00.0 40 base fed19000 limit fed19fff mem (fixed)
 avoid_fixed_resources: PCI: 00:00:00.0 5420 base fed84000 limit fed84fff mem (fixed)
 avoid_fixed_resources: PCI: 00:00:00.0 5408 base fed80000 limit fed83fff mem (fixed)
 avoid_fixed_resources: PCI: 00:00:00.0 60 base f0000000 limit f3ffffff mem (fixed)
 avoid_fixed_resources: PCI: 00:00:00.0 00 base fed90000 limit fed90fff mem (fixed)
 avoid_fixed_resources: PCI: 00:00:00.0 01 base fed91000 limit fed91fff mem (fixed)
 avoid_fixed_resources: PCI: 00:00:00.0 02 base 00000000 limit 0009ffff mem (fixed)
 avoid_fixed_resources: PCI: 00:00:00.0 03 base 000a0000 limit 000bffff mem (fixed)
 avoid_fixed_resources: PCI: 00:00:00.0 04 base 000c0000 limit 000fffff mem (fixed)
 avoid_fixed_resources: PCI: 00:00:00.0 05 base 00100000 limit 7f7fffff mem (fixed)
 avoid_fixed_resources: PCI: 00:00:00.0 06 base 7f800000 limit 7fffffff mem (fixed)
 avoid_fixed_resources: PCI: 00:00:00.0 07 base 80000000 limit 841fffff mem (fixed)
 avoid_fixed_resources: PCI: 00:00:00.0 08 base 100000000 limit 47adfffff mem (fixed)
 avoid_fixed_resources: PCI: 00:00:1f.0 31fe base fec00000 limit ffffffff mem (fixed)
 DOMAIN: 00000000: Resource ranges:
 * Base: 84200000, Size: 6be00000, Tag: 200
 * Base: 47ae00000, Size: 7b85200000, Tag: 200
  PCI: 00:00:02.0 18 *  [0xe0000000 - 0xefffffff] limit: efffffff prefmem
  PCI: 00:00:02.0 10 *  [0xdfc00000 - 0xdfffffff] limit: dfffffff mem
  PCI: 00:00:1c.1 20 *  [0xdfa00000 - 0xdfbfffff] limit: dfbfffff mem
  PCI: 00:00:1c.0 24 *  [0xdf900000 - 0xdf9fffff] limit: df9fffff prefmem
  PCI: 00:00:1c.0 20 *  [0xdf800000 - 0xdf8fffff] limit: df8fffff mem
  PCI: 00:00:1c.3 20 *  [0xdf700000 - 0xdf7fffff] limit: df7fffff mem
  PCI: 00:00:19.0 10 *  [0xdf6e0000 - 0xdf6fffff] limit: df6fffff mem
  PCI: 00:00:14.0 10 *  [0xdf6d0000 - 0xdf6dffff] limit: df6dffff mem
  PCI: 00:00:1f.2 24 *  [0xdf6c8000 - 0xdf6cffff] limit: df6cffff mem
  PCI: 00:00:03.0 10 *  [0xdf6c4000 - 0xdf6c7fff] limit: df6c7fff mem
  PCI: 00:00:1b.0 10 *  [0xdf6c0000 - 0xdf6c3fff] limit: df6c3fff mem
  PCI: 00:00:19.0 14 *  [0xdf6bf000 - 0xdf6bffff] limit: df6bffff mem
  PCI: 00:00:1f.6 10 *  [0xdf6be000 - 0xdf6befff] limit: df6befff mem
  PCI: 00:00:1a.0 10 *  [0xdf6bd000 - 0xdf6bd3ff] limit: df6bd3ff mem
  PCI: 00:00:1d.0 10 *  [0xdf6bc000 - 0xdf6bc3ff] limit: df6bc3ff mem
  PCI: 00:00:1f.3 10 *  [0xdf6bb000 - 0xdf6bb0ff] limit: df6bb0ff mem
  PCI: 00:00:16.0 10 *  [0xdf6ba000 - 0xdf6ba00f] limit: df6ba00f mem
DOMAIN: 00000000 mem: base: 7f800000 size: 0 align: 0 gran: 0 limit: efffffff done
DOMAIN: 00000000 mem: base: 100000000 size: 0 align: 0 gran: 0 limit: 7fffffffff done
  PCI: 00:02:00.0 10 *  [0xd000 - 0xd0ff] limit: d0ff io
  PCI: 00:02:00.0 20 *  [0xdf900000 - 0xdf903fff] limit: df903fff prefmem
  PCI: 00:02:00.0 18 *  [0xdf800000 - 0xdf800fff] limit: df800fff mem
  PCI: 00:03:00.0 1c *  [0xe000 - 0xffff] limit: ffff io
  PCI: 00:03:00.0 20 *  [0xdfa00000 - 0xdfbfffff] limit: dfbfffff mem
  PCI: 00:04:03.0 1c *  [0xe000 - 0xefff] limit: efff io
  PCI: 00:04:07.0 1c *  [0xf000 - 0xffff] limit: ffff io
  PCI: 00:04:03.0 20 *  [0xdfa00000 - 0xdfafffff] limit: dfafffff mem
  PCI: 00:04:07.0 20 *  [0xdfb00000 - 0xdfbfffff] limit: dfbfffff mem
  PCI: 00:06:00.0 10 *  [0xe010 - 0xe017] limit: e017 io
  PCI: 00:06:00.0 14 *  [0xe020 - 0xe023] limit: e023 io
  PCI: 00:06:00.0 18 *  [0xe018 - 0xe01f] limit: e01f io
  PCI: 00:06:00.0 1c *  [0xe024 - 0xe027] limit: e027 io
  PCI: 00:06:00.0 20 *  [0xe000 - 0xe00f] limit: e00f io
  PCI: 00:06:00.0 24 *  [0xdfa00000 - 0xdfa001ff] limit: dfa001ff mem
  PCI: 00:08:00.0 10 *  [0xf010 - 0xf017] limit: f017 io
  PCI: 00:08:00.0 14 *  [0xf020 - 0xf023] limit: f023 io
  PCI: 00:08:00.0 18 *  [0xf018 - 0xf01f] limit: f01f io
  PCI: 00:08:00.0 1c *  [0xf024 - 0xf027] limit: f027 io
  PCI: 00:08:00.0 20 *  [0xf000 - 0xf00f] limit: f00f io
  PCI: 00:08:00.0 24 *  [0xdfb00000 - 0xdfb001ff] limit: dfb001ff mem
  PCI: 00:0a:00.0 10 *  [0xdf700000 - 0xdf707fff] limit: df707fff mem
=== Resource allocator: DOMAIN: 00000000 - resource allocation complete ===
PCI: 00:00:01.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 01 io
PCI: 00:00:01.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 prefmem
PCI: 00:00:01.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 01 mem
PCI: 00:00:02.0 10 <- [0x00000000dfc00000 - 0x00000000dfffffff] size 0x00400000 gran 0x16 mem64
PCI: 00:00:02.0 18 <- [0x00000000e0000000 - 0x00000000efffffff] size 0x10000000 gran 0x1c prefmem64
PCI: 00:00:02.0 20 <- [0x000000000000cfc0 - 0x000000000000cfff] size 0x00000040 gran 0x06 io
PCI: 00:00:03.0 10 <- [0x00000000df6c4000 - 0x00000000df6c7fff] size 0x00004000 gran 0x0e mem64
PCI: 00:00:14.0 10 <- [0x00000000df6d0000 - 0x00000000df6dffff] size 0x00010000 gran 0x10 mem64
PCI: 00:00:16.0 10 <- [0x00000000df6ba000 - 0x00000000df6ba00f] size 0x00000010 gran 0x04 mem64
PCI: 00:00:19.0 10 <- [0x00000000df6e0000 - 0x00000000df6fffff] size 0x00020000 gran 0x11 mem
PCI: 00:00:19.0 14 <- [0x00000000df6bf000 - 0x00000000df6bffff] size 0x00001000 gran 0x0c mem
PCI: 00:00:19.0 18 <- [0x000000000000cfa0 - 0x000000000000cfbf] size 0x00000020 gran 0x05 io
PCI: 00:00:1a.0 10 <- [0x00000000df6bd000 - 0x00000000df6bd3ff] size 0x00000400 gran 0x0a mem
PCI: 00:00:1b.0 10 <- [0x00000000df6c0000 - 0x00000000df6c3fff] size 0x00004000 gran 0x0e mem64
PCI: 00:00:1c.0 1c <- [0x000000000000d000 - 0x000000000000dfff] size 0x00001000 gran 0x0c seg 00 bus 02 io
PCI: 00:00:1c.0 24 <- [0x00000000df900000 - 0x00000000df9fffff] size 0x00100000 gran 0x14 seg 00 bus 02 prefmem
PCI: 00:00:1c.0 20 <- [0x00000000df800000 - 0x00000000df8fffff] size 0x00100000 gran 0x14 seg 00 bus 02 mem
PCI: 00:02:00.0 10 <- [0x000000000000d000 - 0x000000000000d0ff] size 0x00000100 gran 0x08 io
PCI: 00:02:00.0 18 <- [0x00000000df800000 - 0x00000000df800fff] size 0x00001000 gran 0x0c mem64
PCI: 00:02:00.0 20 <- [0x00000000df900000 - 0x00000000df903fff] size 0x00004000 gran 0x0e prefmem64
PCI: 00:00:1c.1 1c <- [0x000000000000e000 - 0x000000000000ffff] size 0x00002000 gran 0x0c seg 00 bus 03 io
PCI: 00:00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 03 prefmem
PCI: 00:00:1c.1 20 <- [0x00000000dfa00000 - 0x00000000dfbfffff] size 0x00200000 gran 0x14 seg 00 bus 03 mem
PCI: 00:03:00.0 1c <- [0x000000000000e000 - 0x000000000000ffff] size 0x00002000 gran 0x0c seg 00 bus 04 io
PCI: 00:03:00.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 04 prefmem
PCI: 00:03:00.0 20 <- [0x00000000dfa00000 - 0x00000000dfbfffff] size 0x00200000 gran 0x14 seg 00 bus 04 mem
PCI: 00:04:01.0 1c <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x0c seg 00 bus 05 io
PCI: 00:04:01.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 05 prefmem
PCI: 00:04:01.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 05 mem
PCI: 00:04:03.0 1c <- [0x000000000000e000 - 0x000000000000efff] size 0x00001000 gran 0x0c seg 00 bus 06 io
PCI: 00:04:03.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 06 prefmem
PCI: 00:04:03.0 20 <- [0x00000000dfa00000 - 0x00000000dfafffff] size 0x00100000 gran 0x14 seg 00 bus 06 mem
PCI: 00:06:00.0 10 <- [0x000000000000e010 - 0x000000000000e017] size 0x00000008 gran 0x03 io
PCI: 00:06:00.0 14 <- [0x000000000000e020 - 0x000000000000e023] size 0x00000004 gran 0x02 io
PCI: 00:06:00.0 18 <- [0x000000000000e018 - 0x000000000000e01f] size 0x00000008 gran 0x03 io
PCI: 00:06:00.0 1c <- [0x000000000000e024 - 0x000000000000e027] size 0x00000004 gran 0x02 io
PCI: 00:06:00.0 20 <- [0x000000000000e000 - 0x000000000000e00f] size 0x00000010 gran 0x04 io
PCI: 00:06:00.0 24 <- [0x00000000dfa00000 - 0x00000000dfa001ff] size 0x00000200 gran 0x09 mem
PCI: 00:04:05.0 1c <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x0c seg 00 bus 07 io
PCI: 00:04:05.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 07 prefmem
PCI: 00:04:05.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 07 mem
PCI: 00:04:07.0 1c <- [0x000000000000f000 - 0x000000000000ffff] size 0x00001000 gran 0x0c seg 00 bus 08 io
PCI: 00:04:07.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 08 prefmem
PCI: 00:04:07.0 20 <- [0x00000000dfb00000 - 0x00000000dfbfffff] size 0x00100000 gran 0x14 seg 00 bus 08 mem
PCI: 00:08:00.0 10 <- [0x000000000000f010 - 0x000000000000f017] size 0x00000008 gran 0x03 io
PCI: 00:08:00.0 14 <- [0x000000000000f020 - 0x000000000000f023] size 0x00000004 gran 0x02 io
PCI: 00:08:00.0 18 <- [0x000000000000f018 - 0x000000000000f01f] size 0x00000008 gran 0x03 io
PCI: 00:08:00.0 1c <- [0x000000000000f024 - 0x000000000000f027] size 0x00000004 gran 0x02 io
PCI: 00:08:00.0 20 <- [0x000000000000f000 - 0x000000000000f00f] size 0x00000010 gran 0x04 io
PCI: 00:08:00.0 24 <- [0x00000000dfb00000 - 0x00000000dfb001ff] size 0x00000200 gran 0x09 mem
PCI: 00:00:1c.2 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 09 io
PCI: 00:00:1c.2 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 09 prefmem
PCI: 00:00:1c.2 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 seg 00 bus 09 mem
PCI: 00:00:1c.3 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c seg 00 bus 0a io
PCI: 00:00:1c.3 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 seg 00 bus 0a prefmem
PCI: 00:00:1c.3 20 <- [0x00000000df700000 - 0x00000000df7fffff] size 0x00100000 gran 0x14 seg 00 bus 0a mem
PCI: 00:0a:00.0 10 <- [0x00000000df700000 - 0x00000000df707fff] size 0x00008000 gran 0x0f mem64
PCI: 00:00:1d.0 10 <- [0x00000000df6bc000 - 0x00000000df6bc3ff] size 0x00000400 gran 0x0a mem
PNP: 002e.2 60 <- [0x00000000000003f8 - 0x00000000000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.2 70 <- [0x0000000000000004 - 0x0000000000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.5 60 <- [0x0000000000000060 - 0x0000000000000060] size 0x00000001 gran 0x00 io
PNP: 002e.5 62 <- [0x0000000000000064 - 0x0000000000000064] size 0x00000001 gran 0x00 io
PNP: 002e.5 70 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 irq
PNP: 002e.5 72 <- [0x000000000000000c - 0x000000000000000c] size 0x00000001 gran 0x00 irq
PNP: 002e.107 e0 <- [0x000000000000006f - 0x000000000000006e] size 0x00000000 gran 0x00 irq
PNP: 002e.107 e1 <- [0x0000000000000010 - 0x000000000000000f] size 0x00000000 gran 0x00 irq
PNP: 002e.708 f0 <- [0x00000000000000be - 0x00000000000000bd] size 0x00000000 gran 0x00 irq
PNP: 002e.708 f1 <- [0x0000000000000001 - 0x0000000000000000] size 0x00000000 gran 0x00 irq
PNP: 002e.9 e0 <- [0x00000000000000ff - 0x00000000000000fe] size 0x00000000 gran 0x00 irq
PNP: 002e.9 e1 <- [0x0000000000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq
PNP: 002e.109 e4 <- [0x000000000000006f - 0x000000000000006e] size 0x00000000 gran 0x00 irq
PNP: 002e.109 e5 <- [0x0000000000000072 - 0x0000000000000071] size 0x00000000 gran 0x00 irq
PNP: 002e.209 f0 <- [0x000000000000000f - 0x000000000000000e] size 0x00000000 gran 0x00 irq
PNP: 002e.209 f1 <- [0x0000000000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq
PNP: 002e.309 f4 <- [0x00000000000000df - 0x00000000000000de] size 0x00000000 gran 0x00 irq
PNP: 002e.309 f5 <- [0x0000000000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq
PNP: 002e.a e4 <- [0x0000000000000010 - 0x000000000000000f] size 0x00000000 gran 0x00 irq
PNP: 002e.a e5 <- [0x0000000000000012 - 0x0000000000000011] size 0x00000000 gran 0x00 irq
PNP: 002e.a ed <- [0x0000000000000001 - 0x0000000000000000] size 0x00000000 gran 0x00 irq
PNP: 002e.a f0 <- [0x0000000000000030 - 0x000000000000002f] size 0x00000000 gran 0x00 irq
PNP: 002e.b 30 <- [0x00000000000000e1 - 0x00000000000000e0] size 0x00000000 gran 0x00 irq
PNP: 002e.b 60 <- [0x0000000000000290 - 0x0000000000000291] size 0x00000002 gran 0x01 io
PNP: 002e.b 62 <- [0x0000000000000000 - 0x0000000000000001] size 0x00000002 gran 0x01 io
PNP: 002e.b 70 <- [0x0000000000000000 - 0x0000000000000000] size 0x00000001 gran 0x00 irq
PNP: 002e.0 00 <- [0x000000000000002e - 0x000000000000002f] size 0x00000002 gran 0x00 io
PCI: 00:00:1f.2 10 <- [0x000000000000cf78 - 0x000000000000cf7f] size 0x00000008 gran 0x03 io
PCI: 00:00:1f.2 14 <- [0x000000000000cf6c - 0x000000000000cf6f] size 0x00000004 gran 0x02 io
PCI: 00:00:1f.2 18 <- [0x000000000000cf70 - 0x000000000000cf77] size 0x00000008 gran 0x03 io
PCI: 00:00:1f.2 1c <- [0x000000000000cf68 - 0x000000000000cf6b] size 0x00000004 gran 0x02 io
PCI: 00:00:1f.2 20 <- [0x000000000000cf80 - 0x000000000000cf9f] size 0x00000020 gran 0x05 io
PCI: 00:00:1f.2 24 <- [0x00000000df6c8000 - 0x00000000df6cffff] size 0x00008000 gran 0x0f mem
PCI: 00:00:1f.3 10 <- [0x00000000df6bb000 - 0x00000000df6bb0ff] size 0x00000100 gran 0x08 mem64
PCI: 00:00:1f.6 10 <- [0x00000000df6be000 - 0x00000000df6befff] size 0x00001000 gran 0x0c mem64
Done setting resources.
Done allocating resources.
BS: BS_DEV_RESOURCES run times (exec / console): 3 / 1733 ms
Enabling resources...
PCI: 00:00:00.0 subsystem <- 1849/0c00
PCI: 00:00:00.0 cmd <- 06
PCI: 00:00:01.0 bridge ctrl <- 0013
PCI: 00:00:01.0 subsystem <- 1849/0c00
PCI: 00:00:01.0 cmd <- 00
PCI: 00:00:02.0 subsystem <- 1849/0c00
PCI: 00:00:02.0 cmd <- 03
PCI: 00:00:03.0 subsystem <- 1849/0c00
PCI: 00:00:03.0 cmd <- 02
PCI: 00:00:14.0 subsystem <- 1849/0c00
PCI: 00:00:14.0 cmd <- 102
PCI: 00:00:16.0 subsystem <- 1849/0c00
PCI: 00:00:16.0 cmd <- 02
PCI: 00:00:19.0 subsystem <- 1849/0c00
PCI: 00:00:19.0 cmd <- 103
PCI: 00:00:1a.0 subsystem <- 1849/0c00
PCI: 00:00:1a.0 cmd <- 106
PCI: 00:00:1b.0 subsystem <- 1849/0c00
PCI: 00:00:1b.0 cmd <- 102
PCI: 00:00:1c.0 bridge ctrl <- 0013
PCI: 00:00:1c.0 subsystem <- 1849/0c00
PCI: 00:00:1c.0 cmd <- 07
PCI: 00:00:1c.1 bridge ctrl <- 0013
PCI: 00:00:1c.1 subsystem <- 1849/0c00
PCI: 00:00:1c.1 cmd <- 07
PCI: 00:00:1c.2 bridge ctrl <- 0013
PCI: 00:00:1c.2 subsystem <- 1849/0c00
PCI: 00:00:1c.2 cmd <- 00
PCI: 00:00:1c.3 bridge ctrl <- 0013
PCI: 00:00:1c.3 subsystem <- 1849/0c00
PCI: 00:00:1c.3 cmd <- 06
PCI: 00:00:1d.0 subsystem <- 1849/0c00
PCI: 00:00:1d.0 cmd <- 106
PCI: 00:00:1f.0 subsystem <- 1849/0c00
PCI: 00:00:1f.0 cmd <- 107
PCI: 00:00:1f.2 subsystem <- 1849/0c00
PCI: 00:00:1f.2 cmd <- 103
PCI: 00:00:1f.3 subsystem <- 1849/0c00
PCI: 00:00:1f.3 cmd <- 103
PCI: 00:00:1f.6 cmd <- 02
PCI: 00:02:00.0 subsystem <- 1849/0c00
PCI: 00:02:00.0 cmd <- 103
PCI: 00:03:00.0 bridge ctrl <- 0013
PCI: 00:03:00.0 cmd <- 07
PCI: 00:04:01.0 bridge ctrl <- 0013
PCI: 00:04:01.0 cmd <- 00
PCI: 00:04:03.0 bridge ctrl <- 0013
PCI: 00:04:03.0 cmd <- 07
PCI: 00:04:05.0 bridge ctrl <- 0013
PCI: 00:04:05.0 cmd <- 00
PCI: 00:04:07.0 bridge ctrl <- 0013
PCI: 00:04:07.0 cmd <- 07
PCI: 00:06:00.0 cmd <- 03
PCI: 00:08:00.0 cmd <- 03
PCI: 00:0a:00.0 cmd <- 02
done.
BS: BS_DEV_ENABLE run times (exec / console): 0 / 162 ms
Initializing devices...
CPU_CLUSTER: 0 init
LAPIC 0x0 in XAPIC mode.
MTRR: Physical address space:
0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6
0x0000000080000000 - 0x00000000dfffffff size 0x60000000 type 0
0x00000000e0000000 - 0x00000000efffffff size 0x10000000 type 1
0x00000000f0000000 - 0x00000000ffffffff size 0x10000000 type 0
0x0000000100000000 - 0x000000047adfffff size 0x37ae00000 type 6
apic_id 0x0: MTRR: Fixed MSR 0x250 0x0606060606060606
apic_id 0x0: MTRR: Fixed MSR 0x258 0x0606060606060606
apic_id 0x0: MTRR: Fixed MSR 0x259 0x0000000000000000
apic_id 0x0: MTRR: Fixed MSR 0x268 0x0606060606060606
apic_id 0x0: MTRR: Fixed MSR 0x269 0x0606060606060606
apic_id 0x0: MTRR: Fixed MSR 0x26a 0x0606060606060606
apic_id 0x0: MTRR: Fixed MSR 0x26b 0x0606060606060606
apic_id 0x0: MTRR: Fixed MSR 0x26c 0x0606060606060606
apic_id 0x0: MTRR: Fixed MSR 0x26d 0x0606060606060606
apic_id 0x0: MTRR: Fixed MSR 0x26e 0x0606060606060606
apic_id 0x0: MTRR: Fixed MSR 0x26f 0x0606060606060606
apic_id 0x0 setup mtrr for CPU physical address size: 39 bits
MTRR: default type WB/UC MTRR counts: 4/5.
MTRR: WB selected as default type.
MTRR: 0 base 0x0000000080000000 mask 0x0000007fc0000000 type 0
MTRR: 1 base 0x00000000c0000000 mask 0x0000007fe0000000 type 0
MTRR: 2 base 0x00000000e0000000 mask 0x0000007ff0000000 type 1
MTRR: 3 base 0x00000000f0000000 mask 0x0000007ff0000000 type 0

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Initializing VR config.
CPU has 4 cores, 8 threads enabled.
Setting up SMI for CPU
Will perform SMM setup.
microcode: sig=0x306c3 pf=0x2 revision=0x28
Starting cbfs_boot_device
FMAP: area COREBOOT found @ 591000 (2551808 bytes)
Booting from COREBOOT region
CBFS: Found 'cpu_microcode_blob.bin' @0x80 size 0xf800 in mcache @0x7f7fe94c
CPU: Intel(R) Core(TM) i7-4770S CPU @ 3.10GHz.
LAPIC 0x0 in XAPIC mode.
CPU: APIC: 00 enabled
CPU: APIC: 01 enabled
CPU: APIC: 02 enabled
CPU: APIC: 03 enabled
CPU: APIC: 04 enabled
CPU: APIC: 05 enabled
CPU: APIC: 06 enabled
CPU: APIC: 07 enabled
Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
Processing 16 relocs. Offset value of 0x00030000
Attempting to start 7 APs
Waiting for 10ms after sending INIT.
Waiting for SIPI to complete...
LAPIC 0x2 in XAPIC mode.
LAPIC 0x3 in XAPIC mode.
AP: slot 1 apic_id 2, MCU rev: 0x00000028
LAPIC 0x5 in XAPIC mode.
LAPIC 0x4 in XAPIC mode.
AP: slot 4 apic_id 5, MCU rev: 0x00000028
AP: slot 6 apic_id 4, MCU rev: 0x00000028
LAPIC 0x7 in XAPIC mode.
done.
LAPIC 0x1 in XAPIC mode.
Waiting for SIPI to complete...
AP: slot 2 apic_id 1, MCU rev: 0x00000028
done.
AP: slot 3 apic_id 3, MCU rev: 0x00000028
AP: slot 5 apic_id 7, MCU rev: 0x00000028
LAPIC 0x6 in XAPIC mode.
AP: slot 7 apic_id 6, MCU rev: 0x00000028
Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0
Processing 9 relocs. Offset value of 0x00038000
smm_module_setup_stub: stack_top = 0x7f802000
smm_module_setup_stub: per cpu stack_size = 0x400
smm_module_setup_stub: runtime.smm_size = 0x10000
SMM Module: stub loaded at 38000. Will call 0x7f69db9c
Installing permanent SMM handler to 0x7f800000
HANDLER      [0x7fafc000-0x7fafff8f]

CPU 0
  ss0        [0x7fafbc00-0x7fafbfff]
  stub0      [0x7faf4000-0x7faf419f]

CPU 1
  ss1        [0x7fafb800-0x7fafbbff]
  stub1      [0x7faf3c00-0x7faf3d9f]

CPU 2
  ss2        [0x7fafb400-0x7fafb7ff]
  stub2      [0x7faf3800-0x7faf399f]

CPU 3
  ss3        [0x7fafb000-0x7fafb3ff]
  stub3      [0x7faf3400-0x7faf359f]

CPU 4
  ss4        [0x7fafac00-0x7fafafff]
  stub4      [0x7faf3000-0x7faf319f]

CPU 5
  ss5        [0x7fafa800-0x7fafabff]
  stub5      [0x7faf2c00-0x7faf2d9f]

CPU 6
  ss6        [0x7fafa400-0x7fafa7ff]
  stub6      [0x7faf2800-0x7faf299f]

CPU 7
  ss7        [0x7fafa000-0x7fafa3ff]
  stub7      [0x7faf2400-0x7faf259f]

stacks       [0x7f800000-0x7f801fff]
Loading module at 0x7fafc000 with entry 0x7fafc793. filesize: 0x3e50 memsize: 0x3f90
Processing 258 relocs. Offset value of 0x7fafc000
FMAP: area SMMSTORE found @ 510000 (524288 bytes)
smm store: 8 # blocks with size 0x10000
Loading module at 0x7faf4000 with entry 0x7faf4000. filesize: 0x1a0 memsize: 0x1a0
Processing 9 relocs. Offset value of 0x7faf4000
smm_module_setup_stub: stack_top = 0x7f802000
smm_module_setup_stub: per cpu stack_size = 0x400
smm_module_setup_stub: runtime.smm_size = 0x300000
SMM Module: placing smm entry code at 7faf3c00,  cpu # 0x1
SMM Module: placing smm entry code at 7faf3800,  cpu # 0x2
SMM Module: placing smm entry code at 7faf3400,  cpu # 0x3
SMM Module: placing smm entry code at 7faf3000,  cpu # 0x4
SMM Module: placing smm entry code at 7faf2c00,  cpu # 0x5
SMM Module: placing smm entry code at 7faf2800,  cpu # 0x6
SMM Module: placing smm entry code at 7faf2400,  cpu # 0x7
SMM Module: stub loaded at 7faf4000. Will call 0x7fafc793
SMI_STS: PM1 
WAK PWRBTN TMROF smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faec000, cpu = 0
In relocation handler: CPU 0
New SMBASE=0x7faec000 IEDBASE=0x7fc00000
Writing SMRR. base = 0x7f800006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faeb800, cpu = 2
In relocation handler: CPU 2
New SMBASE=0x7faeb800 IEDBASE=0x7fc00000
Writing SMRR. base = 0x7f800006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faeb000, cpu = 4
In relocation handler: CPU 4
New SMBASE=0x7faeb000 IEDBASE=0x7fc00000
Writing SMRR. base = 0x7f800006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faea800, cpu = 6
In relocation handler: CPU 6
New SMBASE=0x7faea800 IEDBASE=0x7fc00000
Writing SMRR. base = 0x7f800006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faeb400, cpu = 3
In relocation handler: CPU 3
New SMBASE=0x7faeb400 IEDBASE=0x7fc00000
Writing SMRR. base = 0x7f800006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faebc00, cpu = 1
In relocation handler: CPU 1
New SMBASE=0x7faebc00 IEDBASE=0x7fc00000
Writing SMRR. base = 0x7f800006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faea400, cpu = 7
In relocation handler: CPU 7
New SMBASE=0x7faea400 IEDBASE=0x7fc00000
Writing SMRR. base = 0x7f800006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faeac00, cpu = 5
In relocation handler: CPU 5
New SMBASE=0x7faeac00 IEDBASE=0x7fc00000
Writing SMRR. base = 0x7f800006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
Initializing CPU #0
CPU: vendor Intel device 306c3
CPU: family 06, model 3c, stepping 03
VMX status: enabled
IA32_FEATURE_CONTROL status: locked
cpu: energy policy set to 6
Turbo is available but hidden
Turbo is available and visible
CPU #0 initialized
Initializing CPU #2
Initializing CPU #4
Initializing CPU #6
CPU: vendor Intel device 306c3
CPU: family 06, model 3c, stepping 03
CPU: vendor Intel device 306c3
CPU: family 06, model 3c, stepping 03
VMX status: enabled
VMX status: enabled
IA32_FEATURE_CONTROL status: locked
IA32_FEATURE_CONTROL status: locked
cpu: energy policy set to 6
cpu: energy policy set to 6
Initializing CPU #5
Initializing CPU #7
CPU: vendor Intel device 306c3
CPU: family 06, model 3c, stepping 03
Initializing CPU #1
Initializing CPU #3
CPU: vendor Intel device 306c3
CPU: family 06, model 3c, stepping 03
CPU: vendor Intel device 306c3
CPU: family 06, model 3c, stepping 03
CPU #6 initialized
CPU #4 initialized
VMX status: enabled
CPU: vendor Intel device 306c3
CPU: family 06, model 3c, stepping 03
VMX status: enabled
CPU: vendor Intel device 306c3
CPU: family 06, model 3c, stepping 03
VMX status: enabled
IA32_FEATURE_CONTROL status: locked
IA32_FEATURE_CONTROL status: locked
cpu: energy policy set to 6
CPU #1 initialized
VMX status: enabled
cpu: energy policy set to 6
CPU #3 initialized
IA32_FEATURE_CONTROL status: locked
IA32_FEATURE_CONTROL status: locked
VMX status: enabled
cpu: energy policy set to 6
IA32_FEATURE_CONTROL status: locked
CPU #5 initialized
cpu: energy policy set to 6
CPU #7 initialized
cpu: energy policy set to 6
CPU #2 initialized
bsp_do_flight_plan done after 531 msecs.
CPU: frequency set to 3900
Enabling SMIs.
Locking SMM.
MTRR: TEMPORARY Physical address space:
0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6
0x0000000080000000 - 0x00000000ff7fffff size 0x7f800000 type 0
0x00000000ff800000 - 0x00000000ffffffff size 0x00800000 type 5
0x0000000100000000 - 0x000000047adfffff size 0x37ae00000 type 6
MTRR: default type WB/UC MTRR counts: 9/5.
MTRR: UC selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
MTRR: 1 base 0x00000000ff800000 mask 0x0000007fff800000 type 5
MTRR: 2 base 0x0000000100000000 mask 0x0000007f00000000 type 6
MTRR: 3 base 0x0000000200000000 mask 0x0000007e00000000 type 6
MTRR: 4 base 0x0000000400000000 mask 0x0000007f80000000 type 6
CPU_CLUSTER: 0 init finished in 864 msecs
PCI: 00:00:00.0 init
Disabling PEG12.
Disabling PEG11.
Disabling "device 4".
Disabling "device 7".
Set BIOS_RESET_CPL
CPU TDP: 65 Watts
PCI: 00:00:00.0 init finished in 11 msecs
PCI: 00:00:01.0 init
PCI: 00:00:01.0 init finished in 0 msecs
PCI: 00:00:02.0 init
Starting cbfs_boot_device
CBFS: Found 'vbt.bin' @0x4d2c0 size 0x566 in mcache @0x7f7feb04
Found a VBT of 6144 bytes
GMA: Found VBT in CBFS
GMA: Found valid VBT in CBFS
GT Power Management Init
framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
                   x_res x y_res: 1920 x 1080, size: 8294400 at 0xe0000000
GT Power Management Init (post VBIOS)
PCI: 00:00:02.0 init finished in 199 msecs
PCI: 00:00:03.0 init
Mini-HD: base = 0xdf6c4000
azalia_audio: initializing Intel Display Audio (HDMI/DP)...
azalia_audio:  - vendor ID:    0x80862807
azalia_audio:  - subsystem ID: 0x80860101
azalia_audio:  - address:      0
azalia_audio: done
PCI: 00:00:03.0 init finished in 24 msecs
PCI: 00:00:14.0 init
PCI: 00:00:14.0 init finished in 0 msecs
PCI: 00:00:16.0 init
ME: FW Partition Table      : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : YES
ME: Manufacturing Mode      : NO
ME: Boot Options Present    : NO
ME: Update In Progress      : NO
ME: Current Working State   : Normal
ME: Current Operation State : M0 with UMA
ME: Current Operation Mode  : Normal
ME: Error Code              : No Error
ME: Progress Phase          : Host Communication
ME: Power Management Event  : Pseudo-global reset
ME: Progress Phase State    : Host communication established
ME: BIOS path: Normal
ME: Extend SHA-256: 270338250cca1d439e1e38229776ad740360322ebaa0afc5e355438989032796
ME MBP: Header: items: 7, size dw: 33
ME: found version 9.1.25.1005
ME: Wake Event to ME Reset:      0 ms
ME: ME Reset to Platform Reset:  0 ms
ME: Platform Reset to CPU Reset: 45 ms
PCI: 00:00:16.0 init finished in 71 msecs
PCI: 00:00:19.0 init
PCI: 00:00:19.0 init finished in 0 msecs
PCI: 00:00:1a.0 init
EHCI: Setting up controller.. done.
PCI: 00:00:1a.0 init finished in 3 msecs
PCI: 00:00:1b.0 init
Azalia: base = 0xdf6c0000
Azalia: codec_mask = 01
azalia_audio: initializing Realtek ALC1150...
azalia_audio:  - vendor ID:    0x10ec0900
azalia_audio:  - subsystem ID: 0x18491151
azalia_audio:  - address:      0
azalia_audio: done
PCI: 00:00:1b.0 init finished in 26 msecs
PCI: 00:00:1c.0 init
Initializing PCH PCIe bridge.
PCI: 00:00:1c.0 init finished in 2 msecs
PCI: 00:00:1c.1 init
Initializing PCH PCIe bridge.
PCI: 00:00:1c.1 init finished in 2 msecs
PCI: 00:00:1c.2 init
Initializing PCH PCIe bridge.
PCI: 00:00:1c.2 init finished in 2 msecs
PCI: 00:00:1c.3 init
Initializing PCH PCIe bridge.
PCI: 00:00:1c.3 init finished in 2 msecs
PCI: 00:00:1d.0 init
EHCI: Setting up controller.. done.
PCI: 00:00:1d.0 init finished in 3 msecs
PCI: 00:00:1f.0 init
pch: lpc_init
IOAPIC: Initializing IOAPIC at fec00000
IOAPIC: ID = 0x00
IOAPIC: 24 interrupts
IOAPIC: Clearing IOAPIC at fec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
EFIVARS: No Firmware Volume header present
EFIVARS: Failed to validate firmware header
Set power off after power failure.
EFIVARS: No Firmware Volume header present
EFIVARS: Failed to validate firmware header
NMI sources disabled.
LynxPoint H PM init
RTC: failed = 0x0
RTC Init
apm_control: Disabling ACPI.
APMC done.
PCI: 00:00:1f.0 init finished in 44 msecs
PCI: 00:00:1f.2 init
SATA: Initializing...
SATA: Controller in AHCI mode.
ABAR: 0xdf6c8000
PCI: 00:00:1f.2 init finished in 6 msecs
PCI: 00:00:1f.3 init
PCI: 00:00:1f.3 init finished in 0 msecs
PCI: 00:00:1f.6 init
PCI: 00:00:1f.6 init finished in 0 msecs
PCI: 00:02:00.0 init
PCI: 00:02:00.0 init finished in 0 msecs
PCI: 00:06:00.0 init
PCI: 00:06:00.0 init finished in 0 msecs
PCI: 00:08:00.0 init
PCI: 00:08:00.0 init finished in 0 msecs
PCI: 00:0a:00.0 init
PCI: 00:0a:00.0 init finished in 0 msecs
PNP: 002e.2 init
PNP: 002e.2 init finished in 0 msecs
PNP: 002e.5 init
PNP: 002e.5 init finished in 0 msecs
PNP: 002e.107 init
PNP: 002e.107 init finished in 0 msecs
PNP: 002e.708 init
PNP: 002e.708 init finished in 0 msecs
PNP: 002e.9 init
PNP: 002e.9 init finished in 0 msecs
PNP: 002e.109 init
PNP: 002e.109 init finished in 0 msecs
PNP: 002e.209 init
PNP: 002e.209 init finished in 0 msecs
PNP: 002e.309 init
PNP: 002e.309 init finished in 0 msecs
PNP: 002e.a init
PNP: 002e.a init finished in 0 msecs
PNP: 002e.b init
PNP: 002e.b init finished in 0 msecs
PNP: 002e.516 init
PNP: 002e.516 init finished in 0 msecs
Devices initialized
BS: BS_DEV_INIT run times (exec / console): 515 / 941 ms
Finalize devices...
PCI: 00:00:00.0 final
PCI: 00:00:16.0 final
ME: MBP cleared
ME: mkhi_end_of_post
ME: END OF POST message successful (0)
EFIVARS: No Firmware Volume header present
EFIVARS: Failed to validate firmware header
PCI: 00:00:1b.0 final
PCI: 00:00:1f.0 final
apm_control: Finalizing SMM.
APMC done.
Devices finalized
BS: BS_POST_DEVICE run times (exec / console): 5 / 30 ms
Starting cbfs_boot_device
CBFS: Found 'fallback/dsdt.aml' @0x4b0c0 size 0x219e in mcache @0x7f7fead8
Starting cbfs_boot_device
CBFS: 'fallback/slic' not found.
ACPI: Writing ACPI tables at 7f62c000.
ACPI:    * FACS
ACPI:    * FACP
ACPI: added table 1/32, length now 44
Found 1 CPU(s) with 8 core(s) each.
PSS: 3101MHz power 65000 control 0x2700 status 0x2700
PSS: 3100MHz power 65000 control 0x1f00 status 0x1f00
PSS: 2400MHz power 46335 control 0x1800 status 0x1800
PSS: 2000MHz power 36810 control 0x1400 status 0x1400
PSS: 1600MHz power 28039 control 0x1000 status 0x1000
PSS: 1200MHz power 19998 control 0xc00 status 0xc00
PSS: 800MHz power 12661 control 0x800 status 0x800
PSS: 3101MHz power 65000 control 0x2700 status 0x2700
PSS: 3100MHz power 65000 control 0x1f00 status 0x1f00
PSS: 2400MHz power 46335 control 0x1800 status 0x1800
PSS: 2000MHz power 36810 control 0x1400 status 0x1400
PSS: 1600MHz power 28039 control 0x1000 status 0x1000
PSS: 1200MHz power 19998 control 0xc00 status 0xc00
PSS: 800MHz power 12661 control 0x800 status 0x800
PSS: 3101MHz power 65000 control 0x2700 status 0x2700
PSS: 3100MHz power 65000 control 0x1f00 status 0x1f00
PSS: 2400MHz power 46335 control 0x1800 status 0x1800
PSS: 2000MHz power 36810 control 0x1400 status 0x1400
PSS: 1600MHz power 28039 control 0x1000 status 0x1000
PSS: 1200MHz power 19998 control 0xc00 status 0xc00
PSS: 800MHz power 12661 control 0x800 status 0x800
PSS: 3101MHz power 65000 control 0x2700 status 0x2700
PSS: 3100MHz power 65000 control 0x1f00 status 0x1f00
PSS: 2400MHz power 46335 control 0x1800 status 0x1800
PSS: 2000MHz power 36810 control 0x1400 status 0x1400
PSS: 1600MHz power 28039 control 0x1000 status 0x1000
PSS: 1200MHz power 19998 control 0xc00 status 0xc00
PSS: 800MHz power 12661 control 0x800 status 0x800
PSS: 3101MHz power 65000 control 0x2700 status 0x2700
PSS: 3100MHz power 65000 control 0x1f00 status 0x1f00
PSS: 2400MHz power 46335 control 0x1800 status 0x1800
PSS: 2000MHz power 36810 control 0x1400 status 0x1400
PSS: 1600MHz power 28039 control 0x1000 status 0x1000
PSS: 1200MHz power 19998 control 0xc00 status 0xc00
PSS: 800MHz power 12661 control 0x800 status 0x800
PSS: 3101MHz power 65000 control 0x2700 status 0x2700
PSS: 3100MHz power 65000 control 0x1f00 status 0x1f00
PSS: 2400MHz power 46335 control 0x1800 status 0x1800
PSS: 2000MHz power 36810 control 0x1400 status 0x1400
PSS: 1600MHz power 28039 control 0x1000 status 0x1000
PSS: 1200MHz power 19998 control 0xc00 status 0xc00
PSS: 800MHz power 12661 control 0x800 status 0x800
PSS: 3101MHz power 65000 control 0x2700 status 0x2700
PSS: 3100MHz power 65000 control 0x1f00 status 0x1f00
PSS: 2400MHz power 46335 control 0x1800 status 0x1800
PSS: 2000MHz power 36810 control 0x1400 status 0x1400
PSS: 1600MHz power 28039 control 0x1000 status 0x1000
PSS: 1200MHz power 19998 control 0xc00 status 0xc00
PSS: 800MHz power 12661 control 0x800 status 0x800
PSS: 3101MHz power 65000 control 0x2700 status 0x2700
PSS: 3100MHz power 65000 control 0x1f00 status 0x1f00
PSS: 2400MHz power 46335 control 0x1800 status 0x1800
PSS: 2000MHz power 36810 control 0x1400 status 0x1400
PSS: 1600MHz power 28039 control 0x1000 status 0x1000
PSS: 1200MHz power 19998 control 0xc00 status 0xc00
PSS: 800MHz power 12661 control 0x800 status 0x800
Generating ACPI PIRQ entries
\_SB.PCI0.LPCB.SIO0: PNP: 002e.0
\_SB.PCI0.LPCB.SIO0.L020: PNP: 002e.2
\_SB.PCI0.LPCB.SIO0.L050: PNP: 002e.5
PNP: 002e.107: Ignoring virtual LDN
PNP: 002e.708: Ignoring virtual LDN
\_SB.PCI0.LPCB.SIO0.L090: PNP: 002e.9
PNP: 002e.109: Ignoring virtual LDN
PNP: 002e.209: Ignoring virtual LDN
PNP: 002e.309: Ignoring virtual LDN
\_SB.PCI0.LPCB.SIO0.L0A0: PNP: 002e.a
\_SB.PCI0.LPCB.SIO0.L0B0: PNP: 002e.b
PNP: 002e.516: Ignoring virtual LDN
ACPI:    * SSDT
ACPI: added table 2/32, length now 52
ACPI:    * MCFG
ACPI: added table 3/32, length now 60
IOAPIC: 24 interrupts
ACPI:    * APIC
ACPI: added table 4/32, length now 68
ACPI:    * SPCR
ACPI: added table 5/32, length now 76
current = 7f631060
ACPI:    * DMAR
ACPI: added table 6/32, length now 84
ACPI:    * HPET
ACPI: added table 7/32, length now 92
current = 7f631160
ACPI: done.
ACPI tables: 20832 bytes.
smbios_write_tables: 7f624000
SMBIOS firmware version is set to coreboot_version: '25.12-538-g142ae8491ce9-dirty'
Create SMBIOS type 16
Create SMBIOS type 17
Create SMBIOS type 20
SMBIOS tables: 1353 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 8079
Writing coreboot table at 0x7f650000
CFR: Written 16 bytes of CFR structures at 0x7f650018, with CRC32 0x00000000
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000a0000-00000000000f5fff: RESERVED
 3. 00000000000f6000-00000000000f6fff: CONFIGURATION TABLES
 4. 00000000000f7000-00000000000fffff: RESERVED
 5. 0000000000100000-000000007f623fff: RAM
 6. 000000007f624000-000000007f67cfff: CONFIGURATION TABLES
 7. 000000007f67d000-000000007f7c9fff: RAMSTAGE
 8. 000000007f7ca000-000000007f7fffff: CONFIGURATION TABLES
 9. 000000007f800000-00000000841fffff: RESERVED
10. 00000000f0000000-00000000f3ffffff: RESERVED
11. 00000000fed10000-00000000fed19fff: RESERVED
12. 00000000fed80000-00000000fed84fff: RESERVED
13. 00000000fed90000-00000000fed91fff: RESERVED
14. 0000000100000000-000000047adfffff: RAM
FMAP: area SMMSTORE found @ 510000 (524288 bytes)
smm store: 8 # blocks with size 0x10000
Starting cbfs_boot_device
Wrote coreboot table at: 0x7f650000, 0x474 bytes, checksum 9c2f
coreboot table: 1164 bytes.
IMD ROOT    0. 0x7f7ff000 0x00001000
IMD SMALL   1. 0x7f7fe000 0x00001000
CONSOLE     2. 0x7f7de000 0x00020000
TIME STAMP  3. 0x7f7dd000 0x00000910
MEM INFO    4. 0x7f7db000 0x000010c8
AFTER CAR   5. 0x7f7ca000 0x00011000
RAMSTAGE    6. 0x7f67c000 0x0014e000
SMM BACKUP  7. 0x7f66c000 0x00010000
SMM COMBUFFER 8. 0x7f65c000 0x00010000
IGD OPREGION 9. 0x7f658000 0x00003200
COREBOOT   10. 0x7f650000 0x00008000
ACPI       11. 0x7f62c000 0x00024000
SMBIOS     12. 0x7f624000 0x00008000
IMD small region:
  IMD ROOT    0. 0x7f7fec00 0x00000400
  RO MCACHE   1. 0x7f7fe920 0x000002c8
  FMAP        2. 0x7f7fe800 0x0000010a
  ROMSTAGE    3. 0x7f7fe7e0 0x00000004
  ROMSTG STCK 4. 0x7f7fe720 0x000000a8
  ACPI GNVS   5. 0x7f7fe660 0x000000b0
BS: BS_WRITE_TABLES run times (exec / console): 2 / 562 ms
Starting cbfs_boot_device
CBFS: Found 'fallback/payload' @0x577c0 size 0x12061d in mcache @0x7f7feb78
Checking segment from ROM address 0xffde87ec
Checking segment from ROM address 0xffde8808
Loading segment from ROM address 0xffde87ec
  code (compression=1)
  New segment dstaddr 0x00800000 memsize 0x800000 srcaddr 0xffde8824 filesize 0x1205e5
Loading Segment: addr: 0x00800000 memsz: 0x0000000000800000 filesz: 0x00000000001205e5
using LZMA
Loading segment from ROM address 0xffde8808
  Entry Point 0x008021d8
BS: BS_PAYLOAD_LOAD run times (exec / console): 325 / 46 ms
ICH-NM10-PCH: watchdog disabled
Jumping to boot code at 0x008021d8(0x7f650000)