Nick: MrChromebox E-mail: none Board: google/lulu Contents: flashrom MrChromebox-v1.5.0-devel (git:v1.4.0-94-g4b42de3726) on Linux 6.9.3-76060903-generic (x86_64) flashrom was built with GCC 11.4.0, little endian Command line (13 args): ./flashrom_15 -p internal --ifd -i bios -w bios.bin -V -c W25Q64BV/W25Q64CV/W25Q64FV -o flashrom.log -N Initializing internal programmer Found candidate at: 00000500-00000528 Found coreboot table at 0x00000500. Found candidate at: 00000000-000004a8 Found coreboot table at 0x00000000. coreboot table found at 0x78e27000. coreboot header(24) checksum: 839f table(1168) checksum: e5fa entries: 40 Vendor ID: Google, part ID: Lulu Using Internal DMI decoder. DMI string chassis-type: "Laptop" Laptop detected via DMI. DMI string system-manufacturer: "GOOGLE" DMI string system-product-name: "Lulu" DMI string system-version: "1.0" DMI string baseboard-manufacturer: "GOOGLE" DMI string baseboard-product-name: "Lulu" DMI string baseboard-version: "1.0" Found chipset "Intel Broadwell U Base" with PCI ID 8086:9cc5. Enabling flash write... Root Complex Register Block address = 0xfed1c000 GCS = 0x21: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (SPI) Top Swap: not enabled 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x4 0x7fffffff/0x7fffffff FWH IDSEL: 0x5 0x7fffffff/0x7fffffff FWH IDSEL: 0x6 0x7fffffff/0x7fffffff FWH IDSEL: 0x7 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled Maximum FWH chip size: 0x100000 bytes SPI Read Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled SPIBAR = 0x00007e4db9f98000 + 0x3800 0x04: 0xe009 (HSFS) HSFS: FDONE=1, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 SPI Configuration is locked down. Reading OPCODES... done OP Type Pre-OP op[0]: 0x01, write w/o addr, none op[1]: 0x02, write w/ addr, none op[2]: 0x03, read w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x20, write w/ addr, none op[5]: 0x9f, read w/o addr, none op[6]: 0xd8, write w/ addr, none op[7]: 0x0b, read w/ addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x50 0x06: 0x0300 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=3, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x00004243 (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x42, BRRA 0x43 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x07ff0200 FREG1: BIOS region (0x00200000-0x007fffff) is read-write. 0x5C: 0x01ff0001 FREG2: Management Engine region (0x00001000-0x001fffff) is locked. 0x60: 0x00007fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x00007fff FREG4: Platform Data region is unused. Not all flash regions are freely accessible by flashrom. This is most likely due to an active ME. Please see https://flashrom.org/ME for details. 0x74: 0x00000000 (PR0 is unused) 0x78: 0x00000000 (PR1 is unused) 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) At least some flash regions are read protected. You have to use a flash layout and include only accessible regions. For write operations, you'll additionally need the --noverify-all switch. See manpage for more details. 0x90: 0x84 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf94130 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=3, DBC=1, SME=0, SCF=1 0x94: 0x5006 (PREOP) 0x96: 0xb32d (OPTYPE) 0x98: 0x05030201 (OPMENU) 0x9c: 0x0bd89f20 (OPMENU+4) 0xa0: 0x00000000 (BBAR) 0xc4: 0x80000000 (LVSCC) LVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0, VCL=0 0xc8: 0x00000000 (UVSCC) UVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x0 0xd0: 0x50444653 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x02040003 FLMAP1 0x15100206 FLMAP2 0x00210120 --- Details --- NR (Number of Regions): 3 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH/SoC Strap Length): 21 FISBA/FPSBA (Flash ICH/PCH/SoC Strap Base Addr): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 1 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x09300044 FLILL 0x00000000 --- Details --- Component 1 density: 8 MB Component 2 is not used. Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 33 MHz Write and Erase Clock Freq.: 33 MHz Fast Read is supported. Fast Read Clock Frequency: 33 MHz Dual Output Fast Read Support: disabled No forbidden opcodes. === Region Section === FLREG0 0x00000000 FLREG1 0x07ff0200 FLREG2 0x01ff0001 --- Details --- Region 0 (Descr. ) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x00200000 - 0x007fffff Region 2 (ME ) 0x00001000 - 0x001fffff === Master Section === FLMSTR1 0x02030000 FLMSTR2 0x04050000 FLMSTR3 0x00000118 --- Details --- Descr. BIOS ME GbE Platf. BIOS r rw ME r rw GbE OK. No board enable found matching coreboot IDs vendor="Google", model="Lulu". The following protocols are supported: SPI. Probing for Winbond W25Q64BV/W25Q64CV/W25Q64FV, 8192 kB: compare_id: id1 0xef, id2 0x4017 Added layout entry 00000000 - 007fffff named complete flash Found Winbond flash chip "W25Q64BV/W25Q64CV/W25Q64FV" (8192 kB, SPI) mapped at physical address 0x00000000ff800000. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set Chip status register: Sector Protect Size (SEC) is 64 KB Chip status register: Top/Bottom (TB) is top Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set Chip status register 2 is NOT decoded! This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Skipping writeprotect-based unlocking for read/verify operations. Block protection is disabled. Reading ich descriptor... read_flash: region (00000000..0x7fffff) is readable, reading range (00000000..0x000fff). done. Assuming chipset '8 series Lynx Point'. Added layout entry 00000000 - 00000fff named fd Added layout entry 00200000 - 007fffff named bios Added layout entry 00001000 - 001fffff named me Using region: "bios". coreboot last image size (not ROM size) is 8388608 bytes. Manufacturer: Google Mainboard ID: Lulu This coreboot image matches this mainboard. spi_read_register: read from register 2 not supported by programmer. wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. spi_read_register: read from register 2 not supported by programmer. wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. spi_read_register: read from register 2 not supported by programmer. wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. spi_read_register: read from register 2 not supported by programmer. wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. spi_read_register: read from register 2 not supported by programmer. wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. write_wp_bits: wp_verify reg:1 value:0x0 spi_read_register: read from register 2 not supported by programmer. wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. write_wp_bits: wp_verify reg:2 value:0x0 spi_read_register: read from register 2 not supported by programmer. wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. write_wp_bits: wp_verify reg:1 value:0x0 spi_read_register: read from register 2 not supported by programmer. wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. write_wp_bits: wp_verify reg:2 value:0x0 Reading old flash chip contents... read_flash: region (00000000..0x7fffff) is readable, reading range (0x200000..0x7fffff). done. Updating flash chip contents... erase_write: region (00000000..0x7fffff) is writable, erasing range (0x200000..0x7fffff). 0x554000..0x554fff verify_range: Verifying region (00000000..0x7fffff) read_flash: region (00000000..0x7fffff) is readable, reading range (0x554000..0x554fff). E(554000:554fff)0x555000..0x555fff verify_range: Verifying region (00000000..0x7fffff) read_flash: region (00000000..0x7fffff) is readable, reading range (0x555000..0x555fff). E(555000:555fff)0x556000..0x556fff verify_range: Verifying region (00000000..0x7fffff) read_flash: region (00000000..0x7fffff) is readable, reading range (0x556000..0x556fff). E(556000:556fff)0x557000..0x557fff verify_range: Verifying region (00000000..0x7fffff) read_flash: region (00000000..0x7fffff) is readable, reading range (0x557000..0x557fff). E(557000:557fff)0x6f8000..0x6f8fff verify_range: Verifying region (00000000..0x7fffff) read_flash: region (00000000..0x7fffff) is readable, reading range (0x6f8000..0x6f8fff). E(6f8000:6f8fff)0x6f9000..0x6f9fff verify_range: Verifying region (00000000..0x7fffff) read_flash: region (00000000..0x7fffff) is readable, reading range (0x6f9000..0x6f9fff). E(6f9000:6f9fff)0x6fa000..0x6fafff verify_range: Verifying region (00000000..0x7fffff) read_flash: region (00000000..0x7fffff) is readable, reading range (0x6fa000..0x6fafff). E(6fa000:6fafff)0x6fb000..0x6fbfff verify_range: Verifying region (00000000..0x7fffff) read_flash: region (00000000..0x7fffff) is readable, reading range (0x6fb000..0x6fbfff). E(6fb000:6fbfff)0x6fc000..0x6fcfff verify_range: Verifying region (00000000..0x7fffff) read_flash: region (00000000..0x7fffff) is readable, reading range (0x6fc000..0x6fcfff). E(6fc000:6fcfff)0x6fd000..0x6fdfff verify_range: Verifying region (00000000..0x7fffff) read_flash: region (00000000..0x7fffff) is readable, reading range (0x6fd000..0x6fdfff). E(6fd000:6fdfff)0x6fe000..0x6fefff verify_range: Verifying region (00000000..0x7fffff) read_flash: region (00000000..0x7fffff) is readable, reading range (0x6fe000..0x6fefff). E(6fe000:6fefff)0x7d6000..0x7d6fff verify_range: Verifying region (00000000..0x7fffff) read_flash: region (00000000..0x7fffff) is readable, reading range (0x7d6000..0x7d6fff). E(7d6000:7d6fff)0x7fd000..0x7fdfff verify_range: Verifying region (00000000..0x7fffff) read_flash: region (00000000..0x7fffff) is readable, reading range (0x7fd000..0x7fdfff). E(7fd000:7fdfff)0x7fe000..0x7fefff verify_range: Verifying region (00000000..0x7fffff) read_flash: region (00000000..0x7fffff) is readable, reading range (0x7fe000..0x7fefff). E(7fe000:7fefff)0x7ff000..0x7fffff verify_range: Verifying region (00000000..0x7fffff) read_flash: region (00000000..0x7fffff) is readable, reading range (0x7ff000..0x7fffff). E(7ff000:7fffff)Invalid OPCODE 0x06, will not execute. spi_write_cmd failed during command execution at address 0x558000 Erase/write done from 200000 to 7fffff Write Failed!Uh oh. Erase/write failed. Your flash chip is in an unknown state. Get help on IRC (see https://www.flashrom.org/Contact) or mail flashrom@flashrom.org with the subject "FAILED: "!------------------------------------------------------------------------------- DO NOT REBOOT OR POWEROFF! spi_read_register: read from register 2 not supported by programmer. wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. spi_read_register: read from register 2 not supported by programmer. wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. spi_read_register: read from register 2 not supported by programmer. wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. write_wp_bits: wp_verify reg:1 value:0x0 spi_read_register: read from register 2 not supported by programmer. wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. write_wp_bits: wp_verify reg:2 value:0x0 spi_read_register: read from register 2 not supported by programmer. wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. write_wp_bits: wp_verify reg:1 value:0x0 spi_read_register: read from register 2 not supported by programmer. wp_read_register: read from register 2 not is supported by programmer, writeprotect operations will assume it contains 0x00. write_wp_bits: wp_verify reg:2 value:0x0 Restoring MMIO space at 0x7e4db9f9b8a0