Nick: GNUtoo
E-mail: none
Board: M4A785T-M
Contents: 


coreboot-4.9-192-g747d2e3e42 Sun Jan  6 20:41:59 UTC 2019 romstage starting...
BSP Family_Model: 00100f62
*sysinfo range: [000c4e20,000cf38c]
bsp_apicid = 00
cpu_init_detectedx = 00000000
CBFS @ 200 size ffe00
CBFS: 'Master Header Locator' located CBFS at [200:100000)
CBFS: Locating 'microcode_amd.bin'
CBFS: 'microcode_amd.bin' not found.
[microcode] microcode file not found. Skipping updates.
cpuSetAMDMSR  done
Enter amd_ht_init
FMAP: Found "FLASH" version 1.1 at 0.
FMAP: base = fff00000 size = 100000 #area = 3
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
No CMOS option 'hypertransport_speed_limit'.
Exit amd_ht_init
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
  F3x80: e600e681
  F3x84: 80e641e6
  F3xD4: c8810f24
  F3xD8: 03001016
  F3xDC: 0000532a
core0 started: 
start_other_cores()
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
init node: 00  cores: 01 pass 1
Start other core - nodeid: 00  cores: 01
started ap aicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
* AP 01started

rs780_early_setup()
fam10_optimization()
rs780_por_init
sb700_early_setup()
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
No CMOS option 'sata_ahci_mode'.
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4sb700_devices_por_init(): SATA Device, BDF:0-17-0
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
No CMOS option 'cpu_c_states'.
sb700_pmio_por_init()

Begin FIDVID MSR 0xc0010071 0x30bc0073 0x44035440
FIDVID on BSP, APIC_id: 00
BSP fid = 10600
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
get_boot_apic_id: using 0 as APIC ID for node 0, core 0
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
Wait for AP stage 1: ap_apicid = 1init_fidvid_bsp_stage1: timed out reading from ap 01
common_fid = 10600
FID Change Node:00, F3xD4: c8810f26
End FIDVIDMSR 0xc0010071 0x30bc0073 0x3c005440
rs780_htinit cpu_ht_freq=b.
rs780_htinit: HT3 mode
...WARM RESET...


soft_reset() called!


coreboot-4.9-192-g747d2e3e42 Sun Jan  6 20:41:59 UTC 2019 romstage starting...
BSP Family_Model: 00100f62
*sysino range: [000c4e20,000cf38c]
bsp_apicid = 00
cpu_init_detectedx = 00000000
CBFS @ 200 size ffe00
CBFS: 'Master Header Locator' located CBFS at [200:100000)
CBFS: Locating 'microcode_amd.bin'
CBFS: 'microcode_amd.bin' not found.
[microcode] microcode file not found. Skipping updates.
cpuSetAMDMSR  done
Enter amd_ht_init
FMAP: Found "FLASH" version 1.1 at 0.
FMAP: base = fff00000 size = 100000 #areas = 3
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
No CMOS option 'hypertransport_speed_limit'.
Exit amd_ht_init
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
  F3x80: e600e68
  F3x84: 80e641e6
  F3xD4: c8810f26
  F3xD8: 03001016
  F3xDC: 0000532a
core0 started: 
start_other_cores()
NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
init node: 00  cores: 01 pass 1
Start other core - nodeid: 00  cores: 01
started ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead.
get_boot_apic_id: using 1 as APIC ID for node 0, core 1
* AP 01started

rs780_early_setup()
fam10_optimization()
rs780_por_init
sb700_early_setup()
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBS: Found @ offset 39840 size 48c
No CMOS option 'sata_ahci_mode'.
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-17-0
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
No CMOS option 'cpu_c_states'.
sb700_pmio_por_init()

Begin FIDVID MSR 0xc000071 0x30bc0073 0x3c005440
End FIDVIDMSR 0xc0010071 0x30bc0073 0x3c001c0e
rs780_htinit cpu_ht_freq=b.
rs780_htinit: HT3 mode
fill_mem_ctrl()
Timestamp - before ram initialization: 970117052
raminit_amdmct()
raminit_amdmct begin:
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
mctAutoInitMCT_D: mct_init Node 0
mctAutoInitMCT_D: mct_InitialMCT_D
mct_InitialMCT_D: clear_legacy_Mode
mctAutoInitMCT_D: mctSMBhub_Init
mctAutoInitMCT_D: mct_preInitDCT
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
No CMOS option 'dimm_spd_checksum'.	 DIMMPresence: DIMMValid=1
	 DIMMPresence: DIMMPresent=1
	 DIMMPresence: RegDIMMPresent=0
	 DIMMPresence: LRDIMMPresent=0
	 DIMMPresence: DimmECCPresent=0
	 DIMMPresence: DimmPARPresent=0
	 DIMMPresence: Dimmx4Present=0
	 DIMMPresence: Dimmx8Present=1
	 DIMMPresence: Dimmx16Present=0
	 DIMMPresence: DimmPlPresent=0
	 DIMMPresence: DimmDRPresent=0
	 DIMMPresence: DimmQRPresent=0
	 DIMMPresence: DATAload[0]=1
	 DIMMPresence: MAload[0]=8
	 DIMMPresence: MAdimms[0]=1
	 DIMMPresence: DATAload[1]=0
	 DIMMPresence: MAload[1]=0
	 DIMMPresence: MAdimms[1]=0
	 DIMMPresence: Status 2000
	 DIMMPresence: ErrStatus 0
	 DIMMresence: ErrCode 0
	 DIMMPresence: Done

		DCTPreInit_D: mct_DIMMPresence Done
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
No CMOS option 'allow_spd_nvram_cache_restore'.
mctAutoInitMCT_D: mct_init Node 1
mctAutoInitMCT_D: mct_init Node 2
mctAutoInitMCT_D: mct_init Node 3
mctAutoInitMCT_D: mct_init Node 4
mctAutoInitMCT_D: mct_init Node 5
mctAutoInitMCT_D: mct_init Node 6
mctAutoInitMCT_D: mct_init Node 7
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
WARNING: No CMOS option 'allow_spd_nvram_cache_restore'.
mctAutoInitMCT_D: mctSMBhub_Init
mctAutoInitMCT_D: mct_initDCTSPDCalcWidth: Status 2000
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
		DCTInit_D: mct_SPDCalcWidth Done
AutoCycTiming_D: Start
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
mctGet_MaxLoadFreq: Channel 1: 1 DIMM(s) detected
mctGet_MaxLoadFreq: Channel 2: 0 DIMM(s) detected
mct_MaxLoadFreq: unbuffered DIMMs on 1500mV channel; limiting to DDR3-1333
GetPresetmaxF_D: Start
GetPresetmaxF_D: Done
SPDGetTCL_D: Start
SPDGetTCL_D: DIMMCASL 6
SPDGetTCL_D: DIMMAutoSpeed 4
SPDGetTCL_D: Status 2000
SPDGetTCL_D: ErrStatus 
SPDGetTCL_D: ErrCode 0
SPDGetTCL_D: Done

SPD2ndTiming: Start
SPD2ndTiming: Done
AutoCycTiming: Status 2000
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done

		DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent 1
SPDSetBanks: Status 2000
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done

AfterStich pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7fffff
StitchMemory: Status 2000
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done

FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
InterleaveBanks_D: Status 2000
InterleaveBanks_D: ErrStatus 80
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done

AutoConfig_D: DramControl:     00002a06
AutoConfig_D: DramTimingLo:    00090092
AutoConfig_D: DramConfigMisc:  00000000
AutoConfig_D: DramConfigMisc2: 00000040
AutoConfig_D: DramConfigLo:    08010000
AutoConfig_D: DramConfigHi:    0f48000b
mct_SetDramConfigHi_D: Start
mctSetDramConfigHi_D: DramConfigHi:    1f48010b
mct_SetDramConfigHi_D: Done
mct_EarlyArbEn_D: Start
mct_EarlyArbEn_D: Done
AutoConfig: Status 2000
AutoConfig: ErrStatus 80
AutoConfig: ErrCode 0
AutoConfig: Done

		DCTInit_D: AutoConfig_D Done
set_2t_configuration: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatfomSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00000000 20113222
mct_PlatformSpec: Done
InitPhyCompensation: DCT 0: Start
InitPhyCompensation: DCT 0: Done
		DCTInit_D: PlatformSpec_D Done
		DCTFinalInit_D: StartupDCT_D Start
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
mct_DCTAccessDone: Start
mct_DCTAccessDone: Done
Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00020040
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 0 rank 0 MR3 control word 00030000
mct_SendMrsCmd: Start
mct_SendMrsCd: Done
Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00010006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00000528
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
mct_SendZQCmd: Start
mct_SendZQCmd: Done
mct_SendZQCmd: Start
mct_SendZQCmd: Done
mct_DCTAccessDone: Start
mct_DCTAccessDone: Done
mct_DramInit_Sw_D: Done
		DCTFinalInit_D: StartupDCT_D Done
mctAutoInitMCT_D: SyncDCTsReady_D
mctAutoInitMCT_D: HTMemMapInit_D
 Node: 00  base: 00  limit: 7fffff  BottomIO: a00000
 Node: 00  base: 03  limit: 7fffff
 Node: 01  base: 00  limit: 00
 Node: 02  base: 00  limit: 00
 Node: 03  base: 00  limit: 00
 Node: 04  base: 00  limit: 0
 Node: 05  base: 00  limit: 00
 Node: 06  base: 00  limit: 00
 Node: 07  base: 00  limit: 00
mctAutoInitMCT_D: CPUMemTyping_D
	 CPUMemTyping: Cache32bTOP:800000
	 CPUMemTyping: Bottom32bIO:800000
	 CPUMemTyping: Bottom40bIO:0
mctAutoInitMCT_D: mctHookAfterCPU
mctAutoInitMCT_D: DQSTiming_D
phyAssistedMemFnceTraining: Start
phyAssistedMemFnceTraining: Done
AgesaHwWlPhase1: training nibble 0
Programmed DCT 0 write levelling ODT pattern 00000001 from DIMM 0 data
	Lane 00 initial seed: 000d
	Lane 01 initial seed: 000d
	Lane 02 initial seed: 000d
	Lane 03 initial seed: 000d
	Lane 04 intial seed: 000d
	Lane 05 initial seed: 000d
	Lane 06 initial seed: 000d
	Lane 07 initial seed: 000d
	Lane 00 nibble 0 raw readback: 0008
	Lane 00 nibble 0 adjusted value (pre nibble): 0008
	Lane 00 nibble 0 adjusted value (post nibble): 0008
	Lane 01 nibble 0 raw readback: 000d
	Lane 01 nibble 0 adjusted value (pre nibble): 000d
	Lane 01 nibble 0 adjusted value (post nibble): 000d
	Lane 02 nibble 0 raw readback: 0011
	Lane 02 nibble 0 adjusted value (pre nibble): 0011
	Lane 02 nibble 0 adjusted value (post nibble): 0011
	Lane 03 nibble 0 raw readback: 0017
	Lane 03 nibble 0 adjusted value (pre nibble): 0017
	Lane 03 nibble 0 adjusted value (post nibble): 0017
	Lane 04 nibble 0 raw readback: 001c
	Lane 04 nibble 0 adjusted value (pre nibble): 01c
	Lane 04 nibble 0 adjusted value (post nibble): 001c
	Lane 05 nibble 0 raw readback: 001d
	Lane 05 nibble 0 adjusted value (pre nibble): 001d
	Lane 05 nibble 0 adjusted value (post nibble): 001d
	Lane 06 nibble 0 raw readback: 001f
	Lane 06 nibble 0 adjusted value (pre nibble): 001f
	Lane 06 nibble 0 adjusted value (post nibble): 001f
	Lane 07 nibble 0 raw readback: 001f
	Lane 07 nibble 0 adjusted value (pre nibble): 001f
	Lane 07 nibble 0 adjusted value (post nibble): 001f
SetTargetFreq: Start
SetTargetFreq: Node 0: New frequency code: 0006
ChangeMemClk: Start
ChangeMemClk: Done
SetTargetFreq: Done
SPD2ndTiming: Start
SPD2ndTiming: Done
set_2t_configurtion: Start
set_2t_configuration: Done
mct_BeforePlatformSpec: Start
mct_BeforePlatformSpec: Done
mct_PlatformSpec: Start
Programmed DCT 0 timing/termination pattern 00000000 20113222
mct_PlatformSpec: Done
mct_BeforeDramInit_Prod_D: Start
mct_ProgramODT_D: Start
mct_ProgramODT_D: Done
mct_BeforeDramInit_Prod_D: Done
mct_DramInit_Sw_D: Start
Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00020050
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 0 rank 0 MR3 control word 00030000
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00010006
mct_SendMrsCmd: Start
mct_SendMrsCmd: Done
Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00000b58
mct_SenMrsCmd: Start
mct_SendMrsCmd: Done
mct_DramInit_Sw_D: Done
AgesaHwWlPhase1: training nibble 0
Programmed DCT 0 write levelling ODT pattern 00000001 from DIMM 0 data
	Lane 00 new seed: 000d
	Lane 01 new seed: 0015
	Lane 02 new seed: 001c
	Lane 03 new seed: 0026
	Lane 04 new seed: 002e
	Lane 05 new seed: 0030
	Lane 06 new seed: 0033
	Lane 07 new seed: 0033
	Lane 00 nibble 0 raw readback: 0011
	Lane 00 nibble 0 adjusted value (pre nibble): 0011
	Lane 00 nibble 0 adjusted value (post nibble): 0011
	Lane 01 nibble 0 raw readback: 0019
	Lane 01 nibble 0 adjusted value (pre nibble): 0019
	Lane 01 nibble 0 adjusted value (post nibble): 0019
	Lane 02 nibble 0 raw readback: 001e
	Lane 02 nibble 0 adjusted vlue (pre nibble): 001e
	Lane 02 nibble 0 adjusted value (post nibble): 001e
	Lane 03 nibble 0 raw readback: 0025
	Lane 03 nibble 0 adjusted value (pre nibble): 0025
	Lane 03 nibble 0 adjusted value (post nibble): 0025
	Lane 04 nibble 0 raw readback: 002b
	Lane 04 nibble 0 adjusted value (pre nibble): 002b
	Lane 04 nibble 0 adjusted value (post nibble): 002b
	Lane 05 nibble 0 raw readback: 002f
	Lane 05 nibble 0 adjusted value (pre nibble): 002f
	Lane 05 nibble 0 adjusted value (post nibble): 002f
	Lane 06 nibble 0 raw readback: 0035
	Lane 06 nibble 0 adjusted value (pre nibble): 0035
	Lane 06 nibble 0 adjusted value (post nibble): 0035
	Lane 07 nibble 0 raw readback: 0038
Lane 07 nibble 0 adjusted value (pre nibble): 0038
	Lane 07 nibble 0 adjusted value (post nibble): 0038
TrainRcvrEn: Status 2000
TrainRcvrEn: ErrStatus 80
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done

TrainDQSRdWrPos: Status 2000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 80
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
mctAutoInitMCT_D: UMAMemTyping_D
mctAutoInitMCT_D: :OtherTiming
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
No CMOS option 'interleave_nodes'.
InterleaveNodes_D: Status 2000
InterleaveNodes_D: ErrStatus 80
InterleaveNodes_D: ErrCode 0
InterleaveNodes_D: Done

InterleaveChannels_D: Node 0
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 80
InterleaveChannels_D: ErrCode 0
IntrleaveChannels_D: Node 1
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 2
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 3
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 4
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 5
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
Interleavehannels_D: ErrCode 0
InterleaveChannels_D: Node 6
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 7
InterleaveChannels_D: Status 2000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Done

mctAutoInitMCT_D Done: Global Status: 0
raminit_amdmct end:
Timestamp - after ram initialization: 7841021933
CBMEM:
IMD: root @ 6ffff000 24 entries.
IMD: root @ 6fffec00 62 entries.
Timestamp - start of romstage: 2532512
Timestamp - before ram initialization: 782223920
Timestamp - after ram initialization: 7653128801
amdmct_cbmem_store_info: Storing AMDMCT configuration in CBMEM
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
No CMOS option 'ecc_scrub_rate'.
BSP overran lower stack boundary.  Undefined behaviour may result!
Timestamp - end of romstage: 7995019967
CBFS @ 200 size ffe00
CBFS: 'Master Header Locator' located CBFS at [200:100000)
CBFS: Locating 'fallback/rmstage'
CBFS: Found @ offset 27ac0 size 116d5
Timestamp - starting to load ramstage: 8061199004
Timestamp - starting LZMA decompress (ignore for x86): 8075153309
Timestamp - finished LZMA decompress (ignore for x86): 8238800726
Timestamp - finished loading ramstage: 8257042029


coreboot-4.9-192-g747d2e3e42 Sun Jan  6 20:41:59 UTC 2019 ramstage starting...
Moving GDT to 6fffe9e0...ok
Timestamp - start of ramstage: 8302238267
BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0
Timestamp - device enumeration: 8327042615
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3833 exit 0
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
DOMAIN: 0000: enabled 1
APIC: 00: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1
CI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 0
PCI: 00:04.0: enabled 0
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:09.0: enabled 0
PCI: 00:0a.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1:enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:05.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 1
PNP: 002e.2: enabled 0
PNP: 002e.3: enabled 0
PNP: 002e.4: enabled 0
PNP: 002e.5: enabled 1
PNP: 002e.6: enabled 1
PNP: 002e.7: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.a: enabled 0
Compare with tree...
Root Device: enabled 1
 CPU_CLUSTE: 0: enabled 1
  APIC: 00: enabled 1
 DOMAIN: 0000: enabled 1
  PCI: 00:18.0: enabled 1
   PCI: 00:00.0: enabled 1
   PCI: 00:01.0: enabled 1
    PCI: 00:05.0: enabled 1
   PCI: 00:02.0: enabled 1
   PCI: 00:03.0: enabled 0
   PCI: 00:04.0: enabled 0
   PCI: 00:05.0: enabled 0
   PCI: 00:06.0: enabled 0
   PCI: 00:07.0: enabled 0
   PCI: 00:08.0: enabled 0
   PCI: 00:09.0: enabled 0
   PCI: 00:0a.0: enabled 1
   PCI: 00:11.0: enabled 1
   PCI: 00:12.0: enabled 1
   PCI: 00:12.1: enabled 1
   PCI: 00:12.2: enabled 1
   PCI: 00:13.0: enabled 1
   PCI: 00:13.1: enabled 1
   PCI: 00:13.2: enabled 1
   PCI: 00:14.0: enabled 1
    I2C: 00:50: enabled 1
    I2C: 00:51: enabled 1
    I2C: 00:52: enbled 1
    I2C: 00:53: enabled 1
   PCI: 00:14.1: enabled 1
   PCI: 00:14.2: enabled 1
   PCI: 00:14.3: enabled 1
    PNP: 002e.0: enabled 0
    PNP: 002e.1: enabled 1
    PNP: 002e.2: enabled 0
    PNP: 002e.3: enabled 0
    PNP: 002e.4: enabled 0
    PNP: 002e.5: enabled 1
    PNP: 002e.6: enabled 1
    PNP: 002e.7: enabled 0
    PNP: 002e.8: enabled 0
    PNP: 002e.9: enabled 0
    PNP: 002e.a: enabled 0
   PCI: 00:14.4: enabled 1
   PCI: 00:14.5: enabled 1
  PCI: 00:18.1: enabled 1
  PCI: 00:18.2: enabled 1
  PCI: 00:18.3: enabled 1
  PCI: 00:1.4: enabled 1
Mainboard enable. dev=0x00e23220
Init adt7461 end, status 0x02 fd
Root Device scanning...
root_dev_scan_bus for Root Device
setup_bsp_ramtop, TOP MEM: msr.lo = 0x80000000, msr.hi = 0x00000000
setup_bsp_ramtop, TOP MEM2: msr.lo = 0x00000000, msr.hi = 0x00000000
setup_uma_memory: uma size 0x10000000, memory start 0x70000000
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
CPU_CLUSTER: 0 scanning...
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
No CMOS option 'compute_unit_siblings'.
  PCI: 00:18.3 siblings=1
CPU: APIC: 00 enabled
CPU: APIC: 01 enabled
scan_bus: scanning of bus CPU_CLUSTER: 0 took 3355 usecs
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:18.0 [1022/1200] bus ops
PCI: 00:18.0 [1022/1200] enabled
PCI: 00:18.1 [1022/1201] enabled
PCI: 00:18.2 [1022/1202] enabled
PCI: 00:18.3 [1022/1203] ops
PCI: 00:18.3 [1022/1203] enabled
PCI: 00:18.4 [1022/1204] ops
PCI: 00:18.4 [1022/1204] enabled
PCI: 00:18.0 scanning...
do_hypertransport_scan_chain for bus 00
rs780_enable: dev=00e24dc0, VID_DID=0x96011022
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()addr=e0000000,bus=0,devfn=40
gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
NB_PCI_REG04 = 6.
NB_PCI_REG84 = 3000095.
NB_PCI_REG4C = 52042.
PCI: 00:00.0 [1022/9601] enabled
Capability: type 0x08 @ 0xc4
flags: 0x0181
PCI: pci_scan_bus for bus 00
PCI: pci_scan_bus limits devfn 0 - devfn ffffffff
PCI: pci_scan_bus upper limit too big. Using 0xff.
rs780_enable: dev=00e24dc0, VID_DID=0x96011022
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
NB_PCI_REG04 = 6.
NB_PCI_REG84 = 3000095.
NB_PCI_REG4C = 52042.
PCI: 00:00.0 [1022/9601] enabled
rs780_enable: dev=00e24d20, VID_DID=0x96021022
Bus-0, Dev-1, Fun-0.
GC is accessible fro now on.
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0x44
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
PCI: 00:01.0 [1022/9602] enabled
rs780_enable: dev=00e24c40, VID_DID=0x96031022
Bus-0, Dev-2,3, Fun-0. enable=1
rs780_gfx_init, nb_dev=0x00e24dc0, dev=0x00e24c40, port=0x2.
misc 28 = 1
rs780_gfx_init step5.9.12.1.
rs780_gfx_init step5.9.12.3.
rs780_gfx_init step5.9.12.9.
rs780_gfx_init step1.
device = 2
rs780_gfx_init single_port_configuration.PcieLinkTraining port=2:lc current state=2030400
rs780_gfx_init single_port_configuration step12.
rs780_gfx_init single_port_configuration step13.
rs780_gfx_init single_port_configuration step14.
PCI: Static device PCI: 00:02.0 not found, disabling it.
rs780_enable: dev=00e24ba0, VID_DID=0xffffffff
Bus-0, Dev-2,3, Fun-0. enable=0
rs780_enable: dev=00e24b00, VID_DID=0xffffffff
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=00e24a60, VID_DID=0xffffffff
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=00e249c0, VID_DID=0xffffffff
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=00e24920, VID_DID=0xffffffff
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=00e24880, VID_DID0x960a1022
Bus-0, Dev-8, Fun-0. enable=0
rs780_enable: dev=00e247e0, VID_DID=0x96081022
Bus-0, Dev-9, 10, Fun-0. enable=0
rs780_enable: dev=00e24740, VID_DID=0x96091022
Bus-0, Dev-9, 10, Fun-0. enable=1
gpp_sb_init nb_dev=0x0, dev=0x50, port=0xa
PcieLinkTraining port=a:lc current state=a0b0f10
addr=e0000000,bus=0,devfn=50
PcieTrainPort reg=0x10000
PcieTrainPort port=0xa result=1
disable_pcie_bar3()
rs780 unused GPP ports bitmap=0x2fc, force disabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability:type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:0a.0 subordinate bus PCI Express
PCI: 00:0a.0 [1022/9609] enabled
sb7xx_51xx_enable()
PCI: 00:11.0 [1002/4390] ops
PCI: 00:11.0 [1002/4390] enabled
sb7xx_51xx_enable()
PCI: 00:12.0 [1002/4397] ops
PCI: 00:12.0 [1002/4397] enabled
sb7xx_51xx_enable()
PCI: 00:12.1 [1002/4398] ops
PCI: 00:12.1 [1002/4398] enabled
sb7xx_51xx_enable(
PCI: 00:12.2 [1002/4396] ops
PCI: 00:12.2 [1002/4396] enabled
sb7xx_51xx_enable()
PCI: 00:13.0 [1002/4397] ops
PCI: 00:13.0 [1002/4397] enabled
sb7xx_51xx_enable()
PCI: 00:13.1 [1002/4398] ops
PCI: 00:13.1 [1002/4398] enabled
sb7xx_51xx_enable()
PCI: 00:13.2 [1002/4396] ops
PCI: 00:13.2 [1002/4396] enabled
sb7xx_51xx_enable()
PCI: 00:14.0 [1002/4385] bus ops
PCI: 00:14.0 [1002/4385]enabled
sb7xx_51xx_enable()
PCI: 00:14.1 [1002/439c] ops
PCI: 00:14.1 [1002/439c] enabled
sb7xx_51xx_enable()
PCI: 00:14.2 [1002/4383] ops
PCI: 00:14.2 [1002/4383] enabled
sb7xx_51xx_enable()
PCI: 00:14.3 [1002/439d] bus ops
PCI: 00:14.3 [1002/439d] enabled
sb7xx_51xx_enable()
PCI: 00:14.4 [1002/4384] bus ops
PCI: 00:14.4 [1002/4384] enabled
sb7xx_51xx_enable()
PCI: 00:14.5 [1002/4399] ops
PCI: 00:14.5 [1002/4399] enabled
PCI: 00:18.0 [1022/1200] bus ops
PCI: 00:18.0 [1022/1200] enabled
PCI: 00:18.1 [1022/1201] enabled
PCI: 00:18.2 [1022/1202] enabled
PCI: 00:18.3 [1022/1203] ops
PCI: 00:18.3 [1022/1203] enabled
PCI: 00:18.4 [1022/1204] ops
PCI: 00:18.4 [1022/1204] enabled
CI: 00:01.0 scanning...
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
rs780_enable: dev=00e23e00, VID_DID=0x97101002
Bus-0, Dev-4,5,6,7, Fun-0. enable=1
gpp_sb_init nb_dev=0x0, dev=0x28, port=0x5
PcieLinkTraining port=5:lc current state=0
PcieTrainPort port=0x5 result=0
PCI: 01:05.0 [1002/0000] ops
rs780_internal_gfx_enable dev = 0x00e23e00, nb_dev = 0x00e24dc0.
Sysmem TOM = 0_80000000
Sysmem TOM2 = 0_0
PCI: 01:05.0 [1002/9710] enabled
scan_bus: scanning of bus PCI: 00:01.0 took 81474 usecs
PCI: 00:0a.0 scanning...
do_pci_scan_brdge for PCI: 00:0a.0
PCI: pci_scan_bus for bus 02
PCI: 02:00.0 [10ec/8168] enabled
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Failed to enable LTR for dev = CI: 02:00.0
scan_bus: scanning of bus PCI: 00:0a.0 took 41558 usecs
PCI: 00:14.0 scanning...
scan_generic_bus for PCI: 00:14.0
bus: PCI: 00:14.0[0]->I2C: 01:50 enabled
bus: PCI: 00:14.0[0]->I2C: 01:51 enabled
bus: PCI: 00:14.0[0]->I2C: 01:52 enabled
bus: PCI: 00:14.0[0]->I2C: 01:53 enabled
scan_generic_bus for PCI: 00:14.0 done
scan_bus: scanning of bus PCI: 00:14.0 took 23504 usecs
PCI: 00:14.3 scanning...
scan_lpc_bus for PCI: 00:14.3
PNP: 002e.0 disabled
PNP: 002e.1 enabled
PNP: 002e.2 disabled
PNP: 002e.3 disabled
PNP: 002e.4 disabled
PNP: 002e.5 enabled
PNP: 002e.6 enabled
PNP: 002e.7 disabled
PNP: 002e.8 disabled
PNP: 002e.9 disabled
PNP: 002e.a disabled
can_lpc_bus for PCI: 00:14.3 done
scan_bus: scanning of bus PCI: 00:14.3 took 29320 usecs
PCI: 00:14.4 scanning...
do_pci_scan_bridge for PCI: 00:14.4
PCI: pci_scan_bus for bus 03
PCI: 03:05.0 [168c/0029] enabled
PCI: 03:06.0 [1095/0680] ops
PCI: 03:06.0 [1095/0680] enabled
scan_bus: scanning of bus PCI: 00:14.4 took 16702 usecs
PCI: 00:18.0 scanning...
scan_bus: scanning of bus PCI: 00:18.0 took 2271 usecs
scan_bus: scanning of bus PCI: 00:18.0 took 728766 usecs
DOMAIN: 0000 passpw: enabled
scan_bus: scanning of bus DOMAIN: 0000 took 764343 usecs
root_dev_scan_bus for Root Device done
scan_bus: scanning of bus Root Device took 838484 usecs
done
S: BS_DEV_ENUMERATE times (us): entry 0 run 1083354 exit 0
Timestamp - device configuration: 11619937767
found VGA at PCI: 01:05.0
Setting up VGA for PCI: 01:05.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
Adding PCIe enhanced config space BAR 0xc0000000-0xd0000000.
DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:18.0 read_resources bus 0 link: 0
PCI: 00:00.0 register 1c(00000004), read-only ignoring it
PCI: 00:0.0 read_resources bus 1 link: 0
rs780_gfx_read_resources.
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:0a.0 read_resources bus 2 link: 0
PCI: 00:0a.0 read_resources bus 2 link: 0 done
PCI: 00:14.0 read_resources bus 1 link: 0
I2C: 01:50 missing read_resources
I2C: 01:51 missing read_resources
I2C: 01:52 missing read_resources
I2C: 01:53 missing read_resources
PCI: 00:14.0 read_resources bus 1 link: 0 done
PCI: 00:14.3 read_resources bus 0 link: 0
PCI: 00:14.3 read_resources bus 0 link: 0 done
PCI: 00:14.4 read_resources bus 3 link: 0
PCI: 00:14.4 read_resources bus 3 link: 0 done
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840size 48c
PCI: 00:18.0 read_resources bus 0 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 1
PCI: 00:18.0 read_resources bus 0 link: 1 done
PCI: 00:18.0 read_resources bus 0 link: 2
PCI: 00:18.0 read_resources bus 0 link: 2 done
PCI: 00:18.0 read_resources bus 0 link: 3
PCI: 00:18.0 read_resources bus 0 link: 3 done
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
PCI: 00:18.4 read_resources bus 0 link: 0
PCI: 00:18.4 read_resources bus 0 link: 0 done
PCI: 00:18.4 read_resources bus 0 link: 1
PCI: 00:18.4 read_resources bus 0 link: 1 done
PCI: 00:18.4 read_resources bus 0 link: 2
PCI: 00:18.4 read_resources bus 0 link: 2 doe
PCI: 00:18.4 read_resources bus 0 link: 3
PCI: 00:18.4 read_resources bus 0 link: 3 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 CPU_CLUSTER: 0
  CPU_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
   APIC: 01
  DOMAIN: 0000 child on link 0 PCI: 00:18.0
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
  DOMAIN: 0000 resource base c0000000 size 1000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
  DOMAIN: 0000 resource base 0 size 80000000 align 0 gran 0 limit 0 flags e0004200 index 7
   PCI: 00:18.0 child on link 0 PCI: 00:00.0
   PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 10d8
   PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 10b8
   PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 10b0
    PCI: 00:00.0
    PCI: 00:01.0 child on link 0 PCI: 01:05.0
    PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit 1ffffff flags 80102 index 1c
    PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81202 index 24
    PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
     PCI: 01:05.0
     PCI: 01:05.0 resource base 0 size 8000000 align 27 gran 27 limit ffffffff flags 1200 index 10
     PCI: 01:05.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
     PCI: 01:05.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 200 index 18
    PCI: 01:05.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 24
    PCI: 00:02.0
    PCI: 00:03.0
    PCI: 00:04.0
    PCI: 00:05.0
    PCI: 00:06.0
    PCI: 00:07.0
    PCI: 00:08.0
    PCI: 00:09.0
    PCI: 00:0a.0 child on link 0 PCI: 02:00.0
    PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
    PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
    PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
     PCI: 02:00.0
     PCI: 02:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
     PCI: 02:00.0 resource base 0 size 1000 lign 12 gran 12 limit ffffffffffffffff flags 1201 index 18
     PCI: 02:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
     PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
    PCI: 00:11.0
    PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
    PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
    PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
    PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
    PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
    PCI: 00:11.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 24
    PCI: 00:12.0
    PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:12.1
    PCI: 00:12.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:12.2
    PCI: 00:122 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
    PCI: 00:13.0
    PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:13.1
    PCI: 00:13.1 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:13.2
    PCI: 00:13.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
    PCI: 00:14.0 child on link 0 I2C: 01:50
    PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
    PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c
    PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
    PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
    PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58
     I2C: 01:50
     I2C: 01:51
     I2C: 01:52
     I2C: 01:53
    PCI: 00:14.1
    PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flgs 100 index 10
    PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
    PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
    PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
    PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
    PCI: 00:14.2
    PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
    PCI: 00:14.3 child on link 0 PNP: 002e.0
    PCI: 00:14.3 resource base 0 size 1 align 12 gran 0 limit ffffffff flags 200 index a0
    PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
    PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
    PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
     PNP: 002e.0
     PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
     PNP: 002e.0 resource base 0 size 1 algn 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
     PNP: 002e.1
     PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
     PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.2
     PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
     PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.3
     PNP: 002e.3 resource base 378 size 4 align 2 gran 2 limit fff flags c0000100 index 60
     PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
     PNP: 002e.4
     PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
     PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
     PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.5
     PNP: 002e.5 resource base 60 size 1 align 0 gra 0 limit fff flags c0000100 index 60
     PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit fff flags c0000100 index 62
     PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.6
     PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.7
     PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit fff flags 100 index 60
     PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
     PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 64
     PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.8
     PNP: 002e.8 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
     PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.9
     PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit fff flags 100 index 60
     PNP: 002e.a
     PNP: 002e.a resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
     PNP: 002e.a resource base 0 size 1 alin 0 gran 0 limit 0 flags 400 index 70
    PCI: 00:14.4 child on link 0 PCI: 03:05.0
    PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
    PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
    PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
     PCI: 03:05.0
     PCI: 03:05.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 200 index 10
     PCI: 03:06.0
     PCI: 03:06.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
     PCI: 03:06.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
     PCI: 03:06.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
     PCI: 03:06.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
     PCI: 03:06.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
     PCI: 03:06.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index24
     PCI: 03:06.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30
    PCI: 00:14.5
    PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 00:18.0
    PCI: 00:18.1
    PCI: 00:18.2
    PCI: 00:18.3
    PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
    PCI: 00:18.4
   PCI: 00:18.1
   PCI: 00:18.2
   PCI: 00:18.3
   PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
   PCI: 00:18.4
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:18.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: 1ffffff
PCI: 01:05.0 14 * [0x0 - 0xff] io
PCI: 00:01.0 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:0a.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 02:00.0 10 *  [0x0 - 0xff] io
PCI: 00:0a.0 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:14.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 03:06.0 20 *  [0x0 - 0xf] io
PCI: 03:06.0 10 *  [0x10 - 0x17] io
PCI: 03:06.0 18 *  [0x18 - 0x1f] io
PCI: 03:06.0 14 *  [0x20 - 0x23] io
PCI: 03:06.0 1c *  [0x24 - 0x27] io
PCI: 00:14.4 io: base: 28 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:01.0 1c *  [0x0 - 0xfff] io
PCI: 00:0a.0 1c *  [0x1000 - 0x1fff] io
PCI: 00:14.4 1c *  [0x2000 - 0x2fff] io
PCI: 00:11.0 20 *  [0x3000 - 0x300f] io
PCI: 00:14.1 20 *  [0x3010 - 0x301f] io
PCI: 00:11.0 10 *  [0x3020 - 0x3027] io
PCI: 00:11.0 18 *  [0x3028 - 0x302f] io
PCI: 00:14.1 10 *  [0x3030 - 0x3037] io
PCI: 00:14.1 18 *  [0x3038 - 0x303f] io
PCI: 00:11.0 14 *  [0x3040 - 0x3043] io
PCI: 00:11.0 1c *  [0x3044 - 0x3047] io
PCI: 00:14.1 14 *  [0x3048 - 0x304b] io
PCI: 00:14.1 1c *  [0x304c - 0x304f] io
PCI: 00:18.0 io: base: 3050 size: 4000 align: 12 gran: 12 limit: ffff done
PCI: 00:18.0 10d8 *  [0x0 - 0x3fff] io
DOMAIN: 0000 io: base: 4000 size: 4000 align: 12 gran: 0 limit: ffff done
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:18.0 prefmm: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 01:05.0 10 *  [0x0 - 0x7ffffff] prefmem
PCI: 00:01.0 prefmem: base: 8000000 size: 8000000 align: 27 gran: 20 limit: ffffffff done
PCI: 00:0a.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 02:00.0 20 *  [0x0 - 0x3fff] prefmem
PCI: 02:00.0 18 *  [0x4000 - 0x4fff] prefmem
PCI: 00:0a.0 prefmem: base: 5000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:01.0 24 *  [0x0 - 0x7ffffff] prefmem
PCI: 00:0a.0 24 *  [0x8000000 - 0x80fffff] prefmem
PCI: 00:18.0 prefmem: base: 8100000 size: 8100000 align: 27 gran: 20 limit: ffffffff done
PCI: 00:18.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:05.0 24 *  [0x0 - 0xfffff] mem
PCI: 01:05.0 18 *  [0x100000 - 0x10ffff] mem
PCI: 00:01.0 mem: base: 11000 size: 200000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:0a.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 02:00.0 30 *  [0x0 - 0xffff] mem
PCI: 00:0a.0 mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 03:06.0 30 *  [0x0 - 0x7ffff] mem
PCI: 03:05.0 10 *  [0x80000 - 0x8ffff] mem
PCI: 03:06.0 24 *  [0x90000 - 0x900ff] mem
PCI: 00:14.4 mem: base: 90100 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:18.3 94 *  [0x0 - 0x3ffffff] mem
PCI: 00:01.0 20 *  [0x4000000 - 0x41fffff] mem
PCI: 00:0a.0 20 *  [0x4200000 - 0x42fffff] mem
PCI: 00:14.4 20 *  [0x4300000 - 0x43fffff] mem
PCI: 00:14.2 10 *  [0x4400000 - 0x4403fff] mem
PCI: 00:12.0 10 *  [0x4404000 - 0x4404fff] mem
PCI: 00:12.1 10 *  [0x4405000 - 0x4405fff mem
PCI: 00:13.0 10 *  [0x4406000 - 0x4406fff] mem
PCI: 00:13.1 10 *  [0x4407000 - 0x4407fff] mem
PCI: 00:14.5 10 *  [0x4408000 - 0x4408fff] mem
PCI: 00:11.0 24 *  [0x4409000 - 0x44093ff] mem
PCI: 00:12.2 10 *  [0x440a000 - 0x440a0ff] mem
PCI: 00:13.2 10 *  [0x440b000 - 0x440b0ff] mem
PCI: 00:14.3 a0 *  [0x440c000 - 0x440c000] mem
PCI: 00:18.0 mem: base: 440c001 size: 4500000 align: 26 gran: 20 limit: ffffffff done
PCI: 00:18.0 10b8 *  [0x0 - 0x80fffff] prefmem
PCI: 00:18.0 10b0 *  [0xc000000 - 0x104fffff] mem
PCI: 00:18.3 94 *  [0x14000000 - 0x17ffffff] mem
DOMAIN: 0000 mem: base: 18000000 size: 18000000 align: 27 gran: 0 limit: ffffffff done
avoid_fixed_resources:DOMAIN: 0000
avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: DOMAIN: 0000 c0010058 base c0000000 limit cfffffff mem (fixed)
constrain_resources: DOMAIN: 0000 07 base 00000000 limit 7fffffff mem (fixed)
constrain_resources: PCI: 00:14.0 90 base 00000b00 limit 00000b0f io (fixed)
constrain_resources: PCI: 00:14.0 58 base 00000b20 limit 00000b2f io (fixed)
constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed)
avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff
avoid_fixed_resources:@DOMAIN: 0000 10000100 base a8000000 limit bfffffff
Setting resources...
DOMAIN: 0000 io: base:1000 size:4000 align:12 gran:0 limit:ffff
PCI: 00:18.0 10d8 *  [0x1000 - 0x4fff] io
DOMAIN: 0000 io: next_base: 5000 size: 4000 align: 12 gran: 0 done
PCI: 00:18.0 io: base:1000 size:4000 align:12 gran:12 limit:4fff
PCI: 00:01.0 1c *  [0x1000 - 0x1fff] io
PCI: 00:0a.0 1c *  [0x2000 - 0x2fff] io
PCI: 00:14.4 1c *  [0x3000 - 0x3fff] io
PCI: 00:11.0 20 *  [0x4000 - 0x400f] io
PCI: 00:14.1 20 * [0x4010 - 0x401f] io
PCI: 00:11.0 10 *  [0x4020 - 0x4027] io
PCI: 00:11.0 18 *  [0x4028 - 0x402f] io
PCI: 00:14.1 10 *  [0x4030 - 0x4037] io
PCI: 00:14.1 18 *  [0x4038 - 0x403f] io
PCI: 00:11.0 14 *  [0x4040 - 0x4043] io
PCI: 00:11.0 1c *  [0x4044 - 0x4047] io
PCI: 00:14.1 14 *  [0x4048 - 0x404b] io
PCI: 00:14.1 1c *  [0x404c - 0x404f] io
PCI: 00:18.0 io: next_base: 4050 size: 4000 align: 12 gran: 12 done
PCI: 00:01.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff
PCI: 01:05.0 14 *  [0x1000 - 0x10ff] io
PCI: 00:01.0 io: next_base: 1100 size: 1000 align: 12 gran: 12 done
PCI: 00:0a.0 io: base:2000 size:1000 align:12 gran:12 limit:2fff
PCI: 02:00.0 10 *  [0x2000 - 0x20ff] io
PCI: 00:0a.0 io: next_ase: 2100 size: 1000 align: 12 gran: 12 done
PCI: 00:14.4 io: base:3000 size:1000 align:12 gran:12 limit:3fff
PCI: 03:06.0 20 *  [0x3000 - 0x300f] io
PCI: 03:06.0 10 *  [0x3010 - 0x3017] io
PCI: 03:06.0 18 *  [0x3018 - 0x301f] io
PCI: 03:06.0 14 *  [0x3020 - 0x3023] io
PCI: 03:06.0 1c *  [0x3024 - 0x3027] io
PCI: 00:14.4 io: next_base: 3028 size: 1000 align: 12 gran: 12 done
DOMAIN: 0000 mem: base:a8000000 size:18000000 align:27 gran:0 limit:bfffffff
PCI: 00:18.0 10b8 *  [0xa8000000 - 0xb00fffff] prefmem
PCI: 00:18.0 10b0 *  [0xb4000000 - 0xb84fffff] mem
PCI: 00:18.3 94 *  [0xbc000000 - 0xbfffffff] mem
DOMAIN: 0000 mem: next_base: c0000000 size: 18000000 align: 27 gran: 0 done
PCI: 00:18.0 prefme: base:a8000000 size:8100000 align:27 gran:20 limit:b00fffff
PCI: 00:01.0 24 *  [0xa8000000 - 0xafffffff] prefmem
PCI: 00:0a.0 24 *  [0xb0000000 - 0xb00fffff] prefmem
PCI: 00:18.0 prefmem: next_base: b0100000 size: 8100000 align: 27 gran: 20 done
PCI: 00:01.0 prefmem: base:a8000000 size:8000000 align:27 gran:20 limit:afffffff
PCI: 01:05.0 10 *  [0xa8000000 - 0xafffffff] prefmem
PCI: 00:01.0 prefmem: next_base: b0000000 size: 8000000 align: 27 gran: 20 done
PCI: 00:0a.0 prefmem: base:b0000000 size:100000 align:20 gran:20 limit:b00fffff
PCI: 02:00.0 20 *  [0xb0000000 - 0xb0003fff] prefmem
PCI: 02:00.0 18 *  [0xb0004000 - 0xb0004fff] prefmem
PCI: 00:0a.0 prefmem: next_base: b0005000 size: 100000 align: 20 gran: 20 done
PCI: 00:14.4 prefmem: base:b00fffff size:0 align:20 gran:20 limit:b00fffff
PCI: 00:14.4 prefmem: next_base: b00fffff size: 0 align: 20 gran: 20 done
PCI: 00:18.0 mem: base:b4000000 size:4500000 align:26 gran:20 limit:b84fffff
PCI: 00:18.3 94 *  [0xb4000000 - 0xb7ffffff] mem
PCI: 00:01.0 20 *  [0xb8000000 - 0xb81fffff] mem
PCI: 000a.0 20 *  [0xb8200000 - 0xb82fffff] mem
PCI: 00:14.4 20 *  [0xb8300000 - 0xb83fffff] mem
PCI: 00:14.2 10 *  [0xb8400000 - 0xb8403fff] mem
PCI: 00:12.0 10 *  [0xb8404000 - 0xb8404fff] mem
PCI: 00:12.1 10 *  [0xb8405000 - 0xb8405fff] mem
PCI: 00:13.0 10 *  [0xb8406000 - 0xb8406fff] mem
PCI: 00:13.1 10 *  [0xb8407000 - 0xb8407fff] mem
PCI: 00:14.5 10 *  [0xb8408000 - 0xb8408fff] mem
PCI: 00:11.0 24 *  [0xb8409000 - 0xb84093ff] mem
PCI: 00:12.2 10 *  [0xb840a000 - 0xb840a0ff] mem
PCI: 00:13.2 10 *  [0xb840b000 - 0xb840b0ff] mem
PCI: 00:14.3 a0 *  [0xb840c000 - 0xb840c000] mem
PCI: 00:18.0 mem: next_base: b840c001 size: 4500000 align: 26 gran: 20 done
PCI: 0:01.0 mem: base:b8000000 size:200000 align:20 gran:20 limit:b81fffff
PCI: 01:05.0 24 *  [0xb8000000 - 0xb80fffff] mem
PCI: 01:05.0 18 *  [0xb8100000 - 0xb810ffff] mem
PCI: 00:01.0 mem: next_base: b8110000 size: 200000 align: 20 gran: 20 done
PCI: 00:0a.0 mem: base:b8200000 size:100000 align:20 gran:20 limit:b82fffff
PCI: 02:00.0 30 *  [0xb8200000 - 0xb820ffff] mem
PCI: 00:0a.0 mem: next_base: b8210000 size: 100000 align: 20 gran: 20 done
PCI: 00:14.4 mem: base:b8300000 size:100000 align:20 gran:20 limit:b83fffff
PCI: 03:06.0 30 *  [0xb8300000 - 0xb837ffff] mem
PCI: 03:05.0 10 *  [0xb8380000 - 0xb838ffff] mem
PCI: 03:06.0 24 *  [0xb8390000 - 0xb83900ff] mem
PCI: 00:14.4 mem: next_base: b8390100 size: 100000 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
0: mmio_basek=002a0000, basek=00000300, limitk=00200000
DOMAIN: 0000 assign_resources, bus 0 link: 0
VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device
PCI: 00:18.0 11b8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem <node 0 link 0>
PCI: 00:18.0 10d8 <- [0x0000001000 - 0x0000004fff] size 0x00004000 gran 0x0c io node 0 link 0>
PCI: 00:18.0 10b8 <- [0x00a8000000 - 0x00b00fffff] size 0x08100000 gran 0x14 prefmem <node 0 link 0>
PCI: 00:18.0 10b0 <- [0x00b4000000 - 0x00b84fffff] size 0x04500000 gran 0x14 mem <node 0 link 0>
PCI: 00:18.0 assign_resources, bus 0 link: 0
PCI: 00:01.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00a8000000 - 0x00afffffff] size 0x08000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00b8000000 - 0x00b81fffff] size 0x00200000 gran 0x14 bus 01 mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 01:05.0 10 <- [0x00a8000000 - 0x00afffffff] size 0x08000000 gran 0x1b prefmem
PCI: 01:05.0 14 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 01:05.0 18 <- [0x00b8100000 - 0x00b810ffff] size 0x00010000 gran 0x10 mem
PCI: 01:05.0 24 <- [0x00b8000000 - 0x00b80fffff] size 0x00100000 gran 0x14 mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 00:0a.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 02 io
PCI: 00:0a.0 24 <- [0x00b0000000 - 0x0000fffff] size 0x00100000 gran 0x14 bus 02 prefmem
PCI: 00:0a.0 20 <- [0x00b8200000 - 0x00b82fffff] size 0x00100000 gran 0x14 bus 02 mem
PCI: 00:0a.0 assign_resources, bus 2 link: 0
PCI: 02:00.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
PCI: 02:00.0 18 <- [0x00b0004000 - 0x00b0004fff] size 0x00001000 gran 0x0c prefmem64
PCI: 02:00.0 20 <- [0x00b0000000 - 0x00b0003fff] size 0x00004000 gran 0x0e prefmem64
PCI: 02:00.0 30 <- [0x00b8200000 - 0x00b820ffff] size 0x00010000 gran 0x10 romem
PCI: 00:0a.0 assign_resources, bus 2 link: 0
PCI: 00:11.0 10 <- [0x0000004020 - 0x0000004027] size 0x00000008 gran 0x03 io
PCI: 00:11.0 14 <- [0x0000004040 - 0x0000004043] size 0x00000004 gran 0x02 io
PCI: 00:11.0 18 <- [0x0000004028 - 0x000000402f] size 0x00000008 gran 0x03 io
PCI: 00:11.0 1c <- [0x0000004044 - 0x0000004047] size 0x00000004 gran 0x02 io
PCI: 00:11.0 20 <- [0x0000004000 - 0x000000400f] size 0x00000010 gran 0x04 io
PCI: 00:11.0 24 <- [0x00b8409000 - 0x00b84093ff] size 0x00000400 gran 0x0a mem
PCI: 00:12.0 10 <- [0x00b8404000 - 0x00b8404fff] size 0x00001000 gran 0x0c mem
PCI: 00:2.1 10 <- [0x00b8405000 - 0x00b8405fff] size 0x00001000 gran 0x0c mem
PCI: 00:12.2 10 <- [0x00b840a000 - 0x00b840a0ff] size 0x00000100 gran 0x08 mem
PCI: 00:13.0 10 <- [0x00b8406000 - 0x00b8406fff] size 0x00001000 gran 0x0c mem
PCI: 00:13.1 10 <- [0x00b8407000 - 0x00b8407fff] size 0x00001000 gran 0x0c mem
PCI: 00:13.2 10 <- [0x00b840b000 - 0x00b840b0ff] size 0x00000100 gran 0x08 mem
PCI: 00:14.0 assign_resources, bus 1 link: 0
PCI: 00:14.0 assign_resources, bus 1 link: 0
PCI: 00:14.1 10 <- [0x0000004030 - 0x0000004037] size 0x00000008 gran 0x03 io
PCI: 00:14.1 14 <- [0x0000004048 - 0x000000404b] size 0x00000004 gran 0x02 io
PCI: 00:14.1 18 <- [0x0000004038 - 0x000000403f] size 0x00000008 gran 0x03 io
PCI: 00:14.1 1c <- [0x000000404c - 0x000000404f] size 0x00000004 gran 0x02 io
PCI: 00:14.1 20 <- [0x0000004010 - 0x000000401f] size 0x00000010 gran 0x04 io
PCI: 00:14.2 10 <- [0x00b8400000 - 0x00b8403fff] size 0x00004000 gran 0x0e mem64
PCI: 00:14.3 a0 <- [0x00b840c000 - 0x00b840c000] size 0x00000001 gran 0x00 mem
PCI: 00:14.3 assign_resourcs, bus 0 link: 0
PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
PNP: 002e.6 70 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
PCI: 00:14.3 assign_resources, bus 0 link: 0
PCI: 00:14.4 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 03 io
PCI: 00:14.4 24 <- [0x00b00fffff - 0x00b00ffffe] size 0x00000000 gran 0x14 bus 03 prefmem
PCI: 00:14.4 20 <- [0x00b8300000 - 0x00b83fffff] size 0x00100000 gran 0x14 bus 03 mem
PCI: 00:14.4 assign_resources, bus 3 link: 0
PCI: 03:05.0 10 <- [0x00b8380000 - 0x00b838ffff] size 0x00010000 gran 0x10 mem
PCI: 03:06.0 10 <- [0x0000003010 - 0x0000003017] size 0x00000008 gran 0x03 io
PCI: 03:06.0 14 <- [0x0000003020 - 0x0000003023] size 0x00000004 gran 0x02 io
PCI: 03:06.0 18 <- [0x0000003018  0x000000301f] size 0x00000008 gran 0x03 io
PCI: 03:06.0 1c <- [0x0000003024 - 0x0000003027] size 0x00000004 gran 0x02 io
PCI: 03:06.0 20 <- [0x0000003000 - 0x000000300f] size 0x00000010 gran 0x04 io
PCI: 03:06.0 24 <- [0x00b8390000 - 0x00b83900ff] size 0x00000100 gran 0x08 mem
PCI: 03:06.0 30 <- [0x00b8300000 - 0x00b837ffff] size 0x00080000 gran 0x13 romem
PCI: 00:14.4 assign_resources, bus 3 link: 0
PCI: 00:14.5 10 <- [0x00b8408000 - 0x00b8408fff] size 0x00001000 gran 0x0c mem
PCI: 00:18.3 94 <- [0x00b4000000 - 0x00b7ffffff] size 0x04000000 gran 0x1a mem <gart>
PCI: 00:18.3 94 <- [0x00b4000000 - 0x00b7ffffff] size 0x04000000 gran 0x1a mem <gart>
PCI: 00:18.0 assign_resources, bus 0 link: 0
PCI: 00:18.3 94 <- [0x00bc000000 - 0x00bfffffff] size 0x04000000 gran 0x1a mem <gart>
PCI: 00:18.3 94 <- [0x00bc000000 - 0x00bfffffff] size 0x04000000 gran 0x1a mem <gart>
DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device child on link0 CPU_CLUSTER: 0
  CPU_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
   APIC: 01
  DOMAIN: 0000 child on link 0 PCI: 00:18.0
  DOMAIN: 0000 resource base 1000 size 4000 align 12 gran 0 limit ffff flags 40040100 index 10000000
  DOMAIN: 0000 resource base a8000000 size 18000000 align 27 gran 0 limit bfffffff flags 40040200 index 10000100
  DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
  DOMAIN: 0000 resource base 70000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 7
  DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
  DOMAIN: 0000 resource base c0000 size 7ff40000 align 0 gran 0 limit 0 flags e0004200 index 20
   PCI: 00:18.0 child on link 0 PCI: 00:00.0
   PCI: 00:18.0 resource base 1000 size 4000 align 12 gran 12 limit 4fff flags 60080100 index 10d8
   PCI: 00:18.0 resource base a8000000 size 8100000 align 27 gran 20 limit b00fffff flags 60081200 index 10b8
   PCI: 00:18.0 resource base b4000000 size 4500000 aign 26 gran 20 limit b84fffff flags 60080200 index 10b0
   PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags e0000200 index 11b8
    PCI: 00:00.0
    PCI: 00:01.0 child on link 0 PCI: 01:05.0
    PCI: 00:01.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c
    PCI: 00:01.0 resource base a8000000 size 8000000 align 27 gran 20 limit afffffff flags 60081202 index 24
    PCI: 00:01.0 resource base b8000000 size 200000 align 20 gran 20 limit b81fffff flags 60080202 index 20
     PCI: 01:05.0
     PCI: 01:05.0 resource base a8000000 size 8000000 align 27 gran 27 limit afffffff flags 60001200 index 10
     PCI: 01:05.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 14
     PCI: 01:05.0 resource base b8100000 size 10000 align 16 gran 16 limit b810ffff flags 60000200 index 18
     PCI: 01:05.0 resource base b8000000 size 100000 align 20 gran 20 limit b80fffff flags 60000200 index 24
    PCI: 00:02.0
    PCI: 00:03.0
    PCI: 00:04.0
    PCI: 00:05.0
    PCI: 00:06.0
    PCI: 00:07.0
   PCI: 00:08.0
    PCI: 00:09.0
    PCI: 00:0a.0 child on link 0 PCI: 02:00.0
    PCI: 00:0a.0 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c
    PCI: 00:0a.0 resource base b0000000 size 100000 align 20 gran 20 limit b00fffff flags 60081202 index 24
    PCI: 00:0a.0 resource base b8200000 size 100000 align 20 gran 20 limit b82fffff flags 60080202 index 20
     PCI: 02:00.0
     PCI: 02:00.0 resource base 2000 size 100 align 8 gran 8 limit 20ff flags 60000100 index 10
     PCI: 02:00.0 resource base b0004000 size 1000 align 12 gran 12 limit b0004fff flags 60001201 index 18
     PCI: 02:00.0 resource base b0000000 size 4000 align 14 gran 14 limit b0003fff flags 60001201 index 20
     PCI: 02:00.0 resource base b8200000 size 10000 align 16 gran 16 limit b820ffff flags 60002200 index 30
    PCI: 00:11.0
    PCI: 00:11.0 resource base 4020 size 8 align 3 gran 3 limit 4027 flags 60000100 index 10
    PCI: 00:11.0 resource base 4040 size 4 align 2 gran 2 limit 4043 flags 60000100 index 14
    PCI: 00:11.0 resource base 4028 size 8 align 3 grn 3 limit 402f flags 60000100 index 18
    PCI: 00:11.0 resource base 4044 size 4 align 2 gran 2 limit 4047 flags 60000100 index 1c
    PCI: 00:11.0 resource base 4000 size 10 align 4 gran 4 limit 400f flags 60000100 index 20
    PCI: 00:11.0 resource base b8409000 size 400 align 12 gran 10 limit b84093ff flags 60000200 index 24
    PCI: 00:12.0
    PCI: 00:12.0 resource base b8404000 size 1000 align 12 gran 12 limit b8404fff flags 60000200 index 10
    PCI: 00:12.1
    PCI: 00:12.1 resource base b8405000 size 1000 align 12 gran 12 limit b8405fff flags 60000200 index 10
    PCI: 00:12.2
    PCI: 00:12.2 resource base b840a000 size 100 align 12 gran 8 limit b840a0ff flags 60000200 index 10
    PCI: 00:13.0
    PCI: 00:13.0 resource base b8406000 size 1000 align 12 gran 12 limit b8406fff flags 60000200 index 10
    PCI: 00:13.1
    PCI: 00:13.1 resource base b8407000 size 1000 align 12 gran 12 limit b8407fff flags 60000200 index 10
    PCI: 00:13.2
    PCI: 00:13.2 resource base b840b000 size 100 align 12 gran 8 limit b840b0ff flags 60000200 index 10
    PCI: 00:14.0 child on lnk 0 I2C: 01:50
    PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 74
    PCI: 00:14.0 resource base feb00000 size 1000 align 8 gran 8 limit ffffffff flags d0000200 index 9c
    PCI: 00:14.0 resource base fed00000 size 400 align 8 gran 8 limit ffffffff flags d0000200 index b4
    PCI: 00:14.0 resource base b00 size 10 align 8 gran 8 limit ffff flags d0000100 index 90
    PCI: 00:14.0 resource base b20 size 10 align 8 gran 8 limit ffff flags d0000100 index 58
     I2C: 01:50
     I2C: 01:51
     I2C: 01:52
     I2C: 01:53
    PCI: 00:14.1
    PCI: 00:14.1 resource base 4030 size 8 align 3 gran 3 limit 4037 flags 60000100 index 10
    PCI: 00:14.1 resource base 4048 size 4 align 2 gran 2 limit 404b flags 60000100 index 14
    PCI: 00:14.1 resource base 4038 size 8 align 3 gran 3 limit 403f flags 60000100 index 18
    PCI: 00:14.1 resource base 404c size 4 align 2 gran 2 limit 404f flags 60000100 index 1c
    PCI: 00:14.1 resource base 4010 size 10 align 4 gran 4 limit 401f flags 60000100 index 20
   PCI: 00:14.2
    PCI: 00:14.2 resource base b8400000 size 4000 align 14 gran 14 limit b8403fff flags 60000201 index 10
    PCI: 00:14.3 child on link 0 PNP: 002e.0
    PCI: 00:14.3 resource base b840c000 size 1 align 12 gran 0 limit b840c000 flags 60000200 index a0
    PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
    PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
    PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
     PNP: 002e.0
     PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
     PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
     PNP: 002e.1
     PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
     PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
     PNP: 002e.2
     PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limt fff flags c0000100 index 60
     PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.3
     PNP: 002e.3 resource base 378 size 4 align 2 gran 2 limit fff flags c0000100 index 60
     PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
     PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
     PNP: 002e.4
     PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
     PNP: 002e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
     PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.5
     PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit fff flags e0000100 index 60
     PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit fff flags e0000100 index 62
     PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
     PNP: 002e.6
     PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 70
     PNP: 02e.7
     PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit fff flags 100 index 60
     PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
     PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 64
     PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.8
     PNP: 002e.8 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
     PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
     PNP: 002e.9
     PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit fff flags 100 index 60
     PNP: 002e.a
     PNP: 002e.a resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
     PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PCI: 00:14.4 child on link 0 PCI: 03:05.0
    PCI: 00:14.4 resource base 3000 size 1000 align 12 gran 12 limit 3fff flags 60080102 index 1c
    PCI: 00:14.4 resource base b00fffff size 0 align 20 gran 20 limit b00fffff flags 60081202 index 24
    PCI:00:14.4 resource base b8300000 size 100000 align 20 gran 20 limit b83fffff flags 60080202 index 20
     PCI: 03:05.0
     PCI: 03:05.0 resource base b8380000 size 10000 align 16 gran 16 limit b838ffff flags 60000200 index 10
     PCI: 03:06.0
     PCI: 03:06.0 resource base 3010 size 8 align 3 gran 3 limit 3017 flags 60000100 index 10
     PCI: 03:06.0 resource base 3020 size 4 align 2 gran 2 limit 3023 flags 60000100 index 14
     PCI: 03:06.0 resource base 3018 size 8 align 3 gran 3 limit 301f flags 60000100 index 18
     PCI: 03:06.0 resource base 3024 size 4 align 2 gran 2 limit 3027 flags 60000100 index 1c
     PCI: 03:06.0 resource base 3000 size 10 align 4 gran 4 limit 300f flags 60000100 index 20
     PCI: 03:06.0 resource base b8390000 size 100 align 12 gran 8 limit b83900ff flags 60000200 index 24
     PCI: 03:06.0 resource base b8300000 size 80000 align 19 gran 19 limit b837ffff flags 60002200 index 30
    PCI: 00:14.5
    PCI: 00:14.5 resource base b8408000 size 1000 align 12 gran 12 limit b8408fff flags 60000200 index 10
   PCI: 00:18.0
    PCI: 00:18.1
    PCI: 00:18.2
    PCI: 00:18.3
    PCI: 00:18.3 resource base b4000000 size 4000000 align 26 gran 26 limit b7ffffff flags 60000200 index 94
    PCI: 00:18.4
   PCI: 00:18.1
   PCI: 00:18.2
   PCI: 00:18.3
   PCI: 00:18.3 resource base bc000000 size 4000000 align 26 gran 26 limit bfffffff flags 60000200 index 94
   PCI: 00:18.4
Done allocating resources.
BS: BS_DEV_RESOURCES times (us): entry 0 run 3238015 exit 0
Timestamp - device enable: 21349897952
Enabling resources...
PCI: 00:18.0 cmd <- 00
PCI: 00:18.1 subsystem <- 1043/83a2
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 subsystem <- 1043/83a2
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 cmd <- 00
PCI: 00:18.4 cmd <- 00
PCI: 00:00.0 subsystem <- 104383a2
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 000b
PCI: 00:01.0 cmd <- 07
PCI: 00:0a.0 bridge ctrl <- 0003
PCI: 00:0a.0 cmd <- 07
PCI: 00:11.0 subsystem <- 1043/83a2
PCI: 00:11.0 cmd <- 03
PCI: 00:12.0 subsystem <- 1043/83a2
PCI: 00:12.0 cmd <- 02
PCI: 00:12.1 subsystem <- 1043/83a2
PCI: 00:12.1 cmd <- 02
PCI: 00:12.2 subsystem <- 1043/83a2
PCI: 00:12.2 cmd <- 02
PCI: 00:13.0 subsystem <- 1043/83a2
PCI: 00:13.0 cmd <- 02
PCI: 00:13.1 subsystem <- 1043/83a2
PCI: 00:13.1 cmd <- 02
PCI: 00:13.2 subsystem <- 1043/83a2
PCI: 00:13.2 cmd <- 02
PCI: 00:14.0 subsystem <- 1043/83a2
PCI: 00:14.0 cmd <- 403
PCI: 00:14.1 subsystem <- 1043/83a2
PCI: 00:14.1 cmd <- 01
PCI: 00:14.2subsystem <- 1043/83a2
PCI: 00:14.2 cmd <- 02
PCI: 00:14.3 subsystem <- 1043/83a2
PCI: 00:14.3 cmd <- 0f
sb700 lpc decode:PNP: 002e.1, base=0x000003f8, end=0x000003ff
sb700 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060
sb700 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064
PCI: 00:14.4 bridge ctrl <- 0003
PCI: 00:14.4 cmd <- 07
PCI: 00:14.5 subsystem <- 1043/83a2
PCI: 00:14.5 cmd <- 02
PCI: 00:18.0 cmd <- 00
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 cmd <- 00
PCI: 00:18.4 cmd <- 00
PCI: 01:05.0 subsystem <- 1043/83a2
PCI: 01:05.0 cmd <- 03
PCI: 02:00.0 cmd <- 03
PCI: 03:05.0 cmd <- 02
PCI: 03:06.0 cmd <- 03
done.
BS: BS_DEV_ENABLE times (us): enry 0 run 146096 exit 0
Timestamp - device initialization: 21803061380
Initializing devices...
Root Device init ...
Root Device init finished in 1922 usecs
CPU_CLUSTER: 0 init ...
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
No CMOS option 'probe_filter'.
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
No CMOS option 'l3_cache_partitioning'.
start_eip=0x00001000, code_size=0x00000031
Initializing CPU #0
CPU: vendor AMD device 100f62
CPU: family 10, model 06, stepping 02
nodeid = 00, coreid = 00
Enabling cache
CPU ID 0x80000001: 100f62
CPU is Fam 0Fh rv.F or later. We can use TOM2WB for any memory above 4GB
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x0000000070000000 size 0x6ff40000 type 6
0x0000000070000000 - 0x00000000a8000000 size 0x38000000 type 0
0x00000000a8000000 - 0x00000000b0000000 size 0x08000000 type 1
0x00000000b0000000 - 0x0000000100000000 size 0x50000000 type 0
MTRR addr 0x0-0x10 set to 6 type @ 0
MTRR addr 0x10-0x20 set to 6 type @ 1
MTRR addr 0x20-0x30 set to 6 type @ 2
MTRR addr 0x30-0x40 set to 6 type @ 3
MTRR addr 0x40-0x50 set to 6 type @ 4
MTRR addr 0x50-0x60 set to 6 type @ 5
MTRR adr 0x60-0x70 set to 6 type @ 6
MTRR addr 0x70-0x80 set to 6 type @ 7
MTRR addr 0x80-0x84 set to 6 type @ 8
MTRR addr 0x84-0x88 set to 6 type @ 9
MTRR addr 0x88-0x8c set to 6 type @ 10
MTRR addr 0x8c-0x90 set to 6 type @ 11
MTRR addr 0x90-0x94 set to 6 type @ 12
MTRR addr 0x94-0x98 set to 6 type @ 13
MTRR addr 0x98-0x9c set to 6 type @ 14
MTRR addr 0x9c-0xa0 set to 6 type @ 15
MTRR addr 0xa0-0xa4 set to 0 type @ 16
MTRR addr 0xa4-0xa8 set to 0 type @ 17
MTRR addr 0xa8-0xac set to 0 type @ 18
MTRR addr 0xac-0xb0 set to 0 type @ 19
MTRR addr 0xb0-0xb4 set to 0 type @ 20
MTRR addr 0xb4-0xb8 set to 0 type @ 21
MTRR addr 0xb8-0xbc set to 0 type @ 22
MTRR addr 0xbc-0xc0 set to 0 type @ 23
MTRR addr 0xc0-0xc set to 6 type @ 24
MTRR addr 0xc1-0xc2 set to 6 type @ 25
MTRR addr 0xc2-0xc3 set to 6 type @ 26
MTRR addr 0xc3-0xc4 set to 6 type @ 27
MTRR addr 0xc4-0xc5 set to 6 type @ 28
MTRR addr 0xc5-0xc6 set to 6 type @ 29
MTRR addr 0xc6-0xc7 set to 6 type @ 30
MTRR addr 0xc7-0xc8 set to 6 type @ 31
MTRR addr 0xc8-0xc9 set to 6 type @ 32
MTRR addr 0xc9-0xca set to 6 type @ 33
MTRR addr 0xca-0xcb set to 6 type @ 34
MTRR addr 0xcb-0xcc set to 6 type @ 35
MTRR addr 0xcc-0xcd set to 6 type @ 36
MTRR addr 0xcd-0xce set to 6 type @ 37
MTRR addr 0xce-0xcf set to 6 type @ 38
MTRR addr 0xcf-0xd0 set to 6 type @ 39
MTRR addr 0xd0-0xd1 set to 6 type @ 40
MTRR addr 0xd1-0xd2 set to 6 type @ 41
MTRR addr 0xd20xd3 set to 6 type @ 42
MTRR addr 0xd3-0xd4 set to 6 type @ 43
MTRR addr 0xd4-0xd5 set to 6 type @ 44
MTRR addr 0xd5-0xd6 set to 6 type @ 45
MTRR addr 0xd6-0xd7 set to 6 type @ 46
MTRR addr 0xd7-0xd8 set to 6 type @ 47
MTRR addr 0xd8-0xd9 set to 6 type @ 48
MTRR addr 0xd9-0xda set to 6 type @ 49
MTRR addr 0xda-0xdb set to 6 type @ 50
MTRR addr 0xdb-0xdc set to 6 type @ 51
MTRR addr 0xdc-0xdd set to 6 type @ 52
MTRR addr 0xdd-0xde set to 6 type @ 53
MTRR addr 0xde-0xdf set to 6 type @ 54
MTRR addr 0xdf-0xe0 set to 6 type @ 55
MTRR addr 0xe0-0xe1 set to 6 type @ 56
MTRR addr 0xe1-0xe2 set to 6 type @ 57
MTRR addr 0xe2-0xe3 set to 6 type @ 58
MTRR addr 0xe3-0xe4 set to 6 type @ 59
MTR addr 0xe4-0xe5 set to 6 type @ 60
MTRR addr 0xe5-0xe6 set to 6 type @ 61
MTRR addr 0xe6-0xe7 set to 6 type @ 62
MTRR addr 0xe7-0xe8 set to 6 type @ 63
MTRR addr 0xe8-0xe9 set to 6 type @ 64
MTRR addr 0xe9-0xea set to 6 type @ 65
MTRR addr 0xea-0xeb set to 6 type @ 66
MTRR addr 0xeb-0xec set to 6 type @ 67
MTRR addr 0xec-0xed set to 6 type @ 68
MTRR addr 0xed-0xee set to 6 type @ 69
MTRR addr 0xee-0xef set to 6 type @ 70
MTRR addr 0xef-0xf0 set to 6 type @ 71
MTRR addr 0xf0-0xf1 set to 6 type @ 72
MTRR addr 0xf1-0xf2 set to 6 type @ 73
MTRR addr 0xf2-0xf3 set to 6 type @ 74
MTRR addr 0xf3-0xf4 set to 6 type @ 75
MTRR addr 0xf4-0xf5 set to 6 type @ 76
MTRR addr 0xf5-0xf6 set to 6 type @ 77
MTRR addr 0xf6-0xf7 set to 6 type@ 78
MTRR addr 0xf7-0xf8 set to 6 type @ 79
MTRR addr 0xf8-0xf9 set to 6 type @ 80
MTRR addr 0xf9-0xfa set to 6 type @ 81
MTRR addr 0xfa-0xfb set to 6 type @ 82
MTRR addr 0xfb-0xfc set to 6 type @ 83
MTRR addr 0xfc-0xfd set to 6 type @ 84
MTRR addr 0xfd-0xfe set to 6 type @ 85
MTRR addr 0xfe-0xff set to 6 type @ 86
MTRR addr 0xff-0x100 set to 6 type @ 87
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
MTRR: Fixed SR 0x26d 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e
MTRR: default type WB/UC MTRR counts: 6/3.
MTRR: UC selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6
MTRR: 1 base 0x0000000070000000 mask 0x0000fffff0000000 type 0
MTRR: 2 base 0x00000000a8000000 mask 0x0000fffff8000000 type 1

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local APIC... apic_id: 0x00 done.
CPU model: AMD Athlon(tm) II X2 250 Processor
siblings = 01, Disabling SMM ASeg memory
CPU #0 initialized
CPU1: stack_base 00e2c000, stack_end 00e2cff8
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waitng for send to finish...
+#startup loops: 1.
Sending STARTUP #1 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #1
Waiting for 1 CPUS to stop
CPU: vendor AMD device 100f62
CPU: family 10, model 06, stepping 02
nodeid = 00, coreid = 01
Enabling cache
CPU ID 0x80000001: 100f62
CPU is Fam 0Fh rev.F or later. e can use TOM2WB for any memory above 4GB
MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e
MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

Setting up local APIC... apic_id: 0x01 done.
CPU model: AMD Athlon(tm) II X2 250 Processor
siblings = 01, Disabling SMM ASeg memory
CPU #1 initalized
All AP CPUs stopped (7859 loops)
CPU0: stack: 00e2d000 - 00e2e000, lowest used address 00e2d9ac, stack used: 1620 bytes
CPU1: stack: 00e2c000 - 00e2d000, lowest used address 00e2cccc, stack used: 820 bytes
CPU_CLUSTER: 0 init finished in 606207 usecs
PCI: 00:18.0 init ...
PCI: 00:18.0 init finished in 2009 usecs
PCI: 00:18.1 init ...
PCI: 00:18.1 init finished in 2011 usecs
PCI: 00:18.2 init ...
PCI: 00:18.2 init finished in 2010 usecs
PCI: 00:18.3 init ...
NB: Function 3 Misc Control.. FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
No CMOS option 'maximum_p_state_limit'.
done.
PCI: 00:18.3 init finished in 1999 usecs
PCI: 00:18.4 init ...
NB: Function 4 Link Control.. done.
PCI: 00:18.4 init finished in 5251 usecs
PCI: 00:00.0 init ...
PCI: 00:00.0 init finished in 2010 usecs
PCI: 00:11.0 init ...
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
No CMOS option 'sata_ahci_mode'.
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
No CMOS option 'sata_alpm'.
rev_id=14
sata_bar0=4020
sata_bar1=4040
sata_bar2=4028
sata_bar3=4044
sata_bar4=4000
sata_bar5=b8409000
ide_bar0=4030
ide_bar1=4048
ide_bar24038
ide_bar3=404c
Maximum SATA port count supported by silicon: 4
SATA port 0 status = 0
No Primary Master SATA drive on Slot0
SATA port 1 status = 23
0x6=ff, 0x7=7f
drive no longer selected after 0 ms, retrying init
0x6=ff, 0x7=7f
drive no longer selected after 0 ms, retrying init
0x6=ff, 0x7=7f
drive no longer selected after 0 ms, retrying init
0x6=ff, 0x7=7f
drive no longer selected after 0 ms, retrying init
0x6=ff, 0x7=7f
drive no longer selected after 0 ms, retrying init
0x6=ff, 0x7=7f
drive no longer selected after 0 ms, retrying init
0x6=ff, 0x7=7f
drive no longer selected after 0 ms, retrying init
0x6=ff, 0x7=7f
drive no longer seected after 0 ms, retrying init
0x6=ff, 0x7=7f
drive no longer selected after 0 ms, retrying init
0x6=ff, 0x7=7f
drive no longer selected after 0 ms, retrying init
Primary Slave device is not ready after 10 tries
SATA port 2 status = 0
No Secondary Master SATA drive on Slot2
SATA port 3 status = 0
No Secondary Slave SATA drive on Slot3
PCI: 00:11.0 init finished in 139708 usecs
PCI: 00:12.0 init ...
PCI: 00:12.0 init finished in 2041 usecs
PCI: 00:12.1 init ...
PCI: 00:12.1 init finished in 2041 usecs
PCI: 00:12.2 init ...
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
No CMOS option 'ehci_async_datacache'.
usb2_bar0=0xb840a000
rpr 6.23, final dword=809e01c8
PCI: 00:12.2 init finished in 21449 usecs
PCI: 00:13.0 init ...
PCI: 00:13.0 init finished in 2039 usecs
PCI: 00:13.1 init ...
PCI: 00:13.1 init finished in 2041 usecs
PCI: 00:13.2 init ...
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
No CMOS option 'ehci_async_data_cache'.
usb2_bar0=0xb840b000
rpr 6.23, final dword=809e01c8
PCI: 00:13.2 init finished in 21449 usecs
PCI: 00:14.0 init ...
sm_init().
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: Dumping registers
  reg 0x0000: 0x00000000
  reg 0x0001: 0x00178021
  re 0x0002: 0x00000000
IOAPIC: 24 interrupts
IOAPIC: Enabling interrupts on FSB
IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'CBFS: Found @ offset 39840 size 48c
No CMOS option 'enable_legacy_usb'.
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
set power "off" after power fail
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
++++++++++set NMI+++++
RTC Init
sm_init() end
PCI: 00:14.0 init finished in 178350 usecs
PCI: 00:14.1 init ...
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
No CMOS option 'sata_ahci_mode'.
PCI: 00:14.1 init finished in 16126 usecs
PCI: 00:14.2 init ...
base = 0xb8400000codec_mask = 05
2(th) codec viddid: ffffffff
0(th) codec viddid: ffffffff
PCI: 00:14.2 init finished in 13434 usecs
PCI: 00:14.3 init ...
lpc_init
Skipping isa_dma_init() to avoid getting stuck.
PCI: 00:14.3 init finished in 7184 usecs
PCI: 00:14.4 init ...
PCI: 00:14.4 init finished in 2036 usecs
PCI: 00:14.5 init ...
PCI: 00:14.5 init finished in 2041 usecs
PCI: 00:18.0 init ...
PCI: 00:18.0 init finished in 2010 usecs
PCI: 00:18.1 init ...
PCI: 00:18.1 init finished in 2010 usecs
PCI: 00:18.2 init ...
PCI: 00:18.2 init finished in 2010 usecs
PCI: 00:18.3 init ...
NB: Function 3 Misc Control.. FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locatin 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
No CMOS option 'maximum_p_state_limit'.
done.
PCI: 00:18.3 init finished in 19986 usecs
PCI: 00:18.4 init ...
NB: Function 4 Link Control.. done.
PCI: 00:18.4 init finished in 5251 usecs
PCI: 01:05.0 init ...
internal_gfx_pci_dev_init device=9710, vendor=1002.
vgainfo:
  ulBootUpEngineClock:50000
  ulBootUpUMAClock:66700
  ulBootUpSidePortClock:0
  ulMinSidePortClock:0
  ulSystemConfig:0
  ulBootUpReqDisplayVector:0
  ulOtherDisplayMisc:0
  ulDDISlot1Config:0
  ulDDISlot2Config:0
  ucMemoryType:0
  ucUMAChannelNumber:1
  ucDockingPinBit:0
  ucDockingPinPolarity:0
  ulDockingPinCFGInfo:0
  ulCPUCapInfo: 2
  usNumberOfCyclesInPeriod:0
  usMaxNBVoltage:0
  usinNBVoltage:0
  usBootUpNBVoltage:0
  ulHTLinkFreq:200000
  usMinHTLinkWidth:16
  usMaxHTLinkWidth:16
  usUMASyncStartDelay:100
  usUMADataReturnTime:150
  usLinkStatusZeroTime:0
  ulHighVoltageHTLinkFreq:200000
  ulLowVoltageHTLinkFreq:180000
  usMaxUpStreamHTLinkWidth:16
  usMaxDownStreamHTLinkWidth:16
  usMinUpStreamHTLinkWidth:16
  usMinDownStreamHTLinWidth:16
PCI: 01:05.0 init finished in 76350 usecs
PCI: 02:00.0 init ...
PCI: 02:00.0 init finished in 2009 usecs
PNP: 002e.1 init ...
PNP: 002e.1 init finished in 1923 usecs
PNP: 002e.5 init ...
PNP: 002e.5 init finished in 1943 usecs
PNP: 002e.6 init ...
PNP: 002e.6 init finished in 1922 usecs
PCI: 03:05.0 init ...
PCI: 03:05.0 init finished in 2008 usecs
PCI: 03:06.0 init ...
SIL3114 set to IDE compatible mode
PCI: 03:06.0 init finished in 5148 usecs
Devices initialized
Show all devs... After init.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
DOMAIN: 0000: enabled 1
APIC: 00: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 0
PCI: 00:03.0: enabled 0
PCI: 00:04.0: enabled 0
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:09.0: enabled 0
PCI: 00:0a.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI:00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 01:05.0: enabled 1
I2C: 01:50: enabled 1
I2C: 01:51: enabled 1
I2C: 01:52: enabled 1
I2C: 01:53: enabld 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 1
PNP: 002e.2: enabled 0
PNP: 002e.3: enabled 0
PNP: 002e.4: enabled 0
PNP: 002e.5: enabled 1
PNP: 002e.6: enabled 1
PNP: 002e.7: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.a: enabled 0
APIC: 01: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1
CI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 02:00.0: enabled 1
PCI: 03:05.0: enabled 1
PCI: 03:06.0: enabled 1
BS: BS_DEV_INIT times (us): entry 0 run 1430789 exit 0
Finalize devices...
Devices finalized
Timestamp - device setup done: 26120637902
BS: BS_POST_DEVICE times (us): entry 0 run 7330 exit 0
Timestamp - cbmem post: 26146741596
BS: BS_OS_RESUME_CHECK times (us): entry 0 run 3223 exit 0
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
Timestamp - write tables: 26205701748
Copying Interrupt Routing Table to 0x000f0000... done.
Copying Interrupt Routing Table to 0x6ffcf000... done.
PIRQ table: 336 bytes.
Wrote th mp table end at: 000f0410 - 000f0514
Wrote the mp table end at: 6ffce010 - 6ffce114
MP table: 276 bytes.
CBFS @ 200 size ffe00
CBFS: 'Master Header Locator' located CBFS at [200:100000)
CBFS: Locating 'fallback/dsdt.aml'
CBFS: Found @ offset 39d40 size 2892
CBFS @ 200 size ffe00
CBFS: 'Master Header Locator' located CBFS at [200:100000)
CBFS: Locating 'fallback/slic'
CBFS: 'fallback/slic' not found.
ACPI: Writing ACPI tables at 6ffaa000.
ACPI:    * FACS
ACPI:    * DSDT
ACPI:    * FADT
pm_base: 0x0800
ACPI: added table 1/32, length now 40
ACPI:     * SSDT
FMAP: area COREBOOT found @ 200 (1048064 bytes)
CBFS: Loating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
No CMOS option 'cpu_c_states'.
processor_brand=AMD Athlon(tm) II X2 250 Processor
Pstates algorithm ...
Pstate_freq[0] = 3000MHz	Pstate_power[0] = 30937mw
Pstate_latency[0] = 5us
Pstate_freq[1] = 2300MHz	Pstate_power[1] = 26010mw
Pstate_latency[1] = 5us
Pstate_freq[2] = 1800MHz	Pstate_power[2] = 22207mw
Pstate_latency[2] = 5us
PSS: 3000MHz power 30937 control 0x0 status 0x0
PSS: 2300MHz power 26010 control 0x1 status 0x1
PSS: 1800MHz power 22207 control 0x2 status 0x2
PSS: 3000MHz power 30937 control 0x0 status 0x0
PSS: 2300MHz power 26010 control 0x1 status 0x1
PSS: 1800MHz power 22207 control 0x2 status 0x2
ACP: added table 2/32, length now 44
ACPI:    * MCFG
ACPI:    * MADT
ACPI: added table 3/32, length now 48
current = 6ffad4f0
ACPI:    * SRAT at 6ffad4f0
SRAT: lapic cpu_index=00, node_id=00, apic_id=00
SRAT: lapic cpu_index=01, node_id=00, apic_id=01
set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=001ffd00
ACPI: added table 4/32, length now 52
ACPI:   * SLIT at 6ffad590
ACPI: added table 5/32, length now 56
ACPI:    * HPET
ACPI: added table 6/32, length now 60
ACPI:    * SRAT at 6ffad600
SRAT: lapic cpu_index=00, node_id=00, apic_id=00
SRAT: lapic cpu_index=01, nod_id=00, apic_id=01
set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=001ffd00
ACPI: added table 7/32, length now 64
ACPI:   * SLIT at 6ffad6a0
ACPI: added table 8/32, length now 68
ACPI: done.
ACPI tables: 14032 bytes.
smbios_write_tables: 6ffa9000
DOMAIN: 0000 (AMD Family 10h/15h Root Complex)
SMBIOS tables: 454 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 8fe1
Writing coreboot table at 0x6ffd0000
CBFS @ 200 size ffe00
CBFS: 'Master Header Locator' located CBFS at [200:100000)
CBFS: Locating 'cmos_layout.bin'
CBFS: Found @ offset 39840 size 48c
 0. 0000000000000000-000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000c0000-0000000000dfffff: RAM
 3. 0000000000e00000-0000000000ef3fff: RAMSTAGE
 4. 0000000000ef4000-000000006ffa8fff: RAM
 5. 000000006ffa9000-000000006fffffff: CONFIGURATION TABLES
 6. 0000000070000000-000000007fffffff: RESERVED
 7. 00000000c0000000-00000000cfffffff: RESERVED
 8. 00000000feb00000-00000000feb00fff: RESERVED
 9. 00000000fec00000-00000000fec00fff: RESERVED
10. 00000000fed00000-00000000fed00fff: RESERVED
CBFS @ 200 size ffe00
CBFS: 'Master Header Locator' located CBFS at [200:100000)
Wrote coreboot table at: 6ffd0000, 0x790 bytes, checksum 2541
coreboot table: 1960 bytes.
IMD ROOT    0. 6ffff00 00001000
IMD SMALL   1. 6fffe000 00001000
CAR GLOBALS 2. 6fff3000 0000a7c0
CONSOLE     3. 6ffe3000 00010000
TIME STAMP  4. 6ffe2000 00000910
AMDMEM INFO 5. 6ffd8000 000093fc
COREBOOT    6. 6ffd0000 00008000
IRQ TABLE   7. 6ffcf000 00001000
SMP TABLE   8. 6ffce000 00001000
ACPI        9. 6ffaa000 00024000
SMBIOS     10. 6ffa9000 00000800
IMD small region:
  IMD ROOT    0. 6fffec00 00000400
  ROMSTAGE    1. 6fffebe0 00000004
  GDT         2. 6fffe9e0 00000200
  COREBOOTFWD 3. 6fffe9a0 00000028
Timestamp - finalize chips: 27331769919
BS: BS_WRITE_TABLES times (us): entry 11211 run 378929 exit 0
Timestamp - load payload: 27358919006
CBFS @ 200 size ffe00
CBFS: 'Master Header Locator' locatedCBFS at [200:100000)
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset 3c640 size 10a0e
Checking segment from ROM address 0xfff3c878
Checking segment from ROM address 0xfff3c894
Loading segment from ROM address 0xfff3c878
  code (compression=1)
  New segment dstaddr 0x000e06e0 memsize 0x1f920 srcaddr 0xfff3c8b0 filesize 0x109d6
Loading Segment: addr: 0x000e06e0 memsz: 0x000000000001f920 filesz: 0x00000000000109d6
using LZMA
Timestamp - starting LZMA decompress (ignore for x86): 27501875177
Timestamp - finished LZMA decompress (ignore for x86): 27635319734
[ 0x000e06e0, 00100000, 0x00100000) <- fff3c8b0
Loading segment from ROM address 0xfff3c894
  Entry Point 0x000fd258
Loaded segments
BS: BS_PAYLOAD_LOAD times (us): entry 0 run 110030 exit 0
Jumping to boot code at 000fd258(6ffd0000)
Timestamp - selfboot jump: 27715898606
CPU0: stack: 00e2d000 - 00e2e000, lowest used address 00e2d9ac, stack used: 1620 bytes
SeaBIOS (version rel-1.12.0-4-g29ba89)
BUILD: gcc: (coreboot toolchain v1.53 August 16th, 2018) 8.1.0 binutils: (GNU Binutils) 2.30
SeaBIOS (version rel-1.12.0-4-g29ba89e)
BUILD: gcc: (coreboot toolchain v1.53 August 16th, 2018) 8.1.0 binutils: (GNU Binutils) 2.30
Found coreboot cbmem console @ 6ffe3000
Found mainboard ASUS M4A785T-M
Relocating init from 0x000e1d40 to 0x6ff5c560 (size 51712)
Found CBFS header at 0xfff00238
multiboot: eax=e257a0, ebx=e25754
Found 25 PCI devices (max PCI bus is 03)
Copying SMBIOS entry point from 0x6ffa9000 to 0x000f6280
Copying ACPI RSDP from 0x6ffaa000 to 0x000f6250
Copying MPTABLE from 0x6ffce000/6ffce010 to 0x000f6130
Copying PIR from 0x6ffcf000 to 0x000f5fe0
Using pmtimer, ioport 0x820
Scan fo VGA option rom
Turning on vga text mode console
SeaBIOS (version rel-1.12.0-4-g29ba89e)
EHCI init on dev 00:12.2 (regs=0xb840a020)
EHCI init on dev 00:13.2 (regs=0xb840b020)
OHCI init on dev 00:12.0 (regs=0xb8404000)
OHCI init on dev 00:12.1 (regs=0xb8405000)
OHCI init on dev 00:13.0 (regs=0xb8406000)
OHCI init on dev 00:13.1 (regs=0xb8407000)
OHCI init on dev 00:14.5 (regs=0xb8408000)
ATA controller 1 at 4020/4040/0 (irq 0 dev 88)
ATA controller 2 at 4028/4044/0 (irq 0 dev 88)
ATA controller 3 at 1f0/3f4/0 (irq 14 dev a1)
ATA controller 4 at 170/374/0 (irq 15 dev a1)
ATA controller 5 at 3010/3020/0 (irq 0 dev 330)
ata1-0: KINGSTON SV300S37A60G ATA- Hard-Disk (57241 MiBytes)
Searching bootorder for: /pci@i0cf8/*@11/drive@1/disk@0
Got ps2 nak (status=51)
ATA controller 6 at 3018/3024/0 (irq 0 dev 330)
Found 0 lpt ports
Found 4 serial ports
Searching bootorder for: /rom@img/memtest
DVD/CD [ata3-0: _NEC DVD_RW ND-4570A ATAPI-0 DVD/CD]
Searching bootorder for: /pci@i0cf8/*@14,1/drive@1/disk@0
All threads complete.
Scan for option roms

Press ESC for boot menu.
Searching bootorder for: HALT
drive 0x000f5f10: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=117231408
Space available for UMB: c0000-ed000, f5aa0-f5e90
Returned 262144 bytes of ZoneHigh
e820 map has 9 items:
  0: 0000000000000000 - 000000000009fc00 = 1 RAM
  1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
  3: 0000000000100000 - 000000006ffa9000 = 1 RAM
  4: 000000006ffa9000 - 0000000080000000 = 2 RESERVED
  5: 00000000c0000000 - 00000000d0000000 = 2 RESERVED
  6: 00000000feb00000 - 00000000feb01000 = 2 RESERVED
  7: 00000000fec00000 - 00000000fec01000 = 2 RESERVED
  8: 00000000fed00000 - 00000000fed01000 = 2 RESERVED  Booting `Parabola GNU/Linux-libre'

Loading linux-libre kernel ...
Loading initial ramdisk ...
[    0.003763] do_IRQ: 1.55 No irq handler for vector
starting version 239