Nick: milly E-mail: none Board: hp 8200 mt Contents: flashrom v1.3.0 on Linux 6.1.0-17-amd64 (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). flashrom was built with GCC 12.2.0, little endian Command line (17 args): flashrom -p internal -c MX25L6406E/MX25L6408E -w seabios_withgrub_hp8200sff_4mb_libgfxinit_corebootfb_usqwerty.rom -l layout3 -i fd -i gbe -i bios -i me -VVV Added layout entry 00000000 - 00000fff named fd Added layout entry 00017000 - 003fffff named bios Added layout entry 00003000 - 00016fff named me Added layout entry 00001000 - 00002fff named gbe Looking for region "me"... found. Looking for region "bios"... found. Looking for region "gbe"... found. Looking for region "fd"... found. Using regions: "me", "bios", "gbe", "fd". Initializing internal programmer /sys/class/mtd/mtd0 does not exist No coreboot table found. Using Internal DMI decoder. page_size=1000 pre-rounding: start=0x00000000000f0000, len=0x10000, end=0x0000000000100000 post-rounding: start=0x00000000000f0000, len=0x10000, end=0x0000000000100000 page_size=1000 pre-rounding: start=0x00000000000e87d9, len=0xbc5, end=0x00000000000e939e post-rounding: start=0x00000000000e8000, len=0x2000, end=0x00000000000ea000 DMI string chassis-type: "Mini Tower" page_size=1000 pre-rounding: start=0x00007fd104d1a7d9, len=0xbc5, end=0x00007fd104d1b39e post-rounding: start=0x00007fd104d1a000, len=0x2000, end=0x00007fd104d1c000 page_size=1000 pre-rounding: start=0x00007fd104d1c000, len=0x10000, end=0x00007fd104d2c000 post-rounding: start=0x00007fd104d1c000, len=0x10000, end=0x00007fd104d2c000 DMI string system-manufacturer: "Hewlett-Packard" DMI string system-product-name: "HP Compaq 8200 Elite MT PC" DMI string system-version: "Not Specified" DMI string baseboard-manufacturer: "Hewlett-Packard" DMI string baseboard-product-name: "1495" DMI string baseboard-version: "Not Specified" W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 1c. Found chipset "Intel Q67" with PCI ID 8086:1c4e. Enabling flash write... Root Complex Register Block address = 0xfed1c000 page_size=1000 pre-rounding: start=0x00000000fed1c000, len=0x4000, end=0x00000000fed20000 post-rounding: start=0x00000000fed1c000, len=0x4000, end=0x00000000fed20000 GCS = 0xc25: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) Top Swap: not enabled 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x4 0x7fffffff/0x7fffffff FWH IDSEL: 0x5 0x7fffffff/0x7fffffff FWH IDSEL: 0x6 0x7fffffff/0x7fffffff FWH IDSEL: 0x7 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled Maximum FWH chip size: 0x100000 bytes SPI Read Configuration: prefetching disabled, caching enabled, BIOS_CNTL = 0x02: BIOS Lock Enable: enabled, BIOS Write Enable: disabled SPIBAR = 0x00007fd104d28000 + 0x3800 0x04: 0xc008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=0, FDV=1, FLOCKDN=1 SPI Configuration is locked down. The Flash Descriptor Override Strap-Pin is set. Restrictions implied by the Master Section of the flash descriptor are NOT in effect. Please note that Protected Range (PR) restrictions still apply. Reading OPCODES... done OP Type Pre-OP op[0]: 0x02, write w/ addr, none op[1]: 0x03, read w/ addr, none op[2]: 0x20, write w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x9f, read w/o addr, none op[5]: 0x01, write w/o addr, none op[6]: 0x00, read w/o addr, none op[7]: 0x00, read w/o addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x00 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x08: 0x00000000 (FADDR) 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write. 0x58: 0x07ff0017 FREG1: BIOS region (0x00017000-0x007fffff) is read-write. 0x5C: 0x00160003 FREG2: Management Engine region (0x00003000-0x00016fff) is read-write. 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write. 0x64: 0x00000fff FREG4: Platform Data region is unused. 0x74: 0x87ff07f0 0x78: 0x00000000 (PR1 is unused) 0x7C: 0x00000000 (PR2 is unused) 0x80: 0x00000000 (PR3 is unused) 0x84: 0x00000000 (PR4 is unused) 0x90: 0x84 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf94130 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=3, DBC=1, SME=0, SCF=1 0x94: 0x0006 (PREOP) 0x96: 0x043b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9c: 0x0000019f (OPMENU+4) 0xa0: 0x00000000 (BBAR) 0xc4: 0x00802005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xc8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 0xd0: 0x00000000 (FPB) Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x04040003 FLMAP1 0x12100206 FLMAP2 0x00000120 --- Details --- NR (Number of Regions): 5 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH/SoC Strap Length): 18 FISBA/FPSBA (Flash ICH/PCH/SoC Strap Base Addr): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x060 MSL/PSL (MCH/PROC Strap Length): 1 FMSBA (Flash MCH/PROC Strap Base Address): 0x200 === Component Section === FLCOMP 0x09300024 FLILL 0x00000000 --- Details --- Component 1 density: 8 MB Component 2 is not used. Read Clock Frequency: 20 MHz Read ID and Status Clock Freq.: 33 MHz Write and Erase Clock Freq.: 33 MHz Fast Read is supported. Fast Read Clock Frequency: 33 MHz No forbidden opcodes. === Region Section === FLREG0 0x00000000 FLREG1 0x07ff0017 FLREG2 0x00160003 FLREG3 0x00020001 FLREG4 0x00000fff --- Details --- Region 0 (Descr. ) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x00017000 - 0x007fffff Region 2 (ME ) 0x00003000 - 0x00016fff Region 3 (GbE ) 0x00001000 - 0x00002fff Region 4 (Platf. ) is unused. === Master Section === FLMSTR1 0x1a1b0000 FLMSTR2 0x0c0d0000 FLMSTR3 0x08080118 --- Details --- Descr. BIOS ME GbE Platf. BIOS r rw rw rw ME r rw rw GbE rw checking for opcode 0x03 checking for opcode 0x05 OK. The following protocols are supported: FWH, SPI. Probing for Macronix MX25L6406E/MX25L6408E, 8192 kB: page_size=1000 pre-rounding: start=0x00000000ff800000, len=0x800000, end=0x0000000100000000 post-rounding: start=0x00000000ff800000, len=0x800000, end=0x0000000100000000 master_map_flash_region: mapping MX25L6406E/MX25L6408E from 0x00000000ff800000 to 0x00007fd10419e000 RDID returned 0xc2 0x20 0x17. compare_id: id1 0xc2, id2 0x2017 Added layout entry 00000000 - 007fffff named complete flash Found Macronix flash chip "MX25L6406E/MX25L6408E" (8192 kB, SPI) mapped at physical address 0x00000000ff800000. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set Chip status register: Bit 6 is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set page_size=1000 pre-rounding: start=0x00007fd10419e000, len=0x800000, end=0x00007fd10499e000 post-rounding: start=0x00007fd10419e000, len=0x800000, end=0x00007fd10499e000 master_unmap_flash_region: unmapped 0x00007fd10419e000 This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). === This flash part has status UNTESTED for operations: WP The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom@flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. Thanks for your help! Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. page_size=1000 pre-rounding: start=0x00000000ff800000, len=0x800000, end=0x0000000100000000 post-rounding: start=0x00000000ff800000, len=0x800000, end=0x0000000100000000 master_map_flash_region: mapping MX25L6406E/MX25L6408E from 0x00000000ff800000 to 0x00007fd10299b000 Block protection is disabled. Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x001000-0x001fff:EW, 0x002000-0x002fff:EW Trying erase function 0... 0x003000-0x003fff:S, 0x004000-0x004fff:S, 0x005000-0x005fff:S, 0x006000-0x006fff:S, 0x007000-0x007fff:S, 0x008000-0x008fff:S, 0x009000-0x009fff:S, 0x00a000-0x00afff:S, 0x00b000-0x00bfff:S, 0x00c000-0x00cfff:S, 0x00d000-0x00dfff:S, 0x00e000-0x00efff:S, 0x00f000-0x00ffff:S, 0x010000-0x010fff:S, 0x011000-0x011fff:S, 0x012000-0x012fff:S, 0x013000-0x013fff:S, 0x014000-0x014fff:S, 0x015000-0x015fff:S, 0x016000-0x016fff:S Trying erase function 0... 0x017000-0x017fff:S, 0x018000-0x018fff:S, 0x019000-0x019fff:S, 0x01a000-0x01afff:S, 0x01b000-0x01bfff:S, 0x01c000-0x01cfff:S, 0x01d000-0x01dfff:S, 0x01e000-0x01efff:S, 0x01f000-0x01ffff:S, 0x020000-0x020fff:S, 0x021000-0x021fff:S, 0x022000-0x022fff:S, 0x023000-0x023fff:S, 0x024000-0x024fff:S, 0x025000-0x025fff:S, 0x026000-0x026fff:S, 0x027000-0x027fff:S, 0x028000-0x028fff:S, 0x029000-0x029fff:S, 0x02a000-0x02afff:S, 0x02b000-0x02bfff:S, 0x02c000-0x02cfff:S, 0x02d000-0x02dfff:S, 0x02e000-0x02efff:S, 0x02f000-0x02ffff:S, 0x030000-0x030fff:ESSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 SSFC: SCGO=0, ACS=1, SPOP=0, COP=2, DBC=0, SME=0, SCF=1 Running OPCODE 0x20 failed at address 0x030000 (payload length was 0). The data was: Reading current flash chip contents... done. Looking for another erase function. Trying erase function 1... 0x010000-0x01ffff:RS, 0x020000-0x02ffff:S, 0x030000-0x03ffff:EInvalid OPCODE 0x06, will not execute. Reading current flash chip contents... done. Looking for another erase function. Trying erase function 2... 0x010000-0x01ffff:RS, 0x020000-0x02ffff:S, 0x030000-0x03ffff:EInvalid OPCODE 0x06, will not execute. Reading current flash chip contents... done. Looking for another erase function. Trying erase function 3... 0x000000-0x7fffff:RREInvalid OPCODE 0x06, will not execute. Reading current flash chip contents... done. Looking for another erase function. Trying erase function 4... 0x000000-0x7fffff:RREInvalid OPCODE 0x06, will not execute. Reading current flash chip contents... done. Looking for another erase function. Trying erase function 5... not defined. Looking for another erase function. Trying erase function 6... not defined. Looking for another erase function. Trying erase function 7... not defined. No usable erase functions left. Reading current flash chip contents... done. page_size=1000 pre-rounding: start=0x00007fd10299b000, len=0x800000, end=0x00007fd10319b000 post-rounding: start=0x00007fd10299b000, len=0x800000, end=0x00007fd10319b000 master_unmap_flash_region: unmapped 0x00007fd10299b000 Restoring MMIO space at 0x7fd104d2b8a0 Restoring PCI config space for 00:1f:0 reg 0xdc