Nick: nick E-mail: none Board: unknown Contents: [NOTE ] coreboot-4.18-751-gfb970a43bd Sat Nov 26 08:42:21 UTC 2022 bootblock starting (log level: 6)... [INFO ] Timestamp - end of bootblock: 364547354 [INFO ] Timestamp - starting to load romstage: 381590857 [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x210000. [DEBUG] FMAP: base = 0xffc00000 size = 0x400000 #areas = 4 [DEBUG] FMAP: area COREBOOT found @ 210200 (2031104 bytes) [INFO ] CBFS: mcache @0xff7c2e00 built for 20 files, used 0x428 of 0x4000 bytes [INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0xde70 in mcache @0xff7c2e2c [INFO ] Timestamp - finished loading romstage: 455651374 [DEBUG] BS: bootblock times (exec / console): total (unknown) / 43 ms [NOTE ] coreboot-4.18-751-gfb970a43bd Sat Nov 26 08:42:21 UTC 2022 romstage starting (log level: 6)... [DEBUG] Disabling Watchdog reboot... done. [DEBUG] SMBus controller enabled [DEBUG] Setting up static northbridge registers... done. [DEBUG] Started PEG10 link training. [DEBUG] Temporarily hiding PEG10. [DEBUG] Initializing IGD... [DEBUG] Back from haswell_early_initialization() [INFO ] POST: 0x3a [DEBUG] CPU id(306c3) ucode:00000028 Intel(R) Core(TM) i5-4670 CPU @ 3.40GHz [DEBUG] AES supported, TXT supported, VT supported [DEBUG] PCH type: H81, device id: 8c5c, rev id 5 [INFO ] Timestamp - before RAM initialization: 526611448 [DEBUG] Starting UEFI PEI System Agent [DEBUG] FMAP: area RW_MRC_CACHE found @ 200000 (65536 bytes) [DEBUG] prepare_mrc_cache: at 0xffe00034, size fd4 [DEBUG] FMAP: area COREBOOT found @ 210200 (2031104 bytes) [INFO ] CBFS: Found 'mrc.bin' @0x18fdc0 size 0x2e6e4 in mcache @0xff7c31a4 System Agent: Starting up... System Agent: Initializing PCH install_ppi: overwrite GUID {ed097352-9041-445a-80b6-b29d509e8845} install_ppi: overwrite GUID {908c7f8b-5c48-47fb-8357-f5fd4e235276} System Agent: Initializing PCH (SMBUS) System Agent: Initializing PCH (USB) System Agent: Initializing PCH (SA Init) System Agent: Initializing PCH (Me UMA) System Agent: Initializing Memory System Agent: Done. Sanity checking heap. [DEBUG] MRC Version 1.6.1 Build 2 [DEBUG] memcfg DDR3 clock 1600 MHz [DEBUG] memcfg channel assignment: A: 0, B 1, C 2 [DEBUG] memcfg channel[0] config (00620020): [DEBUG] ECC inactive [DEBUG] enhanced interleave mode on [DEBUG] rank interleave on [DEBUG] DIMMA 8192 MB width x8 or x32 dual rank, selected [DEBUG] DIMMB 0 MB width x8 or x32 single rank [DEBUG] memcfg channel[1] config (00620020): [DEBUG] ECC inactive [DEBUG] enhanced interleave mode on [DEBUG] rank interleave on [DEBUG] DIMMA 8192 MB width x8 or x32 dual rank, selected [DEBUG] DIMMB 0 MB width x8 or x32 single rank [INFO ] Timestamp - after RAM initialization: 3106773086 [INFO ] POST: 0x3b [DEBUG] CBMEM: [DEBUG] IMD: root @ 0x7f7ff000 254 entries. [DEBUG] IMD: root @ 0x7f7fec00 62 entries. [DEBUG] External stage cache: [DEBUG] IMD: root @ 0x7fbff000 254 entries. [DEBUG] IMD: root @ 0x7fbfec00 62 entries. [DEBUG] FMAP: area RW_MRC_CACHE found @ 200000 (65536 bytes) [DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'. [INFO ] Manufacturer: ef [INFO ] SF: Detected ef 4016 with sector size 0x1000, total 0x400000 [DEBUG] MRC: 'RW_MRC_CACHE' does not need update. [DEBUG] Unhiding PEG10. [INFO ] POST: 0x3f [DEBUG] SMM Memory Map [DEBUG] SMRAM : 0x7f800000 0x800000 [DEBUG] Subregion 0: 0x7f800000 0x300000 [DEBUG] Subregion 1: 0x7fb00000 0x100000 [DEBUG] Subregion 2: 0x7fc00000 0x400000 [DEBUG] Normal boot [INFO ] CBFS: Found 'fallback/postcar' @0x433c0 size 0x80fc in mcache @0xff7c30e0 [DEBUG] Loading module at 0x7f7cd000 with entry 0x7f7cd031. filesize: 0x78e0 memsize: 0xdc18 [DEBUG] Processing 503 relocs. Offset value of 0x7d7cd000 [INFO ] Timestamp - end of romstage: 3242950651 [DEBUG] BS: romstage times (exec / console): total (unknown) / 98 ms [NOTE ] coreboot-4.18-751-gfb970a43bd Sat Nov 26 08:42:21 UTC 2022 postcar starting (log level: 6)... [INFO ] Timestamp - start of postcar: 3299710030 [INFO ] Timestamp - end of postcar: 3317065245 [DEBUG] Normal boot [INFO ] Timestamp - starting to load ramstage: 3334179876 [DEBUG] FMAP: area COREBOOT found @ 210200 (2031104 bytes) [INFO ] CBFS: Found 'fallback/ramstage' @0x13c80 size 0x1c855 in mcache @0x7f7dd10c [INFO ] Timestamp - starting LZMA decompress (ignore for x86): 3381702135 [INFO ] Timestamp - finished LZMA decompress (ignore for x86): 3525395774 [DEBUG] Loading module at 0x7f76f000 with entry 0x7f76f000. filesize: 0x395f8 memsize: 0x5c750 [DEBUG] Processing 4248 relocs. Offset value of 0x7b76f000 [INFO ] Timestamp - finished loading ramstage: 3551042314 [DEBUG] BS: postcar times (exec / console): total (unknown) / 55 ms [NOTE ] coreboot-4.18-751-gfb970a43bd Sat Nov 26 08:42:21 UTC 2022 ramstage starting (log level: 6)... [INFO ] POST: 0x39 [INFO ] Timestamp - start of ramstage: 3616331528 [INFO ] POST: 0x6f [DEBUG] Normal boot [INFO ] POST: 0x70 [DEBUG] BS: BS_PRE_DEVICE run times (exec / console): 0 / 2 ms [INFO ] POST: 0x71 [INFO ] Timestamp - device enumeration: 3659722906 [DEBUG] BS: BS_DEV_INIT_CHIPS run times (exec / console): 0 / 8 ms [INFO ] POST: 0x72 [INFO ] Enumerating buses... [DEBUG] Root Device scanning... [DEBUG] CPU_CLUSTER: 0 enabled [DEBUG] DOMAIN: 0000 enabled [DEBUG] DOMAIN: 0000 scanning... [DEBUG] PCI: pci_scan_bus for bus 00 [INFO ] POST: 0x24 [DEBUG] PCI: 00:00.0 [8086/0c00] enabled [DEBUG] PCI: 00:01.0 [8086/0c01] enabled [DEBUG] PCI: 00:02.0 [8086/0412] enabled [DEBUG] PCI: 00:03.0 [8086/0c0c] enabled [DEBUG] PCI: 00:14.0 [8086/8c31] enabled [DEBUG] PCI: 00:16.0 [8086/8c3a] enabled [DEBUG] PCI: 00:16.1: Disabling device [DEBUG] PCI: 00:16.2: Disabling device [DEBUG] PCI: 00:16.3: Disabling device [DEBUG] PCI: 00:19.0: Disabling device [DEBUG] PCI: 00:1a.0 [8086/8c2d] enabled [DEBUG] PCI: 00:1b.0 [8086/8c20] enabled [DEBUG] PCIe Root Port 1 ASPM is disabled [DEBUG] PCI: 00:1c.0 [8086/8c10] enabled [DEBUG] PCI: 00:1c.1 [8086/8c12] disabled [DEBUG] PCI: 00:1c.2 [8086/8c14] disabled [DEBUG] PCIe Root Port 4 ASPM is disabled [DEBUG] PCI: 00:1c.3 [8086/8c16] enabled [DEBUG] Adjusted number of PCIe root ports to 6 as per strpfusecfg2 [DEBUG] PCIe Root Port 5 ASPM is disabled [DEBUG] PCI: 00:1c.4 [8086/8c18] enabled [DEBUG] PCIe Root Port 6 ASPM is disabled [DEBUG] PCI: 00:1c.1: Disabling device [DEBUG] PCI: 00:1c.2: Disabling device [DEBUG] PCI: 00:1c.5 [8086/8c1a] enabled [DEBUG] PCI: 00:1d.0 [8086/8c26] enabled [DEBUG] PCI: 00:1f.0 [8086/8c5c] enabled [DEBUG] PCI: 00:1f.2 [8086/8c02] enabled [DEBUG] PCI: 00:1f.3 [8086/8c22] enabled [DEBUG] PCI: 00:1f.5: Disabling device [DEBUG] PCI: 00:1f.6: Disabling device [WARN ] PCI: Leftover static devices: [WARN ] PCI: 00:16.1 [WARN ] PCI: 00:16.2 [WARN ] PCI: 00:16.3 [WARN ] PCI: 00:19.0 [WARN ] PCI: 00:1f.5 [WARN ] PCI: 00:1f.6 [WARN ] PCI: Check your devicetree.cb. [DEBUG] PCI: 00:01.0 scanning... [DEBUG] PCI: pci_scan_bus for bus 01 [INFO ] POST: 0x24 [INFO ] POST: 0x25 [DEBUG] scan_bus: bus PCI: 00:01.0 finished in 4 msecs [DEBUG] PCI: 00:1c.0 scanning... [DEBUG] PCI: pci_scan_bus for bus 02 [INFO ] POST: 0x24 [INFO ] POST: 0x25 [DEBUG] scan_bus: bus PCI: 00:1c.0 finished in 4 msecs [DEBUG] PCI: 00:1c.3 scanning... [DEBUG] PCI: pci_scan_bus for bus 03 [INFO ] POST: 0x24 [DEBUG] PCI: 03:00.0 [10ec/8168] enabled [INFO ] POST: 0x25 [INFO ] Enabling Common Clock Configuration [INFO ] ASPM: Enabled L1 [INFO ] PCIe: Max_Payload_Size adjusted to 128 [INFO ] PCI: 03:00.0: Enabled LTR [DEBUG] scan_bus: bus PCI: 00:1c.3 finished in 21 msecs [DEBUG] PCI: 00:1c.4 scanning... [DEBUG] PCI: pci_scan_bus for bus 04 [INFO ] POST: 0x24 [INFO ] PCI: Static device PCI: 04:00.0 not found, disabling it. [WARN ] PCI: Leftover static devices: [WARN ] PCI: 04:00.0 [WARN ] PCI: Check your devicetree.cb. [INFO ] POST: 0x25 [DEBUG] scan_bus: bus PCI: 00:1c.4 finished in 23 msecs [DEBUG] PCI: 00:1c.5 scanning... [DEBUG] PCI: pci_scan_bus for bus 05 [INFO ] POST: 0x24 [INFO ] POST: 0x25 [DEBUG] scan_bus: bus PCI: 00:1c.5 finished in 4 msecs [DEBUG] PCI: 00:1f.0 scanning... [DEBUG] PNP: 002e.0 disabled [DEBUG] PNP: 002e.1 enabled [DEBUG] PNP: 002e.2 enabled [DEBUG] PNP: 002e.3 enabled [DEBUG] PNP: 002e.5 enabled [DEBUG] PNP: 002e.6 disabled [DEBUG] PNP: 002e.7 disabled [DEBUG] PNP: 002e.107 disabled [DEBUG] PNP: 002e.8 disabled [DEBUG] PNP: 002e.108 disabled [DEBUG] PNP: 002e.208 disabled [DEBUG] PNP: 002e.308 disabled [DEBUG] PNP: 002e.109 disabled [DEBUG] PNP: 002e.209 disabled [DEBUG] PNP: 002e.309 disabled [DEBUG] PNP: 002e.409 disabled [DEBUG] PNP: 002e.509 disabled [DEBUG] PNP: 002e.609 disabled [DEBUG] PNP: 002e.709 disabled [DEBUG] PNP: 002e.a disabled [DEBUG] PNP: 002e.b enabled [DEBUG] PNP: 002e.d disabled [DEBUG] PNP: 002e.e disabled [DEBUG] PNP: 002e.f disabled [DEBUG] PNP: 002e.14 disabled [DEBUG] PNP: 002e.16 disabled [DEBUG] PNP: 002e.17 disabled [DEBUG] scan_bus: bus PCI: 00:1f.0 finished in 0 msecs [DEBUG] PCI: 00:1f.3 scanning... [DEBUG] scan_bus: bus PCI: 00:1f.3 finished in 0 msecs [INFO ] POST: 0x25 [DEBUG] scan_bus: bus DOMAIN: 0000 finished in 91 msecs [DEBUG] scan_bus: bus Root Device finished in 91 msecs [INFO ] done [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 99 ms [INFO ] POST: 0x73 [INFO ] Timestamp - device configuration: 4026005042 [DEBUG] found VGA at PCI: 00:02.0 [DEBUG] Setting up VGA for PCI: 00:02.0 [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device [INFO ] Allocating resources... [INFO ] Reading resources... [DEBUG] mc_add_fixed_mmio_resources: Adding MCHBAR @ 48 0xfed10000-0xfed17fff. [DEBUG] mc_add_fixed_mmio_resources: Adding DMIBAR @ 68 0xfed18000-0xfed18fff. [DEBUG] mc_add_fixed_mmio_resources: Adding EPBAR @ 40 0xfed19000-0xfed19fff. [DEBUG] mc_add_fixed_mmio_resources: Adding GDXCBAR @ 5420 0xfed84000-0xfed84fff. [DEBUG] mc_add_fixed_mmio_resources: Adding EDRAMBAR @ 5408 0xfed80000-0xfed83fff. [DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. [DEBUG] MC MAP: TOM: 0x400000000 [DEBUG] MC MAP: TOUUD: 0x47de00000 [DEBUG] MC MAP: MESEG_BASE: 0x7ffff00000 [DEBUG] MC MAP: MESEG_LIMIT: 0xfffff [DEBUG] MC MAP: REMAP_BASE: 0x400000000 [DEBUG] MC MAP: REMAP_LIMIT: 0x47ddfffff [DEBUG] MC MAP: TOLUD: 0x82200000 [DEBUG] MC MAP: BGSM: 0x80000000 [DEBUG] MC MAP: BDSM: 0x80200000 [DEBUG] MC MAP: TSEGMB: 0x7f800000 [DEBUG] MC MAP: GGC: 0x209 [DEBUG] MC MAP: DPR: 0x7f800001 [INFO ] Available memory above 4GB: 14302M [INFO ] Done reading resources. [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === [DEBUG] PCI: 00:1c.3 io: size: 0 align: 12 gran: 12 limit: ffff [DEBUG] PCI: 03:00.0 10 * [0x0 - 0xff] io [DEBUG] PCI: 00:1c.3 io: size: 1000 align: 12 gran: 12 limit: ffff done [DEBUG] PCI: 00:1c.3 mem: size: 0 align: 20 gran: 20 limit: ffffffff [DEBUG] PCI: 03:00.0 18 * [0x0 - 0xfff] mem [DEBUG] PCI: 00:1c.3 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done [DEBUG] PCI: 00:1c.3 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff [DEBUG] PCI: 03:00.0 20 * [0x0 - 0x3fff] prefmem [DEBUG] PCI: 00:1c.3 prefmem: size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff [DEBUG] update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed) [DEBUG] update_constraints: PNP: 002e.1 60 base 00000378 limit 0000037f io (fixed) [DEBUG] update_constraints: PNP: 002e.2 60 base 000003f8 limit 000003ff io (fixed) [DEBUG] update_constraints: PNP: 002e.3 60 base 000002f8 limit 000002ff io (fixed) [DEBUG] update_constraints: PNP: 002e.5 60 base 00000060 limit 00000060 io (fixed) [DEBUG] update_constraints: PNP: 002e.5 62 base 00000064 limit 00000064 io (fixed) [DEBUG] update_constraints: PNP: 002e.b 60 base 00000290 limit 00000291 io (fixed) [DEBUG] update_constraints: PNP: 002e.b 62 base 00000000 limit 00000001 io (fixed) [DEBUG] update_constraints: PCI: 00:1f.3 20 base 00000400 limit 0000041f io (fixed) [INFO ] DOMAIN: 0000: Resource ranges: [INFO ] * Base: 1000, Size: f000, Tag: 100 [DEBUG] PCI: 00:1c.3 1c * [0x1000 - 0x1fff] limit: 1fff io [DEBUG] PCI: 00:02.0 20 * [0x2000 - 0x203f] limit: 203f io [DEBUG] PCI: 00:1f.2 20 * [0x2040 - 0x205f] limit: 205f io [DEBUG] PCI: 00:1f.2 10 * [0x2060 - 0x2067] limit: 2067 io [DEBUG] PCI: 00:1f.2 18 * [0x2068 - 0x206f] limit: 206f io [DEBUG] PCI: 00:1f.2 14 * [0x2070 - 0x2073] limit: 2073 io [DEBUG] PCI: 00:1f.2 1c * [0x2074 - 0x2077] limit: 2077 io [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff [DEBUG] update_constraints: PCI: 00:00.0 48 base fed10000 limit fed17fff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 68 base fed18000 limit fed18fff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 40 base fed19000 limit fed19fff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 5420 base fed84000 limit fed84fff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 5408 base fed80000 limit fed83fff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 00 base fed90000 limit fed90fff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 01 base fed91000 limit fed91fff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 02 base 00000000 limit 0009ffff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 03 base 000c0000 limit 7f7fffff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 04 base 7f800000 limit 7fffffff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 05 base 80000000 limit 821fffff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 06 base 100000000 limit 47ddfffff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 07 base 000a0000 limit 000bffff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 08 base 000c0000 limit 000fffff mem (fixed) [DEBUG] update_constraints: PCI: 00:1f.0 31fe base fec00000 limit ffffffff mem (fixed) [INFO ] DOMAIN: 0000: Resource ranges: [INFO ] * Base: 82200000, Size: 6de00000, Tag: 200 [INFO ] * Base: f4000000, Size: ac00000, Tag: 200 [INFO ] * Base: 47de00000, Size: 7b82200000, Tag: 100200 [DEBUG] PCI: 00:02.0 18 * [0x90000000 - 0x9fffffff] limit: 9fffffff prefmem [DEBUG] PCI: 00:02.0 10 * [0x82400000 - 0x827fffff] limit: 827fffff mem [DEBUG] PCI: 00:1c.3 24 * [0x82200000 - 0x822fffff] limit: 822fffff prefmem [DEBUG] PCI: 00:1c.3 20 * [0x82300000 - 0x823fffff] limit: 823fffff mem [DEBUG] PCI: 00:14.0 10 * [0x82800000 - 0x8280ffff] limit: 8280ffff mem [DEBUG] PCI: 00:03.0 10 * [0x82810000 - 0x82813fff] limit: 82813fff mem [DEBUG] PCI: 00:1b.0 10 * [0x82814000 - 0x82817fff] limit: 82817fff mem [DEBUG] PCI: 00:1f.2 24 * [0x82818000 - 0x828187ff] limit: 828187ff mem [DEBUG] PCI: 00:1a.0 10 * [0x82819000 - 0x828193ff] limit: 828193ff mem [DEBUG] PCI: 00:1d.0 10 * [0x8281a000 - 0x8281a3ff] limit: 8281a3ff mem [DEBUG] PCI: 00:1f.3 10 * [0x8281b000 - 0x8281b0ff] limit: 8281b0ff mem [DEBUG] PCI: 00:16.0 10 * [0x8281c000 - 0x8281c00f] limit: 8281c00f mem [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done [DEBUG] PCI: 00:1c.3 io: base: 1000 size: 1000 align: 12 gran: 12 limit: 1fff [INFO ] PCI: 00:1c.3: Resource ranges: [INFO ] * Base: 1000, Size: 1000, Tag: 100 [DEBUG] PCI: 03:00.0 10 * [0x1000 - 0x10ff] limit: 10ff io [DEBUG] PCI: 00:1c.3 io: base: 1000 size: 1000 align: 12 gran: 12 limit: 1fff done [DEBUG] PCI: 00:1c.3 prefmem: base: 82200000 size: 100000 align: 20 gran: 20 limit: 822fffff [INFO ] PCI: 00:1c.3: Resource ranges: [INFO ] * Base: 82200000, Size: 100000, Tag: 1200 [DEBUG] PCI: 03:00.0 20 * [0x82200000 - 0x82203fff] limit: 82203fff prefmem [DEBUG] PCI: 00:1c.3 prefmem: base: 82200000 size: 100000 align: 20 gran: 20 limit: 822fffff done [DEBUG] PCI: 00:1c.3 mem: base: 82300000 size: 100000 align: 20 gran: 20 limit: 823fffff [INFO ] PCI: 00:1c.3: Resource ranges: [INFO ] * Base: 82300000, Size: 100000, Tag: 200 [DEBUG] PCI: 03:00.0 18 * [0x82300000 - 0x82300fff] limit: 82300fff mem [DEBUG] PCI: 00:1c.3 mem: base: 82300000 size: 100000 align: 20 gran: 20 limit: 823fffff done [INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete === [DEBUG] PCI: 00:01.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 01 io [DEBUG] PCI: 00:01.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem [DEBUG] PCI: 00:01.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 01 mem [DEBUG] PCI: 00:02.0 10 <- [0x0000000082400000 - 0x00000000827fffff] size 0x00400000 gran 0x16 mem64 [DEBUG] PCI: 00:02.0 18 <- [0x0000000090000000 - 0x000000009fffffff] size 0x10000000 gran 0x1c prefmem64 [DEBUG] PCI: 00:02.0 20 <- [0x0000000000002000 - 0x000000000000203f] size 0x00000040 gran 0x06 io [DEBUG] PCI: 00:03.0 10 <- [0x0000000082810000 - 0x0000000082813fff] size 0x00004000 gran 0x0e mem64 [DEBUG] PCI: 00:14.0 10 <- [0x0000000082800000 - 0x000000008280ffff] size 0x00010000 gran 0x10 mem64 [DEBUG] PCI: 00:16.0 10 <- [0x000000008281c000 - 0x000000008281c00f] size 0x00000010 gran 0x04 mem64 [DEBUG] PCI: 00:1a.0 10 <- [0x0000000082819000 - 0x00000000828193ff] size 0x00000400 gran 0x0a mem [DEBUG] PCI: 00:1b.0 10 <- [0x0000000082814000 - 0x0000000082817fff] size 0x00004000 gran 0x0e mem64 [DEBUG] PCI: 00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 02 io [DEBUG] PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem [DEBUG] PCI: 00:1c.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 02 mem [DEBUG] PCI: 00:1c.3 1c <- [0x0000000000001000 - 0x0000000000001fff] size 0x00001000 gran 0x0c bus 03 io [DEBUG] PCI: 00:1c.3 24 <- [0x0000000082200000 - 0x00000000822fffff] size 0x00100000 gran 0x14 bus 03 prefmem [DEBUG] PCI: 00:1c.3 20 <- [0x0000000082300000 - 0x00000000823fffff] size 0x00100000 gran 0x14 bus 03 mem [DEBUG] PCI: 03:00.0 10 <- [0x0000000000001000 - 0x00000000000010ff] size 0x00000100 gran 0x08 io [DEBUG] PCI: 03:00.0 18 <- [0x0000000082300000 - 0x0000000082300fff] size 0x00001000 gran 0x0c mem64 [DEBUG] PCI: 03:00.0 20 <- [0x0000000082200000 - 0x0000000082203fff] size 0x00004000 gran 0x0e prefmem64 [DEBUG] PCI: 00:1c.4 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 04 io [DEBUG] PCI: 00:1c.4 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 04 prefmem [DEBUG] PCI: 00:1c.4 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 04 mem [DEBUG] PCI: 00:1c.5 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 05 io [DEBUG] PCI: 00:1c.5 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 05 prefmem [DEBUG] PCI: 00:1c.5 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 05 mem [DEBUG] PCI: 00:1d.0 10 <- [0x000000008281a000 - 0x000000008281a3ff] size 0x00000400 gran 0x0a mem [DEBUG] PNP: 002e.1 60 <- [0x0000000000000378 - 0x000000000000037f] size 0x00000008 gran 0x03 io [DEBUG] PNP: 002e.1 70 <- [0x0000000000000007 - 0x0000000000000007] size 0x00000001 gran 0x00 irq [DEBUG] PNP: 002e.1 74 <- [0x0000000000000004 - 0x0000000000000004] size 0x00000001 gran 0x00 drq [DEBUG] PNP: 002e.1 f0 <- [0x000000000000003c - 0x000000000000003b] size 0x00000000 gran 0x00 irq [DEBUG] PNP: 002e.2 60 <- [0x00000000000003f8 - 0x00000000000003ff] size 0x00000008 gran 0x03 io [DEBUG] PNP: 002e.2 70 <- [0x0000000000000004 - 0x0000000000000004] size 0x00000001 gran 0x00 irq [DEBUG] PNP: 002e.3 60 <- [0x00000000000002f8 - 0x00000000000002ff] size 0x00000008 gran 0x03 io [DEBUG] PNP: 002e.3 70 <- [0x0000000000000003 - 0x0000000000000003] size 0x00000001 gran 0x00 irq [DEBUG] PNP: 002e.5 60 <- [0x0000000000000060 - 0x0000000000000060] size 0x00000001 gran 0x00 io [DEBUG] PNP: 002e.5 62 <- [0x0000000000000064 - 0x0000000000000064] size 0x00000001 gran 0x00 io [DEBUG] PNP: 002e.5 70 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 irq [DEBUG] PNP: 002e.5 72 <- [0x000000000000000c - 0x000000000000000c] size 0x00000001 gran 0x00 irq [DEBUG] PNP: 002e.b 60 <- [0x0000000000000290 - 0x0000000000000291] size 0x00000002 gran 0x01 io [DEBUG] PNP: 002e.b 62 <- [0x0000000000000000 - 0x0000000000000001] size 0x00000002 gran 0x01 io [DEBUG] PNP: 002e.b 70 <- [0x0000000000000000 - 0x0000000000000000] size 0x00000001 gran 0x00 irq [DEBUG] PCI: 00:1f.2 10 <- [0x0000000000002060 - 0x0000000000002067] size 0x00000008 gran 0x03 io [DEBUG] PCI: 00:1f.2 14 <- [0x0000000000002070 - 0x0000000000002073] size 0x00000004 gran 0x02 io [DEBUG] PCI: 00:1f.2 18 <- [0x0000000000002068 - 0x000000000000206f] size 0x00000008 gran 0x03 io [DEBUG] PCI: 00:1f.2 1c <- [0x0000000000002074 - 0x0000000000002077] size 0x00000004 gran 0x02 io [DEBUG] PCI: 00:1f.2 20 <- [0x0000000000002040 - 0x000000000000205f] size 0x00000020 gran 0x05 io [DEBUG] PCI: 00:1f.2 24 <- [0x0000000082818000 - 0x00000000828187ff] size 0x00000800 gran 0x0b mem [DEBUG] PCI: 00:1f.3 10 <- [0x000000008281b000 - 0x000000008281b0ff] size 0x00000100 gran 0x08 mem64 [INFO ] Done setting resources. [INFO ] Done allocating resources. [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 2 / 113 ms [INFO ] POST: 0x74 [INFO ] Timestamp - device enable: 4417327328 [INFO ] Enabling resources... [DEBUG] PCI: 00:00.0 subsystem <- 1849/0c00 [DEBUG] PCI: 00:00.0 cmd <- 06 [DEBUG] PCI: 00:01.0 bridge ctrl <- 0013 [DEBUG] PCI: 00:01.0 subsystem <- 1849/0c01 [DEBUG] PCI: 00:01.0 cmd <- 00 [DEBUG] PCI: 00:02.0 subsystem <- 1849/0402 [DEBUG] PCI: 00:02.0 cmd <- 03 [DEBUG] PCI: 00:03.0 subsystem <- 1849/0c0c [DEBUG] PCI: 00:03.0 cmd <- 02 [DEBUG] PCI: 00:14.0 subsystem <- 1849/8c31 [DEBUG] PCI: 00:14.0 cmd <- 102 [DEBUG] PCI: 00:16.0 subsystem <- 1849/8c3a [DEBUG] PCI: 00:16.0 cmd <- 02 [DEBUG] PCI: 00:1a.0 subsystem <- 1849/8c2d [DEBUG] PCI: 00:1a.0 cmd <- 102 [DEBUG] PCI: 00:1b.0 subsystem <- 1849/7662 [DEBUG] PCI: 00:1b.0 cmd <- 102 [DEBUG] PCI: 00:1c.0 bridge ctrl <- 0013 [DEBUG] PCI: 00:1c.0 subsystem <- 1849/8c10 [DEBUG] PCI: 00:1c.0 cmd <- 00 [DEBUG] PCI: 00:1c.3 bridge ctrl <- 0013 [DEBUG] PCI: 00:1c.3 subsystem <- 1849/8c16 [DEBUG] PCI: 00:1c.3 cmd <- 07 [DEBUG] PCI: 00:1c.4 bridge ctrl <- 0013 [DEBUG] PCI: 00:1c.4 subsystem <- 1849/8c18 [DEBUG] PCI: 00:1c.4 cmd <- 00 [DEBUG] PCI: 00:1c.5 bridge ctrl <- 0013 [DEBUG] PCI: 00:1c.5 subsystem <- 1849/8c1a [DEBUG] PCI: 00:1c.5 cmd <- 00 [DEBUG] PCI: 00:1d.0 subsystem <- 1849/8c26 [DEBUG] PCI: 00:1d.0 cmd <- 102 [DEBUG] PCI: 00:1f.0 subsystem <- 1849/8c5c [DEBUG] PCI: 00:1f.0 cmd <- 107 [DEBUG] PCI: 00:1f.2 subsystem <- 1849/8c02 [DEBUG] PCI: 00:1f.2 cmd <- 103 [DEBUG] PCI: 00:1f.3 subsystem <- 1849/8c22 [DEBUG] PCI: 00:1f.3 cmd <- 103 [DEBUG] PCI: 03:00.0 cmd <- 03 [INFO ] done. [DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 0 / 13 ms [INFO ] POST: 0x75 [INFO ] Timestamp - device initialization: 4462545135 [INFO ] Initializing devices... [INFO ] POST: 0x75 [DEBUG] CPU_CLUSTER: 0 init [DEBUG] MTRR: Physical address space: [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6 [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0 [DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6 [DEBUG] 0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 0 [DEBUG] 0x0000000090000000 - 0x000000009fffffff size 0x10000000 type 1 [DEBUG] 0x00000000a0000000 - 0x00000000ffffffff size 0x60000000 type 0 [DEBUG] 0x0000000100000000 - 0x000000047ddfffff size 0x37de00000 type 6 [DEBUG] MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] CPU physical address size: 39 bits [DEBUG] MTRR: default type WB/UC MTRR counts: 4/5. [DEBUG] MTRR: WB selected as default type. [DEBUG] MTRR: 0 base 0x0000000080000000 mask 0x0000007ff0000000 type 0 [DEBUG] MTRR: 1 base 0x0000000090000000 mask 0x0000007ff0000000 type 1 [DEBUG] MTRR: 2 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0 [DEBUG] MTRR: 3 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0 [DEBUG] MTRR check [DEBUG] Fixed MTRRs : Enabled [DEBUG] Variable MTRRs: Enabled [INFO ] POST: 0x93 [DEBUG] Initializing VR config. [DEBUG] CPU has 4 cores, 4 threads enabled. [DEBUG] Setting up SMI for CPU [INFO ] Will perform SMM setup. [DEBUG] FMAP: area COREBOOT found @ 210200 (2031104 bytes) [INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0xdf80 size 0x5c00 in mcache @0x7f7dd0ac [DEBUG] microcode: sig=0x306c3 pf=0x2 revision=0x28 [INFO ] CPU: Intel(R) Core(TM) i5-4670 CPU @ 3.40GHz. [INFO ] LAPIC 0x0 in XAPIC mode. [DEBUG] CPU: APIC: 00 enabled [DEBUG] CPU: APIC: 01 enabled [DEBUG] CPU: APIC: 02 enabled [DEBUG] CPU: APIC: 03 enabled [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178 [DEBUG] Processing 16 relocs. Offset value of 0x00030000 [DEBUG] Attempting to start 3 APs [DEBUG] Waiting for 10ms after sending INIT. [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [INFO ] LAPIC 0x2 in XAPIC mode. [INFO ] LAPIC 0x4 in XAPIC mode. [INFO ] AP: slot 1 apic_id 2, MCU rev: 0x00000028 [INFO ] LAPIC 0x6 in XAPIC mode. [INFO ] AP: slot 2 apic_id 4, MCU rev: 0x00000028 [INFO ] AP: slot 3 apic_id 6, MCU rev: 0x00000028 [DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e8 memsize: 0x1e8 [DEBUG] Processing 11 relocs. Offset value of 0x00038000 [DEBUG] smm_module_setup_stub: stack_top = 0x7f801000 [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400 [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000 [DEBUG] SMM Module: stub loaded at 38000. Will call 0x7f78dd88 [DEBUG] Installing permanent SMM handler to 0x7f800000 [DEBUG] FX_SAVE [0x7faff800-0x7fb00000] [DEBUG] HANDLER [0x7fafe000-0x7fafeca0] [DEBUG] CPU 0 [DEBUG] ss0 [0x7fafdc00-0x7fafe000] [DEBUG] stub0 [0x7faf6000-0x7faf61e8] [DEBUG] CPU 1 [DEBUG] ss1 [0x7fafd800-0x7fafdc00] [DEBUG] stub1 [0x7faf5c00-0x7faf5de8] [DEBUG] CPU 2 [DEBUG] ss2 [0x7fafd400-0x7fafd800] [DEBUG] stub2 [0x7faf5800-0x7faf59e8] [DEBUG] CPU 3 [DEBUG] ss3 [0x7fafd000-0x7fafd400] [DEBUG] stub3 [0x7faf5400-0x7faf55e8] [DEBUG] stacks [0x7f800000-0x7f801000] [DEBUG] Loading module at 0x7fafe000 with entry 0x7fafe230. filesize: 0xc88 memsize: 0xca0 [DEBUG] Processing 45 relocs. Offset value of 0x7fafe000 [DEBUG] Loading module at 0x7faf6000 with entry 0x7faf6000. filesize: 0x1e8 memsize: 0x1e8 [DEBUG] Processing 11 relocs. Offset value of 0x7faf6000 [DEBUG] smm_module_setup_stub: stack_top = 0x7f801000 [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400 [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x300000 [DEBUG] SMM Module: placing smm entry code at 7faf5c00, cpu # 0x1 [DEBUG] SMM Module: placing smm entry code at 7faf5800, cpu # 0x2 [DEBUG] SMM Module: placing smm entry code at 7faf5400, cpu # 0x3 [DEBUG] SMM Module: stub loaded at 7faf6000. Will call 0x7fafe230 [DEBUG] Initializing Southbridge SMI... [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faee000, cpu = 0 [DEBUG] In relocation handler: CPU 0 [DEBUG] New SMBASE=0x7faee000 IEDBASE=0x7fc00000 [DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800 [DEBUG] Relocation complete. [INFO ] microcode: Update skipped, already up-to-date [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faed400, cpu = 3 [DEBUG] In relocation handler: CPU 3 [DEBUG] New SMBASE=0x7faed400 IEDBASE=0x7fc00000 [DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800 [DEBUG] Relocation complete. [INFO ] microcode: Update skipped, already up-to-date [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faedc00, cpu = 1 [DEBUG] In relocation handler: CPU 1 [DEBUG] New SMBASE=0x7faedc00 IEDBASE=0x7fc00000 [DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800 [DEBUG] Relocation complete. [INFO ] microcode: Update skipped, already up-to-date [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7faed800, cpu = 2 [DEBUG] In relocation handler: CPU 2 [DEBUG] New SMBASE=0x7faed800 IEDBASE=0x7fc00000 [DEBUG] Writing SMRR. base = 0x7f800006, mask=0xff800800 [DEBUG] Relocation complete. [INFO ] microcode: Update skipped, already up-to-date [INFO ] Initializing CPU #0 [DEBUG] CPU: vendor Intel device 306c3 [DEBUG] CPU: family 06, model 3c, stepping 03 [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled [DEBUG] IA32_FEATURE_CONTROL already locked [DEBUG] cpu: energy policy set to 6 [INFO ] Turbo is available but hidden [INFO ] Turbo is available and visible [INFO ] CPU #0 initialized [INFO ] Initializing CPU #1 [INFO ] Initializing CPU #3 [INFO ] Initializing CPU #2 [DEBUG] CPU: vendor Intel device 306c3 [DEBUG] CPU: family 06, model 3c, stepping 03 [DEBUG] CPU: vendor Intel device 306c3 [DEBUG] CPU: family 06, model 3c, stepping 03 [DEBUG] CPU: vendor Intel device 306c3 [DEBUG] CPU: family 06, model 3c, stepping 03 [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled [DEBUG] IA32_FEATURE_CONTROL already locked [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled [DEBUG] IA32_FEATURE_CONTROL already locked; VMX status: enabled [DEBUG] IA32_FEATURE_CONTROL already locked [DEBUG] IA32_FEATURE_CONTROL already locked [DEBUG] cpu: energy policy set to 6 [INFO ] CPU #3 initialized [DEBUG] cpu: energy policy set to 6 [DEBUG] cpu: energy policy set to 6 [INFO ] CPU #2 initialized [INFO ] CPU #1 initialized [INFO ] bsp_do_flight_plan done after 116 msecs. [DEBUG] CPU: frequency set to 3800 [DEBUG] Enabling SMIs. [DEBUG] Locking SMM. [DEBUG] CPU_CLUSTER: 0 init finished in 160 msecs [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [DEBUG] PCI: 00:00.0 init [DEBUG] Disabling PEG12. [DEBUG] Disabling PEG11. [DEBUG] Disabling "device 4". [DEBUG] Disabling "device 7". [DEBUG] Set BIOS_RESET_CPL [DEBUG] CPU TDP: 84 Watts [DEBUG] PCI: 00:00.0 init finished in 1 msecs [INFO ] POST: 0x75 [DEBUG] PCI: 00:01.0 init [DEBUG] PCI: 00:01.0 init finished in 0 msecs [INFO ] POST: 0x75 [DEBUG] PCI: 00:02.0 init [INFO ] CBFS: Found 'vbt.bin' @0x42ac0 size 0x561 in mcache @0x7f7dd288 [INFO ] Timestamp - starting LZMA decompress (ignore for x86): 5143352524 [INFO ] Timestamp - finished LZMA decompress (ignore for x86): 5169128028 [INFO ] Found a VBT of 4399 bytes after decompression [INFO ] GMA: Found VBT in CBFS [INFO ] GMA: Found valid VBT in CBFS [DEBUG] GT Power Management Init [INFO ] framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32 [INFO ] x_res x y_res: 1920 x 1080, size: 8294400 at 0x90000000 [DEBUG] GT Power Management Init (post VBIOS) [DEBUG] PCI: 00:02.0 init finished in 63 msecs [INFO ] POST: 0x75 [DEBUG] PCI: 00:03.0 init [DEBUG] Mini-HD: base = 0x82810000 [DEBUG] azalia_audio: Initializing codec #0 [DEBUG] azalia_audio: codec viddid: 80862807 [DEBUG] azalia_audio: verb_size: 16 [DEBUG] azalia_audio: verb loaded. [DEBUG] PCI: 00:03.0 init finished in 3 msecs [INFO ] POST: 0x75 [DEBUG] PCI: 00:14.0 init [DEBUG] PCI: 00:14.0 init finished in 0 msecs [INFO ] POST: 0x75 [DEBUG] PCI: 00:16.0 init [CRIT ] intel_me_path: mbp is not ready! [NOTE ] ME: BIOS path: Error [ERROR] ME: MBP not ready [DEBUG] PCI: 00:16.0 init finished in 11 msecs [INFO ] POST: 0x75 [DEBUG] PCI: 00:1a.0 init [DEBUG] EHCI: Setting up controller.. done. [DEBUG] PCI: 00:1a.0 init finished in 0 msecs [INFO ] POST: 0x75 [DEBUG] PCI: 00:1b.0 init [DEBUG] Azalia: base = 0x82814000 [DEBUG] Azalia: codec_mask = 01 [DEBUG] azalia_audio: Initializing codec #0 [DEBUG] azalia_audio: codec viddid: 10ec0662 [DEBUG] azalia_audio: verb_size: 44 [DEBUG] azalia_audio: verb not loaded. [DEBUG] PCI: 00:1b.0 init finished in 4 msecs [INFO ] POST: 0x75 [DEBUG] PCI: 00:1c.0 init [DEBUG] Initializing PCH PCIe bridge. [DEBUG] PCI: 00:1c.0 init finished in 0 msecs [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [DEBUG] PCI: 00:1c.3 init [DEBUG] Initializing PCH PCIe bridge. [DEBUG] PCI: 00:1c.3 init finished in 0 msecs [INFO ] POST: 0x75 [DEBUG] PCI: 00:1c.4 init [DEBUG] Initializing PCH PCIe bridge. [DEBUG] PCI: 00:1c.4 init finished in 0 msecs [INFO ] POST: 0x75 [DEBUG] PCI: 00:1c.5 init [DEBUG] Initializing PCH PCIe bridge. [DEBUG] PCI: 00:1c.5 init finished in 0 msecs [INFO ] POST: 0x75 [DEBUG] PCI: 00:1d.0 init [DEBUG] EHCI: Setting up controller.. done. [DEBUG] PCI: 00:1d.0 init finished in 0 msecs [INFO ] POST: 0x75 [DEBUG] PCI: 00:1f.0 init [DEBUG] pch: lpc_init [DEBUG] IOAPIC: Initializing IOAPIC at 0xfec00000 [DEBUG] IOAPIC: 24 interrupts [DEBUG] IOAPIC: Clearing IOAPIC at 0xfec00000 [DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00 [INFO ] Set power off after power failure. [INFO ] NMI sources disabled. [DEBUG] LynxPoint H PM init [DEBUG] RTC: failed = 0x0 [DEBUG] RTC Init [DEBUG] apm_control: Disabling ACPI. [DEBUG] APMC done. [DEBUG] PCI: 00:1f.0 init finished in 8 msecs [INFO ] POST: 0x75 [DEBUG] PCI: 00:1f.2 init [DEBUG] SATA: Initializing... [DEBUG] SATA: Controller in AHCI mode. [DEBUG] ABAR: 0x82818000 [DEBUG] PCI: 00:1f.2 init finished in 0 msecs [INFO ] POST: 0x75 [DEBUG] PCI: 00:1f.3 init [DEBUG] PCI: 00:1f.3 init finished in 0 msecs [INFO ] POST: 0x75 [DEBUG] PCI: 03:00.0 init [INFO ] CBFS: Found 'rt8168-macaddress' @0x42a80 size 0x11 in mcache @0x7f7dd25c [DEBUG] r8168: Resetting NIC...done [DEBUG] r8168: Programming MAC Address...done [DEBUG] r8168: Customized LED 0x824 [DEBUG] r8168: read back LED setting as 0x824 [DEBUG] PCI: 03:00.0 init finished in 7 msecs [INFO ] POST: 0x75 [INFO ] POST: 0x75 [DEBUG] PNP: 002e.1 init [DEBUG] PNP: 002e.1 init finished in 0 msecs [INFO ] POST: 0x75 [DEBUG] PNP: 002e.2 init [DEBUG] PNP: 002e.2 init finished in 0 msecs [INFO ] POST: 0x75 [DEBUG] PNP: 002e.3 init [DEBUG] PNP: 002e.3 init finished in 0 msecs [INFO ] POST: 0x75 [DEBUG] PNP: 002e.5 init [DEBUG] PNP: 002e.5 init finished in 0 msecs [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [DEBUG] PNP: 002e.b init [DEBUG] PNP: 002e.b init finished in 0 msecs [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] POST: 0x75 [INFO ] Devices initialized [DEBUG] BS: BS_DEV_INIT run times (exec / console): 125 / 280 ms [DEBUG] clear_memory: Clearing DRAM 0000000000000000-0000000000005000 [ERROR] Null dereference at eip: 0x7f791e5a [DEBUG] clear_memory: Clearing DRAM 000000000000a000-00000000000a0000 [DEBUG] clear_memory: Clearing DRAM 00000000000c0000-000000007f75a000 [DEBUG] clear_memory: Clearing DRAM 000000007f800000-0000000080000000 [DEBUG] clear_memory: Clearing DRAM 0000000100000000-000000047de00000 [DEBUG] memset_pae: Using virtual address 0x00200000 as scratchpad [DEBUG] memset_pae: Using address 0x00005000 for page tables [DEBUG] clear_memory: Clearing DRAM 0000000000005000-000000000000a000 [DEBUG] BS: BS_DEV_INIT exit times (exec / console): 763 / 5 ms [INFO ] POST: 0x76 [INFO ] Finalize devices... [DEBUG] PCI: 00:00.0 final [DEBUG] PCI: 00:16.0 final [INFO ] ME: MBP cleared [DEBUG] PCI: 00:1b.0 final [DEBUG] PCI: 00:1f.0 final [INFO ] Manufacturer: ef [INFO ] SF: Detected ef 4016 with sector size 0x1000, total 0x400000 [DEBUG] apm_control: Finalizing SMM. [DEBUG] APMC done. [INFO ] Devices finalized [INFO ] Timestamp - device setup done: 8524561468 [DEBUG] BS: BS_POST_DEVICE run times (exec / console): 0 / 27 ms [INFO ] POST: 0x77 [INFO ] Timestamp - cbmem post: 8550839800 [DEBUG] BS: BS_OS_RESUME_CHECK run times (exec / console): 0 / 7 ms [INFO ] POST: 0x79 [INFO ] Timestamp - write tables: 8575053824 [INFO ] POST: 0x9c [INFO ] CBFS: Found 'fallback/dsdt.aml' @0x40180 size 0x28af in mcache @0x7f7dd230 [WARN ] CBFS: 'fallback/slic' not found. [INFO ] ACPI: Writing ACPI tables at 7f72e000. [DEBUG] ACPI: * FACS [DEBUG] ACPI: * DSDT [DEBUG] ACPI: * FADT [DEBUG] ACPI: added table 1/32, length now 40 [DEBUG] ACPI: * SSDT [DEBUG] Found 1 CPU(s) with 4 core(s) each. [DEBUG] PSS: 3401MHz power 84000 control 0x2600 status 0x2600 [DEBUG] PSS: 3400MHz power 84000 control 0x2200 status 0x2200 [DEBUG] PSS: 2800MHz power 64431 control 0x1c00 status 0x1c00 [DEBUG] PSS: 2400MHz power 52646 control 0x1800 status 0x1800 [DEBUG] PSS: 2000MHz power 41835 control 0x1400 status 0x1400 [DEBUG] PSS: 1600MHz power 31781 control 0x1000 status 0x1000 [DEBUG] PSS: 1200MHz power 22619 control 0xc00 status 0xc00 [DEBUG] PSS: 800MHz power 14331 control 0x800 status 0x800 [DEBUG] PSS: 3401MHz power 84000 control 0x2600 status 0x2600 [DEBUG] PSS: 3400MHz power 84000 control 0x2200 status 0x2200 [DEBUG] PSS: 2800MHz power 64431 control 0x1c00 status 0x1c00 [DEBUG] PSS: 2400MHz power 52646 control 0x1800 status 0x1800 [DEBUG] PSS: 2000MHz power 41835 control 0x1400 status 0x1400 [DEBUG] PSS: 1600MHz power 31781 control 0x1000 status 0x1000 [DEBUG] PSS: 1200MHz power 22619 control 0xc00 status 0xc00 [DEBUG] PSS: 800MHz power 14331 control 0x800 status 0x800 [DEBUG] PSS: 3401MHz power 84000 control 0x2600 status 0x2600 [DEBUG] PSS: 3400MHz power 84000 control 0x2200 status 0x2200 [DEBUG] PSS: 2800MHz power 64431 control 0x1c00 status 0x1c00 [DEBUG] PSS: 2400MHz power 52646 control 0x1800 status 0x1800 [DEBUG] PSS: 2000MHz power 41835 control 0x1400 status 0x1400 [DEBUG] PSS: 1600MHz power 31781 control 0x1000 status 0x1000 [DEBUG] PSS: 1200MHz power 22619 control 0xc00 status 0xc00 [DEBUG] PSS: 800MHz power 14331 control 0x800 status 0x800 [DEBUG] PSS: 3401MHz power 84000 control 0x2600 status 0x2600 [DEBUG] PSS: 3400MHz power 84000 control 0x2200 status 0x2200 [DEBUG] PSS: 2800MHz power 64431 control 0x1c00 status 0x1c00 [DEBUG] PSS: 2400MHz power 52646 control 0x1800 status 0x1800 [DEBUG] PSS: 2000MHz power 41835 control 0x1400 status 0x1400 [DEBUG] PSS: 1600MHz power 31781 control 0x1000 status 0x1000 [DEBUG] PSS: 1200MHz power 22619 control 0xc00 status 0xc00 [DEBUG] PSS: 800MHz power 14331 control 0x800 status 0x800 [DEBUG] Generating ACPI PIRQ entries [DEBUG] ACPI: added table 2/32, length now 44 [DEBUG] ACPI: * MCFG [DEBUG] ACPI: added table 3/32, length now 48 [DEBUG] ACPI: * MADT [DEBUG] IOAPIC: 24 interrupts [DEBUG] ACPI: added table 4/32, length now 52 [DEBUG] current = 7f732250 [DEBUG] ACPI: * DMAR [DEBUG] ACPI: added table 5/32, length now 56 [DEBUG] ACPI: * HPET [DEBUG] ACPI: added table 6/32, length now 60 [DEBUG] current = 7f732350 [INFO ] ACPI: done. [DEBUG] ACPI tables: 17232 bytes. [DEBUG] smbios_write_tables: 7f726000 [DEBUG] SMBIOS firmware version is set to coreboot_version: '4.18-751-gfb970a43bd' [INFO ] Create SMBIOS type 16 [INFO ] Create SMBIOS type 17 [INFO ] Create SMBIOS type 20 [DEBUG] SMBIOS tables: 995 bytes. [DEBUG] Writing table forward entry at 0x00000500 [DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 6069 [DEBUG] Writing coreboot table at 0x7f752000 [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES [DEBUG] 1. 0000000000001000-000000000009ffff: RAM [DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED [DEBUG] 3. 0000000000100000-000000007f725fff: RAM [DEBUG] 4. 000000007f726000-000000007f76efff: CONFIGURATION TABLES [DEBUG] 5. 000000007f76f000-000000007f7cbfff: RAMSTAGE [DEBUG] 6. 000000007f7cc000-000000007f7fffff: CONFIGURATION TABLES [DEBUG] 7. 000000007f800000-00000000821fffff: RESERVED [DEBUG] 8. 00000000f0000000-00000000f3ffffff: RESERVED [DEBUG] 9. 00000000fed10000-00000000fed19fff: RESERVED [DEBUG] 10. 00000000fed80000-00000000fed84fff: RESERVED [DEBUG] 11. 00000000fed90000-00000000fed91fff: RESERVED [DEBUG] 12. 0000000100000000-000000047ddfffff: RAM [INFO ] Setting up bootsplash in 1920x1080@32 [INFO ] CBFS: Found 'bootsplash.jpg' @0x386c0 size 0x7a82 in mcache @0x7f7dd208 [DEBUG] Bootsplash image resolution: 400x400 [ERROR] Bootsplash could not be decoded. jpeg_decode returned 3. [DEBUG] Wrote coreboot table at: 0x7f752000, 0x3fc bytes, checksum 8570 [DEBUG] coreboot table: 1044 bytes. [DEBUG] IMD ROOT 0. 0x7f7ff000 0x00001000 [DEBUG] IMD SMALL 1. 0x7f7fe000 0x00001000 [DEBUG] CONSOLE 2. 0x7f7de000 0x00020000 [DEBUG] RO MCACHE 3. 0x7f7dd000 0x00000428 [DEBUG] TIME STAMP 4. 0x7f7dc000 0x00000910 [DEBUG] MEM INFO 5. 0x7f7db000 0x00000788 [DEBUG] AFTER CAR 6. 0x7f7cc000 0x0000f000 [DEBUG] RAMSTAGE 7. 0x7f76e000 0x0005e000 [DEBUG] SMM BACKUP 8. 0x7f75e000 0x00010000 [DEBUG] IGD OPREGION 9. 0x7f75a000 0x0000312f [DEBUG] COREBOOT 10. 0x7f752000 0x00008000 [DEBUG] ACPI 11. 0x7f72e000 0x00024000 [DEBUG] SMBIOS 12. 0x7f726000 0x00008000 [DEBUG] IMD small region: [DEBUG] IMD ROOT 0. 0x7f7fec00 0x00000400 [DEBUG] FMAP 1. 0x7f7feb20 0x000000e0 [DEBUG] ROMSTAGE 2. 0x7f7feb00 0x00000004 [DEBUG] ROMSTG STCK 3. 0x7f7fea40 0x000000a8 [DEBUG] ACPI GNVS 4. 0x7f7fe980 0x000000b0 [INFO ] Timestamp - finalize chips: 8779276236 [DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 2 / 65 ms [INFO ] POST: 0x7a [INFO ] Timestamp - starting to load payload: 8804381088 [INFO ] CBFS: Found 'fallback/payload' @0x4b500 size 0x11bf3 in mcache @0x7f7dd324 [DEBUG] Checking segment from ROM address 0xffe5b72c [DEBUG] Payload being loaded at below 1MiB without region being marked as RAM usable. [DEBUG] Checking segment from ROM address 0xffe5b748 [DEBUG] Loading segment from ROM address 0xffe5b72c [DEBUG] code (compression=1) [DEBUG] New segment dstaddr 0x000de6e0 memsize 0x21920 srcaddr 0xffe5b764 filesize 0x11bbb [DEBUG] Loading Segment: addr: 0x000de6e0 memsz: 0x0000000000021920 filesz: 0x0000000000011bbb [DEBUG] using LZMA [INFO ] Timestamp - starting LZMA decompress (ignore for x86): 8852010392 [INFO ] Timestamp - finished LZMA decompress (ignore for x86): 8944568223 [DEBUG] Loading segment from ROM address 0xffe5b748 [DEBUG] Entry Point 0x000fd28c [DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 20 / 31 ms [INFO ] POST: 0x7b [DEBUG] ICH-NM10-PCH: watchdog disabled [DEBUG] Jumping to boot code at 0x000fd28c(0x7f752000) [INFO ] POST: 0xf8 [INFO ] Timestamp - selfboot jump: 8986348880 SeaBIOS (version rel-1.16.0-0-gd239552) BUILD: gcc: (coreboot toolchain v2022-11-25_a45ed44724) 11.2.0 binutils: (GNU Binutils) 2.37 Found coreboot cbmem console @ 7f7de000 Found mainboard ASROCK H81M-HDS Relocating init from 0x000dfe40 to 0x7f6d8aa0 (size 54464) Found CBFS header at 0xffe1022c multiboot: eax=7f7a7cc8, ebx=7f7a7c44 Found 17 PCI devices (max PCI bus is 05) Copying SMBIOS from 0x7f726000 to 0x000f61e0 Copying SMBIOS 3.0 from 0x7f726020 to 0x000f61c0 Copying ACPI RSDP from 0x7f72e000 to 0x000f6190 table(50434146)=0x7f730b50 (via xsdt) Using pmtimer, ioport 0x508 Scan for VGA option rom Running option rom at c000:0003 pmm call arg1=0 Turning on vga text mode console SeaBIOS (version rel-1.16.0-0-gd239552) PCI: XHCI at 00:14.0 (mmio 0x82800000) XHCI init: regs @ 0x82800000, 17 ports, 32 slots, 32 byte contexts XHCI protocol USB 2.00, 10 ports (offset 1), def 3001 XHCI protocol USB 3.00, 2 ports (offset 16), def 1000 XHCI extcap 0xc1 @ 0x82808040 XHCI extcap 0xc0 @ 0x82808070 XHCI extcap 0x1 @ 0x8280846c EHCI init on dev 00:1a.0 (regs=0x82819020) EHCI init on dev 00:1d.0 (regs=0x8281a020) AHCI controller at 00:1f.2, iobase 0x82818000, irq 10 Searching bootorder for: HALT Found 0 lpt ports Found 1 serial ports Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0 AHCI/0: Set transfer mode to UDMA-6 Got ps2 nak (status=51) Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@0/disk@0 AHCI/0: registering: "AHCI/0: SanDisk SDSSDHII120G ATA-9 Hard-Disk (111 GiBytes)" XHCI no devices found USB keyboard initialized Searching bootorder for: /pci@i0cf8/usb@1a/hub@1/storage@2/*@0/*@0,0 Searching bootorder for: /pci@i0cf8/usb@1a/hub@1/usb-*@2 USB MSC vendor='Intenso' product='Basic Line' rev='8.07' type=0 removable=1 USB MSC blksize=512 sectors=61440000 Initialized USB HUB (1 ports used) Initialized USB HUB (1 ports used) All threads complete. Scan for option roms Press ESC for boot menu. jpeg_decode failed with return code 9... Searching bootorder for: HALT drive 0x000f6120: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=234441648 drive 0x000f60e0: PCHS=0/0/0 translation=lba LCHS=1024/255/63 s=61440000 Space available for UMB: c7800-eb800, f5a00-f60e0 Returned 184320 bytes of ZoneHigh e820 map has 10 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 000000007f713000 = 1 RAM 4: 000000007f713000 - 0000000082200000 = 2 RESERVED 5: 00000000f0000000 - 00000000f4000000 = 2 RESERVED 6: 00000000fed10000 - 00000000fed1a000 = 2 RESERVED 7: 00000000fed80000 - 00000000fed85000 = 2 RESERVED 8: 00000000fed90000 - 00000000fed92000 = 2 RESERVED 9: 0000000100000000 - 000000047de00000 = 1 RAM enter handle_19: NULL Booting from Hard Disk... Booting from 0000:7c00