Nick: hell
E-mail: NULL
Board: Prodrive Hermes
Contents: 


[NOTE ]  coreboot-4.18-48-g881ce1bd97 Thu Oct 20 15:25:28 UTC 2022 bootblock starting (log level: 7)...
[DEBUG]  CPU: Intel(R) Xeon(R) E-2226GE CPU @ 3.40GHz
[DEBUG]  CPU: ID 906ea, Coffeelake U0 (6+2), ucode: 000000ef
[DEBUG]  CPU: AES supported, TXT supported, VT supported
[DEBUG]  MCH: device id 3ec6 (rev 07) is Coffeelake-S WS(6+2)
[DEBUG]  PCH: device id a309 (rev 10) is Cannonlake-H C246
[DEBUG]  IGD: device id 3e96 (rev 00) is Coffeelake-S GT2
[INFO ]  PMC: Using default GPE route.
[INFO ]  BMC HSI 0x3
[DEBUG]  FMAP: Found "FLASH" version 1.1 at 0x1750000.
[DEBUG]  FMAP: base = 0xfe000000 size = 0x2000000 #areas = 5
[DEBUG]  FMAP: area COREBOOT found @ 1750200 (9108992 bytes)
[INFO ]  CBFS: mcache @0xfef21400 built for 16 files, used 0x388 of 0x4000 bytes
[INFO ]  CBFS: Found 'fallback/romstage' @0x80 size 0xcb58 in mcache @0xfef2142c
[DEBUG]  BS: bootblock times (exec / console): total (unknown) / 96 ms


[NOTE ]  coreboot-4.18-48-g881ce1bd97 Thu Oct 20 15:25:28 UTC 2022 romstage starting (log level: 7)...
[INFO ]  POST: 0x00
[DEBUG]  pm1_sts: 0000 pm1_en: 0000 pm1_cnt: 00001c00
[DEBUG]  gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
[DEBUG]  gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
[DEBUG]  gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
[DEBUG]  gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000
[DEBUG]  TCO_STS:   0000 0000
[DEBUG]  GEN_PMCON: e0015008 00000200
[DEBUG]  GBLRST_CAUSE: 00000000 00000000
[DEBUG]  HPR_CAUSE0: 00000000
[DEBUG]  prev_sleep_state 5
[DEBUG]  FMAP: area COREBOOT found @ 1750200 (9108992 bytes)
[INFO ]  CBFS: Found 'fspm.bin' @0x97dc0 size 0x88000 in mcache @0xfef21660
[INFO ]  POST: 0x34
[DEBUG]  FMAP: area RW_MRC_CACHE found @ 1700000 (65536 bytes)
[DEBUG]  CFG EEPROM: Board settings CRC OK for 12 / 12 bytes
[DEBUG]  CFG EEPROM: Signature valid.
[INFO ]  POST: 0x36
[INFO ]  POST: 0x92
[INFO ]  POST: 0x98
[DEBUG]  CBMEM:
[DEBUG]  IMD: root @ 0x89fff000 254 entries.
[DEBUG]  IMD: root @ 0x89ffec00 62 entries.
[DEBUG]  External stage cache:
[DEBUG]  IMD: root @ 0x8abff000 254 entries.
[DEBUG]  IMD: root @ 0x8abfec00 62 entries.
[DEBUG]  FMAP: area RW_MRC_CACHE found @ 1700000 (65536 bytes)
[DEBUG]  MRC: Checking cached data update for 'RW_MRC_CACHE'.
[INFO ]  SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
[DEBUG]  MRC: 'RW_MRC_CACHE' does not need update.
[DEBUG]  4 DIMMs found
[DEBUG]  SMM Memory Map
[DEBUG]  SMRAM       : 0x8a000000 0x1000000
[DEBUG]   Subregion 0: 0x8a000000 0xa00000
[DEBUG]   Subregion 1: 0x8aa00000 0x200000
[DEBUG]   Subregion 2: 0x8ac00000 0x400000
[DEBUG]  top_of_ram = 0x8a000000
[DEBUG]  Normal boot
[INFO ]  CBFS: Found 'fallback/postcar' @0x14ba40 size 0x5a48 in mcache @0xfef216d4
[DEBUG]  Loading module at 0x89cdf000 with entry 0x89cdf031. filesize: 0x56a0 memsize: 0xb9d8
[DEBUG]  Processing 218 relocs. Offset value of 0x87cdf000
[DEBUG]  BS: romstage times (exec / console): total (unknown) / 222 ms


[NOTE ]  coreboot-4.18-48-g881ce1bd97 Thu Oct 20 15:25:28 UTC 2022 postcar starting (log level: 7)...
[DEBUG]  Normal boot
[DEBUG]  FMAP: area COREBOOT found @ 1750200 (9108992 bytes)
[INFO ]  CBFS: Found 'fallback/ramstage' @0x73140 size 0x2177d in mcache @0x89ced10c
[DEBUG]  Loading module at 0x89c62000 with entry 0x89c62000. filesize: 0x47128 memsize: 0x7b210
[DEBUG]  Processing 4776 relocs. Offset value of 0x85c62000
[DEBUG]  BS: postcar times (exec / console): total (unknown) / 48 ms


[NOTE ]  coreboot-4.18-48-g881ce1bd97 Thu Oct 20 15:25:28 UTC 2022 ramstage starting (log level: 7)...
[INFO ]  POST: 0x39
[INFO ]  POST: 0x6f
[DEBUG]  Normal boot
[INFO ]  POST: 0x70
[DEBUG]  BS: BS_PRE_DEVICE run times (exec / console): 0 / 3 ms
[DEBUG]  CFG EEPROM: Board settings CRC OK for 12 / 12 bytes
[DEBUG]  CFG EEPROM: Signature valid.
[DEBUG]  BS: BS_PRE_DEVICE exit times (exec / console): 70 / 11 ms
[DEBUG]  FMAP: area COREBOOT found @ 1750200 (9108992 bytes)
[INFO ]  CBFS: Found 'cpu_microcode_blob.bin' @0xcc80 size 0x66400 in mcache @0x89ced0ac
[DEBUG]  microcode: sig=0x906ea pf=0x2 revision=0xef
[DEBUG]  Skip microcode update
[INFO ]  CBFS: Found 'fsps.bin' @0x11fe00 size 0x2bbd3 in mcache @0x89ced2a0
[DEBUG]  Detected 6 core, 6 thread CPU.
[DEBUG]  Setting up SMI for CPU
[DEBUG]  IED base = 0x8ac00000
[DEBUG]  IED size = 0x00400000
[INFO ]  Will perform SMM setup.
[INFO ]  CPU: Intel(R) Xeon(R) E-2226GE CPU @ 3.40GHz.
[INFO ]  LAPIC 0x0 in XAPIC mode.
[DEBUG]  Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
[DEBUG]  Processing 18 relocs. Offset value of 0x00030000
[DEBUG]  Attempting to start 5 APs
[DEBUG]  Waiting for 10ms after sending INIT.
[DEBUG]  Waiting for SIPI to complete...
[DEBUG]  done.
[INFO ]  LAPIC 0x6 in XAPIC mode.
[INFO ]  LAPIC 0xa in XAPIC mode.
[DEBUG]  Waiting for SIPI to complete...
[DEBUG]  done.
[INFO ]  AP: slot 5 apic_id a, MCU rev: 0x000000ef
[INFO ]  LAPIC 0x2 in XAPIC mode.
[INFO ]  LAPIC 0x8 in XAPIC mode.
[INFO ]  AP: slot 1 apic_id 2, MCU rev: 0x000000ef
[INFO ]  LAPIC 0x4 in XAPIC mode.
[INFO ]  AP: slot 3 apic_id 6, MCU rev: 0x000000ef
[INFO ]  AP: slot 2 apic_id 4, MCU rev: 0x000000ef
[INFO ]  AP: slot 4 apic_id 8, MCU rev: 0x000000ef
[DEBUG]  Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1f8 memsize: 0x1f8
[DEBUG]  Processing 11 relocs. Offset value of 0x00038000
[DEBUG]  smm_module_setup_stub: stack_top = 0x8a003000
[DEBUG]  smm_module_setup_stub: per cpu stack_size = 0x800
[DEBUG]  smm_module_setup_stub: runtime.start32_offset = 0x4c
[DEBUG]  smm_module_setup_stub: runtime.smm_size = 0x10000
[DEBUG]  SMM Module: stub loaded at 38000. Will call 0x89c84331
[DEBUG]  Installing permanent SMM handler to 0x8a000000
[DEBUG]  FX_SAVE      [0x8a9ff400-0x8aa00000]
[DEBUG]  HANDLER      [0x8a9fc000-0x8a9fed20]

[DEBUG]  CPU 0
[DEBUG]    ss0        [0x8a9fbc00-0x8a9fc000]
[DEBUG]    stub0      [0x8a9f4000-0x8a9f41f8]

[DEBUG]  CPU 1
[DEBUG]    ss1        [0x8a9fb800-0x8a9fbc00]
[DEBUG]    stub1      [0x8a9f3c00-0x8a9f3df8]

[DEBUG]  CPU 2
[DEBUG]    ss2        [0x8a9fb400-0x8a9fb800]
[DEBUG]    stub2      [0x8a9f3800-0x8a9f39f8]

[DEBUG]  CPU 3
[DEBUG]    ss3        [0x8a9fb000-0x8a9fb400]
[DEBUG]    stub3      [0x8a9f3400-0x8a9f35f8]

[DEBUG]  CPU 4
[DEBUG]    ss4        [0x8a9fac00-0x8a9fb000]
[DEBUG]    stub4      [0x8a9f3000-0x8a9f31f8]

[DEBUG]  CPU 5
[DEBUG]    ss5        [0x8a9fa800-0x8a9fac00]
[DEBUG]    stub5      [0x8a9f2c00-0x8a9f2df8]

[DEBUG]  stacks       [0x8a000000-0x8a003000]
[DEBUG]  Loading module at 0x8a9fc000 with entry 0x8a9fc9fd. filesize: 0x2c68 memsize: 0x2d20
[DEBUG]  Processing 175 relocs. Offset value of 0x8a9fc000
[DEBUG]  Loading module at 0x8a9f4000 with entry 0x8a9f4000. filesize: 0x1f8 memsize: 0x1f8
[DEBUG]  Processing 11 relocs. Offset value of 0x8a9f4000
[DEBUG]  smm_module_setup_stub: stack_top = 0x8a003000
[DEBUG]  smm_module_setup_stub: per cpu stack_size = 0x800
[DEBUG]  smm_module_setup_stub: runtime.start32_offset = 0x4c
[DEBUG]  smm_module_setup_stub: runtime.smm_size = 0xa00000
[DEBUG]  SMM Module: placing smm entry code at 8a9f3c00,  cpu # 0x1
[DEBUG]  SMM Module: placing smm entry code at 8a9f3800,  cpu # 0x2
[DEBUG]  SMM Module: placing smm entry code at 8a9f3400,  cpu # 0x3
[DEBUG]  SMM Module: placing smm entry code at 8a9f3000,  cpu # 0x4
[DEBUG]  SMM Module: placing smm entry code at 8a9f2c00,  cpu # 0x5
[DEBUG]  SMM Module: stub loaded at 8a9f4000. Will call 0x8a9fc9fd
[DEBUG]  Clearing SMI status registers
[DEBUG]  SMI_STS: PM1
[DEBUG]  PM1_STS: TMROF
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9ec000, cpu = 0
[DEBUG]  In relocation handler: CPU 0
[DEBUG]  New SMBASE=0x8a9ec000 IEDBASE=0x8ac00000
[DEBUG]  Writing SMRR. base = 0x8a000006, mask=0xff000800
[DEBUG]  Relocation complete.
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9eac00, cpu = 5
[DEBUG]  In relocation handler: CPU 5
[DEBUG]  New SMBASE=0x8a9eac00 IEDBASE=0x8ac00000
[DEBUG]  Writing SMRR. base = 0x8a000006, mask=0xff000800
[DEBUG]  Relocation complete.
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9eb400, cpu = 3
[DEBUG]  In relocation handler: CPU 3
[DEBUG]  New SMBASE=0x8a9eb400 IEDBASE=0x8ac00000
[DEBUG]  Writing SMRR. base = 0x8a000006, mask=0xff000800
[DEBUG]  Relocation complete.
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9eb800, cpu = 2
[DEBUG]  In relocation handler: CPU 2
[DEBUG]  New SMBASE=0x8a9eb800 IEDBASE=0x8ac00000
[DEBUG]  Writing SMRR. base = 0x8a000006, mask=0xff000800
[DEBUG]  Relocation complete.
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9eb000, cpu = 4
[DEBUG]  In relocation handler: CPU 4
[DEBUG]  New SMBASE=0x8a9eb000 IEDBASE=0x8ac00000
[DEBUG]  Writing SMRR. base = 0x8a000006, mask=0xff000800
[DEBUG]  Relocation complete.
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9ebc00, cpu = 1
[DEBUG]  In relocation handler: CPU 1
[DEBUG]  New SMBASE=0x8a9ebc00 IEDBASE=0x8ac00000
[DEBUG]  Writing SMRR. base = 0x8a000006, mask=0xff000800
[DEBUG]  Relocation complete.
[INFO ]  Initializing CPU #0
[DEBUG]  CPU: vendor Intel device 906ea
[DEBUG]  CPU: family 06, model 9e, stepping 0a
[DEBUG]  Clearing out pending MCEs
[DEBUG]  cpu: energy policy set to 6
[INFO ]  Turbo is available but hidden
[INFO ]  Turbo is available and visible
[DEBUG]  VMX status: enabled
[DEBUG]  IA32_FEATURE_CONTROL status: locked
[DEBUG]  Skip microcode update
[INFO ]  CPU #0 initialized
[INFO ]  Initializing CPU #2
[INFO ]  Initializing CPU #3
[INFO ]  Initializing CPU #1
[INFO ]  Initializing CPU #5
[DEBUG]  CPU: vendor Intel device 906ea
[DEBUG]  CPU: family 06, model 9e, stepping 0a
[DEBUG]  CPU: vendor Intel device 906ea
[DEBUG]  CPU: family 06, model 9e, stepping 0a
[INFO ]  Initializing CPU #4
[DEBUG]  Clearing out pending MCEs
[DEBUG]  CPU: vendor Intel device 906ea
[DEBUG]  CPU: family 06, model 9e, stepping 0a
[DEBUG]  CPU: vendor Intel device 906ea
[DEBUG]  CPU: family 06, model 9e, stepping 0a
[DEBUG]  CPU: vendor Intel device 906ea
[DEBUG]  CPU: family 06, model 9e, stepping 0a
[DEBUG]  cpu: energy policy set to 6
[DEBUG]  Clearing out pending MCEs
[DEBUG]  VMX status: enabled
[DEBUG]  cpu: energy policy set to 6
[DEBUG]  IA32_FEATURE_CONTROL status: locked
[DEBUG]  Clearing out pending MCEs
[DEBUG]  Clearing out pending MCEs
[DEBUG]  Skip microcode update
[INFO ]  CPU #3 initialized
[DEBUG]  cpu: energy policy set to 6
[DEBUG]  Clearing out pending MCEs
[DEBUG]  VMX status: enabled
[DEBUG]  cpu: energy policy set to 6
[DEBUG]  cpu: energy policy set to 6
[DEBUG]  IA32_FEATURE_CONTROL status: locked
[DEBUG]  VMX status: enabled
[DEBUG]  Skip microcode update
[INFO ]  CPU #4 initialized
[DEBUG]  IA32_FEATURE_CONTROL status: locked
[DEBUG]  VMX status: enabled
[DEBUG]  VMX status: enabled
[DEBUG]  IA32_FEATURE_CONTROL status: locked
[DEBUG]  Skip microcode update
[INFO ]  CPU #5 initialized
[DEBUG]  Skip microcode update
[INFO ]  CPU #2 initialized
[DEBUG]  IA32_FEATURE_CONTROL status: locked
[DEBUG]  Skip microcode update
[INFO ]  CPU #1 initialized
[INFO ]  bsp_do_flight_plan done after 733 msecs.
[DEBUG]  CPU: frequency set to 4600 MHz
[DEBUG]  Enabling SMIs.
[DEBUG]  Locking SMM.
[DEBUG]  BS: BS_DEV_INIT_CHIPS entry times (exec / console): 557 / 471 ms
[INFO ]  POST: 0x71
[INFO ]  CBFS: Found 'vbt.bin' @0x96f40 size 0x476 in mcache @0x89ced1f4
[INFO ]  Found a VBT of 4608 bytes after decompression
[DEBUG]  CFG EEPROM: Signature valid.
[INFO ]  VR config[0]:
[INFO ]    Psi1Threshold:  80
[INFO ]    Psi2Threshold:  20
[INFO ]    Psi3Threshold:  4
[INFO ]    Psi3Enable:     1
[INFO ]    Psi4Enable:     1
[INFO ]    ImonSlope:      0
[INFO ]    ImonOffset:     0
[INFO ]    VrVoltageLimit: 1520
[INFO ]    IccMax:         44
[INFO ]    AcLoadline:     1030
[INFO ]    DcLoadline:     1030
[INFO ]    TdcEnable:      1
[INFO ]    TdcPowerLimit:  80
[INFO ]  VR config[1]:
[INFO ]    Psi1Threshold:  80
[INFO ]    Psi2Threshold:  20
[INFO ]    Psi3Threshold:  4
[INFO ]    Psi3Enable:     1
[INFO ]    Psi4Enable:     1
[INFO ]    ImonSlope:      0
[INFO ]    ImonOffset:     0
[INFO ]    VrVoltageLimit: 1520
[INFO ]    IccMax:         532
[INFO ]    AcLoadline:     210
[INFO ]    DcLoadline:     210
[INFO ]    TdcEnable:      1
[INFO ]    TdcPowerLimit:  712
[INFO ]  VR config[2]:
[INFO ]    Psi1Threshold:  80
[INFO ]    Psi2Threshold:  20
[INFO ]    Psi3Threshold:  4
[INFO ]    Psi3Enable:     1
[INFO ]    Psi4Enable:     1
[INFO ]    ImonSlope:      0
[INFO ]    ImonOffset:     0
[INFO ]    VrVoltageLimit: 1520
[INFO ]    IccMax:         180
[INFO ]    AcLoadline:     310
[INFO ]    DcLoadline:     310
[INFO ]    TdcEnable:      1
[INFO ]    TdcPowerLimit:  240
[INFO ]  VR config[3]:
[INFO ]    Psi1Threshold:  80
[INFO ]    Psi2Threshold:  20
[INFO ]    Psi3Threshold:  4
[INFO ]    Psi3Enable:     1
[INFO ]    Psi4Enable:     1
[INFO ]    ImonSlope:      0
[INFO ]    ImonOffset:     0
[INFO ]    VrVoltageLimit: 1520
[INFO ]    IccMax:         180
[INFO ]    AcLoadline:     310
[INFO ]    DcLoadline:     310
[INFO ]    TdcEnable:      1
[INFO ]    TdcPowerLimit:  240
[INFO ]  PCI  1.0, PIN A, using IRQ #16
[INFO ]  PCI  1.1, PIN B, using IRQ #17
[INFO ]  PCI  1.2, PIN C, using IRQ #18
[INFO ]  PCI  1.3, PIN D, using IRQ #19
[INFO ]  PCI  2.0, PIN A, using IRQ #20
[INFO ]  PCI  4.0, PIN A, using IRQ #21
[INFO ]  PCI  5.0, PIN A, using IRQ #22
[INFO ]  PCI  8.0, PIN A, using IRQ #23
[INFO ]  PCI 12.0, PIN B, using IRQ #16
[INFO ]  PCI 12.6, PIN A, using IRQ #24
[INFO ]  PCI 13.0, PIN A, using IRQ #25
[INFO ]  PCI 14.0, PIN A, using IRQ #17
[INFO ]  PCI 14.1, PIN B, using IRQ #18
[INFO ]  PCI 14.3, PIN C, using IRQ #19
[INFO ]  PCI 14.5, PIN D, using IRQ #20
[INFO ]  PCI 15.0, PIN A, using IRQ #26
[INFO ]  PCI 15.1, PIN B, using IRQ #27
[INFO ]  PCI 15.2, PIN C, using IRQ #28
[INFO ]  PCI 15.3, PIN D, using IRQ #29
[INFO ]  PCI 16.0, PIN A, using IRQ #21
[INFO ]  PCI 16.1, PIN B, using IRQ #22
[INFO ]  PCI 16.2, PIN C, using IRQ #23
[INFO ]  PCI 16.3, PIN D, using IRQ #16
[INFO ]  PCI 16.4, PIN A, using IRQ #21
[INFO ]  PCI 16.5, PIN B, using IRQ #22
[INFO ]  PCI 17.0, PIN A, using IRQ #17
[INFO ]  PCI 19.2, PIN A, using IRQ #30
[INFO ]  PCI 1B.0, PIN A, using IRQ #16
[INFO ]  PCI 1B.1, PIN B, using IRQ #17
[INFO ]  PCI 1B.2, PIN C, using IRQ #18
[INFO ]  PCI 1B.3, PIN D, using IRQ #19
[INFO ]  PCI 1B.4, PIN A, using IRQ #16
[INFO ]  PCI 1B.5, PIN B, using IRQ #17
[INFO ]  PCI 1B.6, PIN C, using IRQ #18
[INFO ]  PCI 1B.7, PIN D, using IRQ #19
[INFO ]  PCI 1C.0, PIN A, using IRQ #16
[INFO ]  PCI 1C.1, PIN B, using IRQ #17
[INFO ]  PCI 1C.2, PIN C, using IRQ #18
[INFO ]  PCI 1C.3, PIN D, using IRQ #19
[INFO ]  PCI 1C.4, PIN A, using IRQ #16
[INFO ]  PCI 1C.5, PIN B, using IRQ #17
[INFO ]  PCI 1C.6, PIN C, using IRQ #18
[INFO ]  PCI 1C.7, PIN D, using IRQ #19
[INFO ]  PCI 1D.0, PIN A, using IRQ #16
[INFO ]  PCI 1D.1, PIN B, using IRQ #17
[INFO ]  PCI 1D.2, PIN C, using IRQ #18
[INFO ]  PCI 1D.3, PIN D, using IRQ #19
[INFO ]  PCI 1D.4, PIN A, using IRQ #16
[INFO ]  PCI 1D.5, PIN B, using IRQ #17
[INFO ]  PCI 1D.6, PIN C, using IRQ #18
[INFO ]  PCI 1D.7, PIN D, using IRQ #19
[INFO ]  PCI 1E.0, PIN A, using IRQ #31
[INFO ]  PCI 1E.1, PIN B, using IRQ #32
[INFO ]  PCI 1E.2, PIN C, using IRQ #33
[INFO ]  PCI 1E.3, PIN D, using IRQ #34
[INFO ]  PCI 1F.3, PIN B, using IRQ #21
[INFO ]  PCI 1F.4, PIN C, using IRQ #22
[INFO ]  PCI 1F.6, PIN D, using IRQ #23
[INFO ]  PCI 1F.7, PIN A, using IRQ #20
[INFO ]  IRQ: Using dynamically assigned PCI IO-APIC IRQs
[INFO ]  POST: 0x93
[INFO ]  FSPS returned 0
[INFO ]  POST: 0x99
[DEBUG]  Display FSP Version Info HOB
[DEBUG]  Reference Code - CPU = 7.0.74.20
[DEBUG]  uCode Version = 0.0.0.f0
[DEBUG]  TXT ACM version = ff.ff.ff.ffff
[DEBUG]  Reference Code - ME = 7.0.74.20
[DEBUG]  MEBx version = 0.0.0.0
[DEBUG]  ME Firmware Version = Consumer SKU
[DEBUG]  Reference Code - CNL PCH = 7.0.74.20
[DEBUG]  PCH-CRID Status = Disabled
[DEBUG]  PCH-CRID Original Value = ff.ff.ff.ffff
[DEBUG]  PCH-CRID New Value = ff.ff.ff.ffff
[DEBUG]  OPROM - RST - RAID = ff.ff.ff.ffff
[DEBUG]  CNL PCH H A0 Hsio Version = 2.0.0.0
[DEBUG]  CNL PCH H Ax Hsio Version = 9.0.0.0
[DEBUG]  CNL PCH H Bx Hsio Version = d.0.0.0
[DEBUG]  CNL PCH LP B0 Hsio Version = 7.0.0.0
[DEBUG]  CNL PCH LP Bx Hsio Version = 6.0.0.0
[DEBUG]  CNL PCH LP Dx Hsio Version = 8.0.0.0
[DEBUG]  Reference Code - SA - System Agent = 7.0.74.20
[DEBUG]  Reference Code - MRC = 0.7.1.77
[DEBUG]  SA - PCIe Version = 7.0.74.20
[DEBUG]  SA-CRID Status = Disabled
[DEBUG]  SA-CRID Original Value = 0.0.0.7
[DEBUG]  SA-CRID New Value = 0.0.0.7
[DEBUG]  OPROM - VBIOS = ff.ff.ff.ffff
[INFO ]  Found PCIe Root Port #5 at PCI: 00:1c.0.
[INFO ]  Found PCIe Root Port #6 at PCI: 00:1c.5.
[INFO ]  Found PCIe Root Port #7 at PCI: 00:1c.6.
[INFO ]  Found PCIe Root Port #8 at PCI: 00:1c.7.
[INFO ]  Found PCIe Root Port #14 at PCI: 00:1d.0.
[INFO ]  Found PCIe Root Port #15 at PCI: 00:1d.6.
[NOTE ]  pcie_rp_update_dev: Couldn't find PCIe Root Port #21 (originally PCI: 00:1b.4) which was enabled in devicetree, removing.
[NOTE ]  pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
[INFO ]  Remapping PCIe Root Port #5 from PCI: 00:1c.4 to new function number 0.
[NOTE ]  pcie_rp_update_dev: Couldn't find PCIe Root Port #9 (originally PCI: 00:1d.0) which was enabled in devicetree, removing.
[INFO ]  Remapping PCIe Root Port #14 from PCI: 00:1d.5 to new function number 0.
[NOTE ]  pcie_rp_update_dev: Couldn't find PCIe Root Port #16 (originally PCI: 00:1d.7) which was enabled in devicetree, removing.
[DEBUG]  BS: BS_DEV_INIT_CHIPS run times (exec / console): 121 / 758 ms
[INFO ]  POST: 0x72
[INFO ]  Enumerating buses...
[DEBUG]  Root Device scanning...
[DEBUG]  CPU_CLUSTER: 0 enabled
[DEBUG]  DOMAIN: 0000 enabled
[DEBUG]  DOMAIN: 0000 scanning...
[DEBUG]  PCI: pci_scan_bus for bus 00
[INFO ]  POST: 0x24
[DEBUG]  PCI: 00:00.0 [8086/3ec6] enabled
[INFO ]  PCI: Static device PCI: 00:01.0 not found, disabling it.
[INFO ]  PCI: Static device PCI: 00:01.1 not found, disabling it.
[INFO ]  PCI: Static device PCI: 00:01.2 not found, disabling it.
[DEBUG]  PCI: 00:02.0 [8086/3e96] enabled
[INFO ]  PCI: Static device PCI: 00:04.0 not found, disabling it.
[DEBUG]  PCI: 00:08.0 [8086/1911] enabled
[DEBUG]  PCI: 00:12.0 [8086/a379] enabled
[DEBUG]  PCI: 00:14.0 [8086/a36d] enabled
[DEBUG]  PCI: 00:14.2 [8086/a36f] enabled
[DEBUG]  PCI: 00:14.3 [8086/a370] enabled
[DEBUG]  PCI: 00:16.0 [8086/a360] enabled
[INFO ]  PCI: Static device PCI: 00:16.1 not found, disabling it.
[DEBUG]  PCI: 00:17.0 [8086/a352] enabled
[DEBUG]  PCI: 00:19.0 [0000/0000] hidden
[DEBUG]  PCI: 00:19.2 [0000/a347] hidden
[DEBUG]  PCI: 00:1c.0 [8086/a33c] enabled
[DEBUG]  PCI: 00:1c.5 [8086/a33d] enabled
[DEBUG]  PCI: 00:1c.6 [8086/a33e] enabled
[DEBUG]  PCI: 00:1c.7 [8086/a33f] enabled
[DEBUG]  PCI: 00:1d.0 [8086/a335] enabled
[DEBUG]  PCI: 00:1d.6 [8086/a336] enabled
[DEBUG]  PCI: 00:1e.0 [8086/a328] enabled
[DEBUG]  PCI: 00:1e.1 [8086/a329] enabled
[DEBUG]  PCI: 00:1f.0 [8086/a309] enabled
[INFO ]  PCI: Static device PCI: 00:1f.1 not found, disabling it.
[DEBUG]  RTC Init
[INFO ]  Set power on after power failure.
[INFO ]  PMC: Using default GPE route.
[DEBUG]  Disabling Deep S3
[DEBUG]  Disabling Deep S3
[DEBUG]  Enabling Deep S4
[DEBUG]  Enabling Deep S4
[DEBUG]  Enabling Deep S5
[DEBUG]  Enabling Deep S5
[DEBUG]  PCI: 00:1f.2 [0000/0000] hidden
[DEBUG]  PCI: 00:1f.3 [8086/a348] enabled
[DEBUG]  PCI: 00:1f.4 [8086/a323] enabled
[DEBUG]  PCI: 00:1f.5 [8086/a324] enabled
[INFO ]  POST: 0x25
[WARN ]  PCI: Leftover static devices:
[WARN ]  PCI: 00:01.0
[WARN ]  PCI: 00:01.1
[WARN ]  PCI: 00:01.2
[WARN ]  PCI: 00:04.0
[WARN ]  PCI: 00:14.1
[WARN ]  PCI: 00:14.5
[WARN ]  PCI: 00:16.1
[WARN ]  PCI: 00:16.4
[WARN ]  PCI: 00:1e.2
[WARN ]  PCI: 00:1e.3
[WARN ]  PCI: 00:1f.1
[WARN ]  PCI: Check your devicetree.cb.
[DEBUG]  PCI: 00:02.0 scanning...
[DEBUG]  scan_bus: bus PCI: 00:02.0 finished in 0 msecs
[DEBUG]  PCI: 00:14.0 scanning...
[DEBUG]  scan_bus: bus PCI: 00:14.0 finished in 0 msecs
[DEBUG]  PCI: 00:14.3 scanning...
[DEBUG]  GENERIC: 0.0 enabled
[DEBUG]  scan_bus: bus PCI: 00:14.3 finished in 3 msecs
[DEBUG]  PCI: 00:19.0 scanning...
[DEBUG]  scan_bus: bus PCI: 00:19.0 finished in 0 msecs
[DEBUG]  PCI: 00:1c.0 scanning...
[DEBUG]  PCI: pci_scan_bus for bus 01
[INFO ]  POST: 0x24
[DEBUG]  PCI: 01:00.0 [8086/1539] enabled
[INFO ]  POST: 0x25
[INFO ]  POST: 0x55
[INFO ]  Enabling Common Clock Configuration
[INFO ]  ASPM: Enabled L1
[INFO ]  PCIe: Max_Payload_Size adjusted to 128
[DEBUG]  PCI: 01:00.0: No LTR support
[DEBUG]  scan_bus: bus PCI: 00:1c.0 finished in 36 msecs
[DEBUG]  PCI: 00:1c.5 scanning...
[DEBUG]  PCI: pci_scan_bus for bus 02
[INFO ]  POST: 0x24
[DEBUG]  PCI: 02:00.0 [8086/1539] enabled
[INFO ]  POST: 0x25
[INFO ]  POST: 0x55
[INFO ]  Enabling Common Clock Configuration
[INFO ]  ASPM: Enabled L1
[INFO ]  PCIe: Max_Payload_Size adjusted to 128
[DEBUG]  PCI: 02:00.0: No LTR support
[DEBUG]  scan_bus: bus PCI: 00:1c.5 finished in 36 msecs
[DEBUG]  PCI: 00:1c.6 scanning...
[DEBUG]  PCI: pci_scan_bus for bus 03
[INFO ]  POST: 0x24
[DEBUG]  PCI: 03:00.0 [8086/1539] enabled
[INFO ]  POST: 0x25
[INFO ]  POST: 0x55
[INFO ]  Enabling Common Clock Configuration
[INFO ]  ASPM: Enabled L1
[INFO ]  PCIe: Max_Payload_Size adjusted to 128
[DEBUG]  PCI: 03:00.0: No LTR support
[DEBUG]  scan_bus: bus PCI: 00:1c.6 finished in 36 msecs
[DEBUG]  PCI: 00:1c.7 scanning...
[DEBUG]  PCI: pci_scan_bus for bus 04
[INFO ]  POST: 0x24
[DEBUG]  PCI: 04:00.0 [8086/1539] enabled
[INFO ]  POST: 0x25
[INFO ]  POST: 0x55
[INFO ]  Enabling Common Clock Configuration
[INFO ]  ASPM: Enabled L1
[INFO ]  PCIe: Max_Payload_Size adjusted to 128
[DEBUG]  PCI: 04:00.0: No LTR support
[DEBUG]  scan_bus: bus PCI: 00:1c.7 finished in 36 msecs
[DEBUG]  PCI: 00:1d.0 scanning...
[DEBUG]  PCI: pci_scan_bus for bus 05
[INFO ]  POST: 0x24
[DEBUG]  PCI: 05:00.0 [8086/157c] enabled
[INFO ]  POST: 0x25
[INFO ]  POST: 0x55
[INFO ]  Enabling Common Clock Configuration
[INFO ]  ASPM: Enabled L1
[INFO ]  PCIe: Max_Payload_Size adjusted to 128
[DEBUG]  PCI: 05:00.0: No LTR support
[DEBUG]  scan_bus: bus PCI: 00:1d.0 finished in 36 msecs
[DEBUG]  PCI: 00:1d.6 scanning...
[DEBUG]  PCI: pci_scan_bus for bus 06
[INFO ]  POST: 0x24
[DEBUG]  PCI: 06:00.0 subordinate PCI
[DEBUG]  PCI: 06:00.0 [1a03/1150] enabled
[INFO ]  POST: 0x25
[DEBUG]  PCI: 06:00.0 scanning...
[DEBUG]  PCI: pci_scan_bus for bus 07
[INFO ]  POST: 0x24
[DEBUG]  PCI: 07:00.0 [1a03/2000] enabled
[INFO ]  POST: 0x25
[INFO ]  POST: 0x55
[DEBUG]  scan_bus: bus PCI: 06:00.0 finished in 18 msecs
[INFO ]  POST: 0x55
[INFO ]  Enabling Common Clock Configuration
[INFO ]  ASPM: Enabled None
[INFO ]  PCIe: Max_Payload_Size adjusted to 128
[DEBUG]  PCI: 06:00.0: No LTR support
[DEBUG]  scan_bus: bus PCI: 00:1d.6 finished in 70 msecs
[DEBUG]  PCI: 00:1f.0 scanning...
[DEBUG]  PNP: 0c31.0 enabled
[DEBUG]  scan_bus: bus PCI: 00:1f.0 finished in 3 msecs
[DEBUG]  PCI: 00:1f.2 scanning...
[DEBUG]  scan_bus: bus PCI: 00:1f.2 finished in 0 msecs
[DEBUG]  PCI: 00:1f.3 scanning...
[DEBUG]  scan_bus: bus PCI: 00:1f.3 finished in 0 msecs
[DEBUG]  PCI: 00:1f.4 scanning...
[DEBUG]  scan_bus: bus PCI: 00:1f.4 finished in 0 msecs
[INFO ]  POST: 0x55
[DEBUG]  scan_bus: bus DOMAIN: 0000 finished in 663 msecs
[DEBUG]  scan_bus: bus Root Device finished in 681 msecs
[INFO ]  done
[DEBUG]  BS: BS_DEV_ENUMERATE run times (exec / console): 4 / 698 ms
[INFO ]  MRC: Could not find region 'UNIFIED_MRC_CACHE'
[DEBUG]  FMAP: area RW_MRC_CACHE found @ 1700000 (65536 bytes)
[INFO ]  MRC: NOT enabling PRR for 'RW_MRC_CACHE'.
[DEBUG]  BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 19 ms
[INFO ]  POST: 0x73
[DEBUG]  found VGA at PCI: 07:00.0
[DEBUG]  Setting up VGA for PCI: 07:00.0
[DEBUG]  Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 06:00.0
[DEBUG]  Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:1d.6
[DEBUG]  Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
[DEBUG]  Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
[INFO ]  Allocating resources...
[INFO ]  Reading resources...
[DEBUG]  SA MMIO resource: PCIEXBAR ->  base = 0xe0000000, size = 0x10000000
[DEBUG]  SA MMIO resource: MCHBAR   ->  base = 0xfed10000, size = 0x00008000
[DEBUG]  SA MMIO resource: DMIBAR   ->  base = 0xfeda0000, size = 0x00001000
[DEBUG]  SA MMIO resource: EPBAR    ->  base = 0xfeda1000, size = 0x00001000
[DEBUG]  SA MMIO resource: REGBAR   ->  base = 0xfc000000, size = 0x00001000
[DEBUG]  SA MMIO resource: EDRAMBAR ->  base = 0xfed80000, size = 0x00004000
[DEBUG]  SA MMIO resource: GFXVTBAR ->  base = 0xfed90000, size = 0x00001000
[DEBUG]  SA MMIO resource: VTVC0BAR ->  base = 0xfed91000, size = 0x00001000
[INFO ]  Available memory above 4GB: 63208M
[INFO ]  Done reading resources.
[INFO ]  === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
[DEBUG]   PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG]    PCI: 01:00.0 18 *  [0x0 - 0x1f] io
[DEBUG]   PCI: 00:1c.0 io: size: 1000 align: 12 gran: 12 limit: ffff done
[DEBUG]   PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG]    PCI: 01:00.0 10 *  [0x0 - 0x1ffff] mem
[DEBUG]    PCI: 01:00.0 1c *  [0x20000 - 0x23fff] mem
[DEBUG]   PCI: 00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
[DEBUG]   PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG]   PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[DEBUG]   PCI: 00:1c.5 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG]    PCI: 02:00.0 18 *  [0x0 - 0x1f] io
[DEBUG]   PCI: 00:1c.5 io: size: 1000 align: 12 gran: 12 limit: ffff done
[DEBUG]   PCI: 00:1c.5 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG]    PCI: 02:00.0 10 *  [0x0 - 0x1ffff] mem
[DEBUG]    PCI: 02:00.0 1c *  [0x20000 - 0x23fff] mem
[DEBUG]   PCI: 00:1c.5 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
[DEBUG]   PCI: 00:1c.5 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG]   PCI: 00:1c.5 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[DEBUG]   PCI: 00:1c.6 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG]    PCI: 03:00.0 18 *  [0x0 - 0x1f] io
[DEBUG]   PCI: 00:1c.6 io: size: 1000 align: 12 gran: 12 limit: ffff done
[DEBUG]   PCI: 00:1c.6 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG]    PCI: 03:00.0 10 *  [0x0 - 0x1ffff] mem
[DEBUG]    PCI: 03:00.0 1c *  [0x20000 - 0x23fff] mem
[DEBUG]   PCI: 00:1c.6 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
[DEBUG]   PCI: 00:1c.6 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG]   PCI: 00:1c.6 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[DEBUG]   PCI: 00:1c.7 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG]    PCI: 04:00.0 18 *  [0x0 - 0x1f] io
[DEBUG]   PCI: 00:1c.7 io: size: 1000 align: 12 gran: 12 limit: ffff done
[DEBUG]   PCI: 00:1c.7 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG]    PCI: 04:00.0 10 *  [0x0 - 0x1ffff] mem
[DEBUG]    PCI: 04:00.0 1c *  [0x20000 - 0x23fff] mem
[DEBUG]   PCI: 00:1c.7 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
[DEBUG]   PCI: 00:1c.7 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG]   PCI: 00:1c.7 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[DEBUG]   PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG]    PCI: 05:00.0 18 *  [0x0 - 0x1f] io
[DEBUG]   PCI: 00:1d.0 io: size: 1000 align: 12 gran: 12 limit: ffff done
[DEBUG]   PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG]    PCI: 05:00.0 10 *  [0x0 - 0x1ffff] mem
[DEBUG]    PCI: 05:00.0 1c *  [0x20000 - 0x23fff] mem
[DEBUG]   PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
[DEBUG]   PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG]   PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[DEBUG]    PCI: 06:00.0 io: size: 0 align: 12 gran: 12 limit: ffffffff
[DEBUG]     PCI: 07:00.0 18 *  [0x0 - 0x7f] io
[DEBUG]    PCI: 06:00.0 io: size: 1000 align: 12 gran: 12 limit: ffff done
[DEBUG]   PCI: 00:1d.6 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG]    PCI: 06:00.0 1c *  [0x0 - 0xfff] io
[DEBUG]   PCI: 00:1d.6 io: size: 1000 align: 12 gran: 12 limit: ffff done
[DEBUG]    PCI: 06:00.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG]     PCI: 07:00.0 10 *  [0x0 - 0x3ffffff] mem
[DEBUG]     PCI: 07:00.0 14 *  [0x4000000 - 0x401ffff] mem
[DEBUG]    PCI: 06:00.0 mem: size: 4100000 align: 26 gran: 20 limit: ffffffff done
[DEBUG]   PCI: 00:1d.6 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG]    PCI: 06:00.0 20 *  [0x0 - 0x40fffff] mem
[DEBUG]   PCI: 00:1d.6 mem: size: 4100000 align: 26 gran: 20 limit: ffffffff done
[DEBUG]    PCI: 06:00.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG]    PCI: 06:00.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[DEBUG]   PCI: 00:1d.6 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG]   PCI: 00:1d.6 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[INFO ]  === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
[DEBUG]  DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
[DEBUG]   update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
[DEBUG]   update_constraints: PCI: 00:1f.0 84 base 00000080 limit 0000008f io (fixed)
[DEBUG]   update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
[DEBUG]   update_constraints: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
[INFO ]   DOMAIN: 0000: Resource ranges:
[INFO ]   * Base: 1000, Size: 800, Tag: 100
[INFO ]   * Base: 1900, Size: d6a0, Tag: 100
[INFO ]   * Base: efc0, Size: 1040, Tag: 100
[DEBUG]    PCI: 00:1c.0 1c *  [0x2000 - 0x2fff] limit: 2fff io
[DEBUG]    PCI: 00:1c.5 1c *  [0x3000 - 0x3fff] limit: 3fff io
[DEBUG]    PCI: 00:1c.6 1c *  [0x4000 - 0x4fff] limit: 4fff io
[DEBUG]    PCI: 00:1c.7 1c *  [0x5000 - 0x5fff] limit: 5fff io
[DEBUG]    PCI: 00:1d.0 1c *  [0x6000 - 0x6fff] limit: 6fff io
[DEBUG]    PCI: 00:1d.6 1c *  [0x7000 - 0x7fff] limit: 7fff io
[DEBUG]    PCI: 00:02.0 20 *  [0x1000 - 0x103f] limit: 103f io
[DEBUG]    PCI: 00:17.0 20 *  [0x1040 - 0x105f] limit: 105f io
[DEBUG]    PCI: 00:17.0 18 *  [0x1060 - 0x1067] limit: 1067 io
[DEBUG]    PCI: 00:17.0 1c *  [0x1068 - 0x106b] limit: 106b io
[DEBUG]  DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
[DEBUG]  DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
[DEBUG]   update_constraints: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 01 base fed10000 limit fed17fff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 04 base fc000000 limit fc000fff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 07 base fed91000 limit fed91fff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 08 base 00000000 limit 0009ffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 09 base 000c0000 limit 89ffffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 0a base 8a000000 limit 8f7fffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 0b base 100000000 limit 106e7fffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 0c base 000a0000 limit 000bffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 0d base 000c0000 limit 000fffff mem (fixed)
[DEBUG]   update_constraints: PCI: 07:00.0 03 base 000a0000 limit 000bfbff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:1e.0 10 base fe032000 limit fe032fff mem (fixed)
[DEBUG]   update_constraints: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:1f.5 00 base ff000000 limit ffffffff mem (fixed)
[INFO ]   DOMAIN: 0000: Resource ranges:
[INFO ]   * Base: 8f800000, Size: 50800000, Tag: 200
[INFO ]   * Base: f0000000, Size: c000000, Tag: 200
[INFO ]   * Base: fc001000, Size: 1fff000, Tag: 200
[INFO ]   * Base: fe010000, Size: 22000, Tag: 200
[INFO ]   * Base: fe033000, Size: cdd000, Tag: 200
[INFO ]   * Base: fed18000, Size: 28000, Tag: 200
[INFO ]   * Base: fed45000, Size: 3b000, Tag: 200
[INFO ]   * Base: fed84000, Size: c000, Tag: 200
[INFO ]   * Base: fed92000, Size: e000, Tag: 200
[INFO ]   * Base: feda2000, Size: 25e000, Tag: 200
[INFO ]   * Base: 106e800000, Size: 6f91800000, Tag: 100200
[DEBUG]    PCI: 00:02.0 18 *  [0x90000000 - 0x9fffffff] limit: 9fffffff prefmem
[DEBUG]    PCI: 00:1d.6 20 *  [0xa0000000 - 0xa40fffff] limit: a40fffff mem
[DEBUG]    PCI: 00:02.0 10 *  [0xa5000000 - 0xa5ffffff] limit: a5ffffff mem
[DEBUG]    PCI: 00:1c.0 20 *  [0x8f800000 - 0x8f8fffff] limit: 8f8fffff mem
[DEBUG]    PCI: 00:1c.5 20 *  [0x8f900000 - 0x8f9fffff] limit: 8f9fffff mem
[DEBUG]    PCI: 00:1c.6 20 *  [0x8fa00000 - 0x8fafffff] limit: 8fafffff mem
[DEBUG]    PCI: 00:1c.7 20 *  [0x8fb00000 - 0x8fbfffff] limit: 8fbfffff mem
[DEBUG]    PCI: 00:1d.0 20 *  [0x8fc00000 - 0x8fcfffff] limit: 8fcfffff mem
[DEBUG]    PCI: 00:1f.3 20 *  [0x8fd00000 - 0x8fdfffff] limit: 8fdfffff mem
[DEBUG]    PCI: 00:14.0 10 *  [0x8fe00000 - 0x8fe0ffff] limit: 8fe0ffff mem
[DEBUG]    PCI: 00:14.3 10 *  [0x8fe10000 - 0x8fe13fff] limit: 8fe13fff mem
[DEBUG]    PCI: 00:1f.3 10 *  [0x8fe14000 - 0x8fe17fff] limit: 8fe17fff mem
[DEBUG]    PCI: 00:14.2 10 *  [0x8fe18000 - 0x8fe19fff] limit: 8fe19fff mem
[DEBUG]    PCI: 00:17.0 10 *  [0x8fe1a000 - 0x8fe1bfff] limit: 8fe1bfff mem
[DEBUG]    PCI: 00:08.0 10 *  [0x8fe1c000 - 0x8fe1cfff] limit: 8fe1cfff mem
[DEBUG]    PCI: 00:12.0 10 *  [0x8fe1d000 - 0x8fe1dfff] limit: 8fe1dfff mem
[DEBUG]    PCI: 00:14.2 18 *  [0x8fe1e000 - 0x8fe1efff] limit: 8fe1efff mem
[DEBUG]    PCI: 00:16.0 10 *  [0x8fe1f000 - 0x8fe1ffff] limit: 8fe1ffff mem
[DEBUG]    PCI: 00:19.2 10 *  [0x8fe20000 - 0x8fe20fff] limit: 8fe20fff mem
[DEBUG]    PCI: 00:1e.0 18 *  [0x8fe21000 - 0x8fe21fff] limit: 8fe21fff mem
[DEBUG]    PCI: 00:1e.1 10 *  [0x8fe22000 - 0x8fe22fff] limit: 8fe22fff mem
[DEBUG]    PCI: 00:1f.5 10 *  [0x8fe23000 - 0x8fe23fff] limit: 8fe23fff mem
[DEBUG]    PCI: 00:17.0 24 *  [0x8fe24000 - 0x8fe247ff] limit: 8fe247ff mem
[DEBUG]    PCI: 00:17.0 14 *  [0x8fe25000 - 0x8fe250ff] limit: 8fe250ff mem
[DEBUG]    PCI: 00:1f.4 10 *  [0x8fe26000 - 0x8fe260ff] limit: 8fe260ff mem
[DEBUG]  DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
[DEBUG]  PCI: 00:1c.0 io: base: 2000 size: 1000 align: 12 gran: 12 limit: 2fff
[INFO ]   PCI: 00:1c.0: Resource ranges:
[INFO ]   * Base: 2000, Size: 1000, Tag: 100
[DEBUG]    PCI: 01:00.0 18 *  [0x2000 - 0x201f] limit: 201f io
[DEBUG]  PCI: 00:1c.0 io: base: 2000 size: 1000 align: 12 gran: 12 limit: 2fff done
[DEBUG]  PCI: 00:1c.0 mem: base: 8f800000 size: 100000 align: 20 gran: 20 limit: 8f8fffff
[INFO ]   PCI: 00:1c.0: Resource ranges:
[INFO ]   * Base: 8f800000, Size: 100000, Tag: 200
[DEBUG]    PCI: 01:00.0 10 *  [0x8f800000 - 0x8f81ffff] limit: 8f81ffff mem
[DEBUG]    PCI: 01:00.0 1c *  [0x8f820000 - 0x8f823fff] limit: 8f823fff mem
[DEBUG]  PCI: 00:1c.0 mem: base: 8f800000 size: 100000 align: 20 gran: 20 limit: 8f8fffff done
[DEBUG]  PCI: 00:1c.5 io: base: 3000 size: 1000 align: 12 gran: 12 limit: 3fff
[INFO ]   PCI: 00:1c.5: Resource ranges:
[INFO ]   * Base: 3000, Size: 1000, Tag: 100
[DEBUG]    PCI: 02:00.0 18 *  [0x3000 - 0x301f] limit: 301f io
[DEBUG]  PCI: 00:1c.5 io: base: 3000 size: 1000 align: 12 gran: 12 limit: 3fff done
[DEBUG]  PCI: 00:1c.5 mem: base: 8f900000 size: 100000 align: 20 gran: 20 limit: 8f9fffff
[INFO ]   PCI: 00:1c.5: Resource ranges:
[INFO ]   * Base: 8f900000, Size: 100000, Tag: 200
[DEBUG]    PCI: 02:00.0 10 *  [0x8f900000 - 0x8f91ffff] limit: 8f91ffff mem
[DEBUG]    PCI: 02:00.0 1c *  [0x8f920000 - 0x8f923fff] limit: 8f923fff mem
[DEBUG]  PCI: 00:1c.5 mem: base: 8f900000 size: 100000 align: 20 gran: 20 limit: 8f9fffff done
[DEBUG]  PCI: 00:1c.6 io: base: 4000 size: 1000 align: 12 gran: 12 limit: 4fff
[INFO ]   PCI: 00:1c.6: Resource ranges:
[INFO ]   * Base: 4000, Size: 1000, Tag: 100
[DEBUG]    PCI: 03:00.0 18 *  [0x4000 - 0x401f] limit: 401f io
[DEBUG]  PCI: 00:1c.6 io: base: 4000 size: 1000 align: 12 gran: 12 limit: 4fff done
[DEBUG]  PCI: 00:1c.6 mem: base: 8fa00000 size: 100000 align: 20 gran: 20 limit: 8fafffff
[INFO ]   PCI: 00:1c.6: Resource ranges:
[INFO ]   * Base: 8fa00000, Size: 100000, Tag: 200
[DEBUG]    PCI: 03:00.0 10 *  [0x8fa00000 - 0x8fa1ffff] limit: 8fa1ffff mem
[DEBUG]    PCI: 03:00.0 1c *  [0x8fa20000 - 0x8fa23fff] limit: 8fa23fff mem
[DEBUG]  PCI: 00:1c.6 mem: base: 8fa00000 size: 100000 align: 20 gran: 20 limit: 8fafffff done
[DEBUG]  PCI: 00:1c.7 io: base: 5000 size: 1000 align: 12 gran: 12 limit: 5fff
[INFO ]   PCI: 00:1c.7: Resource ranges:
[INFO ]   * Base: 5000, Size: 1000, Tag: 100
[DEBUG]    PCI: 04:00.0 18 *  [0x5000 - 0x501f] limit: 501f io
[DEBUG]  PCI: 00:1c.7 io: base: 5000 size: 1000 align: 12 gran: 12 limit: 5fff done
[DEBUG]  PCI: 00:1c.7 mem: base: 8fb00000 size: 100000 align: 20 gran: 20 limit: 8fbfffff
[INFO ]   PCI: 00:1c.7: Resource ranges:
[INFO ]   * Base: 8fb00000, Size: 100000, Tag: 200
[DEBUG]    PCI: 04:00.0 10 *  [0x8fb00000 - 0x8fb1ffff] limit: 8fb1ffff mem
[DEBUG]    PCI: 04:00.0 1c *  [0x8fb20000 - 0x8fb23fff] limit: 8fb23fff mem
[DEBUG]  PCI: 00:1c.7 mem: base: 8fb00000 size: 100000 align: 20 gran: 20 limit: 8fbfffff done
[DEBUG]  PCI: 00:1d.0 io: base: 6000 size: 1000 align: 12 gran: 12 limit: 6fff
[INFO ]   PCI: 00:1d.0: Resource ranges:
[INFO ]   * Base: 6000, Size: 1000, Tag: 100
[DEBUG]    PCI: 05:00.0 18 *  [0x6000 - 0x601f] limit: 601f io
[DEBUG]  PCI: 00:1d.0 io: base: 6000 size: 1000 align: 12 gran: 12 limit: 6fff done
[DEBUG]  PCI: 00:1d.0 mem: base: 8fc00000 size: 100000 align: 20 gran: 20 limit: 8fcfffff
[INFO ]   PCI: 00:1d.0: Resource ranges:
[INFO ]   * Base: 8fc00000, Size: 100000, Tag: 200
[DEBUG]    PCI: 05:00.0 10 *  [0x8fc00000 - 0x8fc1ffff] limit: 8fc1ffff mem
[DEBUG]    PCI: 05:00.0 1c *  [0x8fc20000 - 0x8fc23fff] limit: 8fc23fff mem
[DEBUG]  PCI: 00:1d.0 mem: base: 8fc00000 size: 100000 align: 20 gran: 20 limit: 8fcfffff done
[DEBUG]  PCI: 00:1d.6 io: base: 7000 size: 1000 align: 12 gran: 12 limit: 7fff
[INFO ]   PCI: 00:1d.6: Resource ranges:
[INFO ]   * Base: 7000, Size: 1000, Tag: 100
[DEBUG]    PCI: 06:00.0 1c *  [0x7000 - 0x7fff] limit: 7fff io
[DEBUG]  PCI: 00:1d.6 io: base: 7000 size: 1000 align: 12 gran: 12 limit: 7fff done
[DEBUG]  PCI: 00:1d.6 mem: base: a0000000 size: 4100000 align: 26 gran: 20 limit: a40fffff
[INFO ]   PCI: 00:1d.6: Resource ranges:
[INFO ]   * Base: a0000000, Size: 4100000, Tag: 200
[DEBUG]    PCI: 06:00.0 20 *  [0xa0000000 - 0xa40fffff] limit: a40fffff mem
[DEBUG]  PCI: 00:1d.6 mem: base: a0000000 size: 4100000 align: 26 gran: 20 limit: a40fffff done
[DEBUG]  PCI: 06:00.0 io: base: 7000 size: 1000 align: 12 gran: 12 limit: 7fff
[INFO ]   PCI: 06:00.0: Resource ranges:
[INFO ]   * Base: 7000, Size: 1000, Tag: 100
[DEBUG]    PCI: 07:00.0 18 *  [0x7000 - 0x707f] limit: 707f io
[DEBUG]  PCI: 06:00.0 io: base: 7000 size: 1000 align: 12 gran: 12 limit: 7fff done
[DEBUG]  PCI: 06:00.0 mem: base: a0000000 size: 4100000 align: 26 gran: 20 limit: a40fffff
[INFO ]   PCI: 06:00.0: Resource ranges:
[INFO ]   * Base: a0000000, Size: 4100000, Tag: 200
[DEBUG]    PCI: 07:00.0 10 *  [0xa0000000 - 0xa3ffffff] limit: a3ffffff mem
[DEBUG]    PCI: 07:00.0 14 *  [0xa4000000 - 0xa401ffff] limit: a401ffff mem
[DEBUG]  PCI: 06:00.0 mem: base: a0000000 size: 4100000 align: 26 gran: 20 limit: a40fffff done
[INFO ]  === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
[DEBUG]  PCI: 00:02.0 10 <- [0x00000000a5000000 - 0x00000000a5ffffff] size 0x01000000 gran 0x18 mem64
[DEBUG]  PCI: 00:02.0 18 <- [0x0000000090000000 - 0x000000009fffffff] size 0x10000000 gran 0x1c prefmem64
[DEBUG]  PCI: 00:02.0 20 <- [0x0000000000001000 - 0x000000000000103f] size 0x00000040 gran 0x06 io
[DEBUG]  PCI: 00:08.0 10 <- [0x000000008fe1c000 - 0x000000008fe1cfff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:12.0 10 <- [0x000000008fe1d000 - 0x000000008fe1dfff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:14.0 10 <- [0x000000008fe00000 - 0x000000008fe0ffff] size 0x00010000 gran 0x10 mem64
[DEBUG]  PCI: 00:14.2 10 <- [0x000000008fe18000 - 0x000000008fe19fff] size 0x00002000 gran 0x0d mem64
[DEBUG]  PCI: 00:14.2 18 <- [0x000000008fe1e000 - 0x000000008fe1efff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:14.3 10 <- [0x000000008fe10000 - 0x000000008fe13fff] size 0x00004000 gran 0x0e mem64
[DEBUG]  PCI: 00:16.0 10 <- [0x000000008fe1f000 - 0x000000008fe1ffff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:17.0 10 <- [0x000000008fe1a000 - 0x000000008fe1bfff] size 0x00002000 gran 0x0d mem
[DEBUG]  PCI: 00:17.0 14 <- [0x000000008fe25000 - 0x000000008fe250ff] size 0x00000100 gran 0x08 mem
[DEBUG]  PCI: 00:17.0 18 <- [0x0000000000001060 - 0x0000000000001067] size 0x00000008 gran 0x03 io
[DEBUG]  PCI: 00:17.0 1c <- [0x0000000000001068 - 0x000000000000106b] size 0x00000004 gran 0x02 io
[DEBUG]  PCI: 00:17.0 20 <- [0x0000000000001040 - 0x000000000000105f] size 0x00000020 gran 0x05 io
[DEBUG]  PCI: 00:17.0 24 <- [0x000000008fe24000 - 0x000000008fe247ff] size 0x00000800 gran 0x0b mem
[DEBUG]  PCI: 00:19.2 10 <- [0x000000008fe20000 - 0x000000008fe20fff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:1c.0 1c <- [0x0000000000002000 - 0x0000000000002fff] size 0x00001000 gran 0x0c bus 01 io
[DEBUG]  PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
[DEBUG]  PCI: 00:1c.0 20 <- [0x000000008f800000 - 0x000000008f8fffff] size 0x00100000 gran 0x14 bus 01 mem
[DEBUG]  PCI: 01:00.0 10 <- [0x000000008f800000 - 0x000000008f81ffff] size 0x00020000 gran 0x11 mem
[DEBUG]  PCI: 01:00.0 18 <- [0x0000000000002000 - 0x000000000000201f] size 0x00000020 gran 0x05 io
[DEBUG]  PCI: 01:00.0 1c <- [0x000000008f820000 - 0x000000008f823fff] size 0x00004000 gran 0x0e mem
[DEBUG]  PCI: 00:1c.5 1c <- [0x0000000000003000 - 0x0000000000003fff] size 0x00001000 gran 0x0c bus 02 io
[DEBUG]  PCI: 00:1c.5 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
[DEBUG]  PCI: 00:1c.5 20 <- [0x000000008f900000 - 0x000000008f9fffff] size 0x00100000 gran 0x14 bus 02 mem
[DEBUG]  PCI: 02:00.0 10 <- [0x000000008f900000 - 0x000000008f91ffff] size 0x00020000 gran 0x11 mem
[DEBUG]  PCI: 02:00.0 18 <- [0x0000000000003000 - 0x000000000000301f] size 0x00000020 gran 0x05 io
[DEBUG]  PCI: 02:00.0 1c <- [0x000000008f920000 - 0x000000008f923fff] size 0x00004000 gran 0x0e mem
[DEBUG]  PCI: 00:1c.6 1c <- [0x0000000000004000 - 0x0000000000004fff] size 0x00001000 gran 0x0c bus 03 io
[DEBUG]  PCI: 00:1c.6 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 03 prefmem
[DEBUG]  PCI: 00:1c.6 20 <- [0x000000008fa00000 - 0x000000008fafffff] size 0x00100000 gran 0x14 bus 03 mem
[DEBUG]  PCI: 03:00.0 10 <- [0x000000008fa00000 - 0x000000008fa1ffff] size 0x00020000 gran 0x11 mem
[DEBUG]  PCI: 03:00.0 18 <- [0x0000000000004000 - 0x000000000000401f] size 0x00000020 gran 0x05 io
[DEBUG]  PCI: 03:00.0 1c <- [0x000000008fa20000 - 0x000000008fa23fff] size 0x00004000 gran 0x0e mem
[DEBUG]  PCI: 00:1c.7 1c <- [0x0000000000005000 - 0x0000000000005fff] size 0x00001000 gran 0x0c bus 04 io
[DEBUG]  PCI: 00:1c.7 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 04 prefmem
[DEBUG]  PCI: 00:1c.7 20 <- [0x000000008fb00000 - 0x000000008fbfffff] size 0x00100000 gran 0x14 bus 04 mem
[DEBUG]  PCI: 04:00.0 10 <- [0x000000008fb00000 - 0x000000008fb1ffff] size 0x00020000 gran 0x11 mem
[DEBUG]  PCI: 04:00.0 18 <- [0x0000000000005000 - 0x000000000000501f] size 0x00000020 gran 0x05 io
[DEBUG]  PCI: 04:00.0 1c <- [0x000000008fb20000 - 0x000000008fb23fff] size 0x00004000 gran 0x0e mem
[DEBUG]  PCI: 00:1d.0 1c <- [0x0000000000006000 - 0x0000000000006fff] size 0x00001000 gran 0x0c bus 05 io
[DEBUG]  PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 05 prefmem
[DEBUG]  PCI: 00:1d.0 20 <- [0x000000008fc00000 - 0x000000008fcfffff] size 0x00100000 gran 0x14 bus 05 mem
[DEBUG]  PCI: 05:00.0 10 <- [0x000000008fc00000 - 0x000000008fc1ffff] size 0x00020000 gran 0x11 mem
[DEBUG]  PCI: 05:00.0 18 <- [0x0000000000006000 - 0x000000000000601f] size 0x00000020 gran 0x05 io
[DEBUG]  PCI: 05:00.0 1c <- [0x000000008fc20000 - 0x000000008fc23fff] size 0x00004000 gran 0x0e mem
[DEBUG]  PCI: 00:1d.6 1c <- [0x0000000000007000 - 0x0000000000007fff] size 0x00001000 gran 0x0c bus 06 io
[DEBUG]  PCI: 00:1d.6 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 06 prefmem
[DEBUG]  PCI: 00:1d.6 20 <- [0x00000000a0000000 - 0x00000000a40fffff] size 0x04100000 gran 0x14 bus 06 mem
[DEBUG]  PCI: 06:00.0 1c <- [0x0000000000007000 - 0x0000000000007fff] size 0x00001000 gran 0x0c bus 07 io
[DEBUG]  PCI: 06:00.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 07 prefmem
[DEBUG]  PCI: 06:00.0 20 <- [0x00000000a0000000 - 0x00000000a40fffff] size 0x04100000 gran 0x14 bus 07 mem
[DEBUG]  PCI: 07:00.0 10 <- [0x00000000a0000000 - 0x00000000a3ffffff] size 0x04000000 gran 0x1a mem
[DEBUG]  PCI: 07:00.0 14 <- [0x00000000a4000000 - 0x00000000a401ffff] size 0x00020000 gran 0x11 mem
[DEBUG]  PCI: 07:00.0 18 <- [0x0000000000007000 - 0x000000000000707f] size 0x00000080 gran 0x07 io
[DEBUG]  PCI: 00:1e.0 18 <- [0x000000008fe21000 - 0x000000008fe21fff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:1e.1 10 <- [0x000000008fe22000 - 0x000000008fe22fff] size 0x00001000 gran 0x0c mem64
[DEBUG]  PCI: 00:1f.3 10 <- [0x000000008fe14000 - 0x000000008fe17fff] size 0x00004000 gran 0x0e mem64
[DEBUG]  PCI: 00:1f.3 20 <- [0x000000008fd00000 - 0x000000008fdfffff] size 0x00100000 gran 0x14 mem64
[DEBUG]  PCI: 00:1f.4 10 <- [0x000000008fe26000 - 0x000000008fe260ff] size 0x00000100 gran 0x08 mem64
[DEBUG]  PCI: 00:1f.5 10 <- [0x000000008fe23000 - 0x000000008fe23fff] size 0x00001000 gran 0x0c mem
[INFO ]  Done setting resources.
[INFO ]  Done allocating resources.
[DEBUG]  BS: BS_DEV_RESOURCES run times (exec / console): 6 / 2483 ms
[INFO ]  POST: 0x94
[INFO ]  POST: 0xa2
[DEBUG]  BS: BS_DEV_ENABLE entry times (exec / console): 1 / 5 ms
[INFO ]  POST: 0x74
[INFO ]  Enabling resources...
[DEBUG]  PCI: 00:00.0 subsystem <- 8086/3ec6
[DEBUG]  PCI: 00:00.0 cmd <- 06
[DEBUG]  PCI: 00:02.0 subsystem <- 8086/3e96
[DEBUG]  PCI: 00:02.0 cmd <- 03
[DEBUG]  PCI: 00:08.0 subsystem <- 8086/1911
[DEBUG]  PCI: 00:08.0 cmd <- 06
[DEBUG]  PCI: 00:12.0 subsystem <- 8086/a379
[DEBUG]  PCI: 00:12.0 cmd <- 02
[DEBUG]  PCI: 00:14.0 subsystem <- 8086/a36d
[DEBUG]  PCI: 00:14.0 cmd <- 02
[DEBUG]  PCI: 00:14.2 subsystem <- 8086/a36f
[DEBUG]  PCI: 00:14.2 cmd <- 02
[DEBUG]  PCI: 00:14.3 subsystem <- 8086/a370
[DEBUG]  PCI: 00:14.3 cmd <- 02
[DEBUG]  PCI: 00:16.0 subsystem <- 8086/a360
[DEBUG]  PCI: 00:16.0 cmd <- 02
[DEBUG]  PCI: 00:17.0 subsystem <- 8086/a352
[DEBUG]  PCI: 00:17.0 cmd <- 03
[DEBUG]  PCI: 00:19.2 subsystem <- 8086/a347
[DEBUG]  PCI: 00:19.2 cmd <- 02
[DEBUG]  PCI: 00:1c.0 bridge ctrl <- 0013
[DEBUG]  PCI: 00:1c.0 subsystem <- 8086/a33c
[DEBUG]  PCI: 00:1c.0 cmd <- 07
[DEBUG]  PCI: 00:1c.5 bridge ctrl <- 0013
[DEBUG]  PCI: 00:1c.5 subsystem <- 8086/a33d
[DEBUG]  PCI: 00:1c.5 cmd <- 07
[DEBUG]  PCI: 00:1c.6 bridge ctrl <- 0013
[DEBUG]  PCI: 00:1c.6 subsystem <- 8086/a33e
[DEBUG]  PCI: 00:1c.6 cmd <- 07
[DEBUG]  PCI: 00:1c.7 bridge ctrl <- 0013
[DEBUG]  PCI: 00:1c.7 subsystem <- 8086/a33f
[DEBUG]  PCI: 00:1c.7 cmd <- 07
[DEBUG]  PCI: 00:1d.0 bridge ctrl <- 0013
[DEBUG]  PCI: 00:1d.0 subsystem <- 8086/a335
[DEBUG]  PCI: 00:1d.0 cmd <- 07
[DEBUG]  PCI: 00:1d.6 bridge ctrl <- 001b
[DEBUG]  PCI: 00:1d.6 subsystem <- 8086/a336
[DEBUG]  PCI: 00:1d.6 cmd <- 07
[DEBUG]  PCI: 00:1e.0 subsystem <- 8086/a328
[DEBUG]  PCI: 00:1e.0 cmd <- 06
[DEBUG]  PCI: 00:1e.1 subsystem <- 8086/a329
[DEBUG]  PCI: 00:1e.1 cmd <- 02
[DEBUG]  PCI: 00:1f.0 subsystem <- 8086/a309
[DEBUG]  PCI: 00:1f.0 cmd <- 07
[DEBUG]  PCI: 00:1f.3 subsystem <- 8086/a348
[DEBUG]  PCI: 00:1f.3 cmd <- 02
[DEBUG]  PCI: 00:1f.4 subsystem <- 8086/a323
[DEBUG]  PCI: 00:1f.4 cmd <- 03
[DEBUG]  PCI: 00:1f.5 cmd <- 406
[DEBUG]  PCI: 01:00.0 subsystem <- 8086/1539
[DEBUG]  PCI: 01:00.0 cmd <- 03
[DEBUG]  PCI: 02:00.0 subsystem <- 8086/1539
[DEBUG]  PCI: 02:00.0 cmd <- 03
[DEBUG]  PCI: 03:00.0 subsystem <- 8086/1539
[DEBUG]  PCI: 03:00.0 cmd <- 03
[DEBUG]  PCI: 04:00.0 subsystem <- 8086/1539
[DEBUG]  PCI: 04:00.0 cmd <- 03
[DEBUG]  PCI: 05:00.0 subsystem <- 8086/157c
[DEBUG]  PCI: 05:00.0 cmd <- 03
[DEBUG]  PCI: 06:00.0 bridge ctrl <- 001b
[DEBUG]  PCI: 06:00.0 cmd <- 07
[DEBUG]  PCI: 07:00.0 cmd <- 03
[INFO ]  done.
[DEBUG]  BS: BS_DEV_ENABLE run times (exec / console): 0 / 296 ms
[INFO ]  POST: 0x00
[DEBUG]  ME: Version: 12.0.81.1753
[DEBUG]  BS: BS_DEV_ENABLE exit times (exec / console): 8 / 7 ms
[INFO ]  Found TPM ST33ZP24 by ST Microelectronics
[INFO ]  tlcl_send_startup: Startup return code is 0
[INFO ]  TPM: setup succeeded
[DEBUG]  BS: BS_DEV_INIT entry times (exec / console): 7 / 15 ms
[INFO ]  POST: 0x75
[INFO ]  Initializing devices...
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:00.0 init
[INFO ]  CPU TDP = 80 Watts
[INFO ]  CPU PL1 = 80 Watts
[INFO ]  CPU PL2 = 100 Watts
[DEBUG]  PCI: 00:00.0 init finished in 11 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:02.0 init
[INFO ]  GMA: Found VBT in CBFS
[INFO ]  GMA: Found valid VBT in CBFS
[ALERT]  Graphics hand-off block not found
[DEBUG]  PCI: 00:02.0 init finished in 14 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:08.0 init
[DEBUG]  PCI: 00:08.0 init finished in 0 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:12.0 init
[DEBUG]  PCI: 00:12.0 init finished in 0 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:14.0 init
[DEBUG]  PCI: 00:14.0 init finished in 0 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:14.2 init
[DEBUG]  PCI: 00:14.2 init finished in 0 msecs
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:16.0 init
[DEBUG]  PCI: 00:16.0 init finished in 0 msecs
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:1c.0 init
[DEBUG]  Initializing PCH PCIe bridge.
[DEBUG]  PCI: 00:1c.0 init finished in 4 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:1c.5 init
[DEBUG]  Initializing PCH PCIe bridge.
[DEBUG]  PCI: 00:1c.5 init finished in 4 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:1c.6 init
[DEBUG]  Initializing PCH PCIe bridge.
[DEBUG]  PCI: 00:1c.6 init finished in 4 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:1c.7 init
[DEBUG]  Initializing PCH PCIe bridge.
[DEBUG]  PCI: 00:1c.7 init finished in 4 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:1d.0 init
[DEBUG]  Initializing PCH PCIe bridge.
[DEBUG]  PCI: 00:1d.0 init finished in 4 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:1d.6 init
[DEBUG]  Initializing PCH PCIe bridge.
[DEBUG]  PCI: 00:1d.6 init finished in 4 msecs
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:1f.0 init
[DEBUG]  IOAPIC: Initializing IOAPIC at 0xfec00000
[DEBUG]  IOAPIC: ID = 0x02
[DEBUG]  IOAPIC: 120 interrupts
[DEBUG]  IOAPIC: Clearing IOAPIC at 0xfec00000
[DEBUG]  IOAPIC: Bootstrap Processor Local APIC = 0x00
[DEBUG]  PCI: 00:1f.0 init finished in 25 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:1f.2 init
[DEBUG]  apm_control: Disabling ACPI.
[DEBUG]  APMC done.
[DEBUG]  PCI: 00:1f.2 init finished in 7 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:1f.3 init
[DEBUG]  azalia_audio: base = 0x8fe14000
[DEBUG]  azalia_audio: codec_mask = 05
[DEBUG]  azalia_audio: Initializing codec #2
[DEBUG]  azalia_audio: codec viddid: 8086280b
[DEBUG]  azalia_audio: verb_size: 20
[DEBUG]  azalia_audio: verb loaded.
[DEBUG]  azalia_audio: Initializing codec #0
[DEBUG]  azalia_audio: codec viddid: 10ec0888
[DEBUG]  azalia_audio: verb_size: 60
[DEBUG]  azalia_audio: verb loaded.
[DEBUG]  CFG EEPROM: HSI 0x3
[DEBUG]  PCI: 00:1f.3 init finished in 59 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 00:1f.4 init
[DEBUG]  PCI: 00:1f.4 init finished in 0 msecs
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[DEBUG]  PCI: 01:00.0 init
[DEBUG]  PCI: 01:00.0 init finished in 0 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 02:00.0 init
[DEBUG]  PCI: 02:00.0 init finished in 0 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 03:00.0 init
[DEBUG]  PCI: 03:00.0 init finished in 0 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 04:00.0 init
[DEBUG]  PCI: 04:00.0 init finished in 0 msecs
[INFO ]  POST: 0x75
[DEBUG]  PCI: 05:00.0 init
[DEBUG]  PCI: 05:00.0 init finished in 0 msecs
[INFO ]  POST: 0x75
[INFO ]  POST: 0x75
[DEBUG]  PCI: 07:00.0 init
[INFO ]  ASpeed AST2050: initializing video device
[INFO ]  ast_detect_chip: VGA not enabled on entry, requesting chip POST
[INFO ]  ast_detect_config_mode: P2A bridge disabled, using default configuration
[INFO ]  ast_detect_chip: AST 2500 detected
[INFO ]  ast_detect_chip: Analog VGA only
[INFO ]  ast_driver_load: dram MCLK=800 Mhz type=1 bus_width=16 size=04000000
[ERROR]  No header found
[INFO ]  ast_select_mode: Failed to decode EDID
[DEBUG]  Assuming VGA for KVM
[DEBUG]  AST: Display has 1024px x 768px
[DEBUG]  Using framebuffer 1024px x 768px pitch 4096 @ 32 BPP
[INFO ]  framebuffer_info: bytes_per_line: 4096, bits_per_pixel: 32
[INFO ]                     x_res x y_res: 1024 x 768, size: 3145728 at 0xa0000000
[INFO ]  ASpeed high resolution framebuffer initialized
[DEBUG]  PCI: 07:00.0 init finished in 192 msecs
[INFO ]  POST: 0x75
[INFO ]  Devices initialized
[DEBUG]  BS: BS_DEV_INIT run times (exec / console): 115 / 556 ms
[DEBUG]  FMAP: area SMMSTORE found @ 1710000 (262144 bytes)
[INFO ]  SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
[DEBUG]  smm store: 4 # blocks with size 0x10000
[INFO ]  SMMSTORE: Setting up SMI handler
[DEBUG]  BS: BS_DEV_INIT exit times (exec / console): 0 / 25 ms
[INFO ]  POST: 0x76
[INFO ]  Finalize devices...
[DEBUG]  Root Device final
[INFO ]  MB: Collecting Board Layout information
[DEBUG]  BOARD LAYOUT:
[DEBUG]   Signature : 0xd59bbd10
[DEBUG]   CPU name  : Intel(R) Xeon(R) E-2226GE CPU @ 3.40GHz
[DEBUG]   CPU count : 6
[DEBUG]   CPU freq  : 3400
[DEBUG]   PCH name  : Cannonlake-H C246
[DEBUG]   DRAM SIZE : 16384
[DEBUG]   DRAM SIZE : 16384
[DEBUG]   DRAM SIZE : 16384
[DEBUG]   DRAM SIZE : 16384
[DEBUG]  CFG EEPROM: Board Layout up to date
[DEBUG]  PCI: 00:02.0 final
[DEBUG]  PCI: 00:16.0 final
[DEBUG]  PCI: 00:17.0 final
[DEBUG]  PCI: 00:1f.2 final
[DEBUG]  PCI: 00:1f.4 final
[INFO ]  Devices finalized
[DEBUG]  BS: BS_POST_DEVICE run times (exec / console): 218 / 82 ms
[INFO ]  POST: 0x77
[DEBUG]  BS: BS_OS_RESUME_CHECK run times (exec / console): 0 / 3 ms
[DEBUG]  ME: HFSTS1                  : 0x90000255
[DEBUG]  ME: HFSTS2                  : 0x30850106
[DEBUG]  ME: HFSTS3                  : 0x00000020
[DEBUG]  ME: HFSTS4                  : 0x00004000
[DEBUG]  ME: HFSTS5                  : 0x00000000
[DEBUG]  ME: HFSTS6                  : 0x00000000
[DEBUG]  ME: Manufacturing Mode      : YES
[DEBUG]  ME: FW Partition Table      : OK
[DEBUG]  ME: Bringup Loader Failure  : NO
[DEBUG]  ME: Firmware Init Complete  : YES
[DEBUG]  ME: Boot Options Present    : NO
[DEBUG]  ME: Update In Progress      : NO
[DEBUG]  ME: D0i3 Support            : YES
[DEBUG]  ME: Low Power State Enabled : NO
[DEBUG]  ME: CPU Replaced            : NO
[DEBUG]  ME: CPU Replacement Valid   : YES
[DEBUG]  ME: Current Working State   : 5
[DEBUG]  ME: Current Operation State : 1
[DEBUG]  ME: Current Operation Mode  : 0
[DEBUG]  ME: Error Code              : 0
[DEBUG]  ME: CPU Debug Disabled      : NO
[DEBUG]  ME: TXT Support             : NO
[DEBUG]  BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 114 ms
[INFO ]  POST: 0x79
[INFO ]  POST: 0x9c
[INFO ]  CBFS: Found 'fallback/dsdt.aml' @0x950c0 size 0x1e33 in mcache @0x89ced1c8
[WARN ]  CBFS: 'fallback/slic' not found.
[INFO ]  ACPI: Writing ACPI tables at 89bdc000.
[DEBUG]  ACPI:    * FACS
[DEBUG]  ACPI:    * DSDT
[DEBUG]  ACPI:    * FADT
[DEBUG]  SCI is IRQ9
[DEBUG]  ACPI: added table 1/32, length now 40
[DEBUG]  ACPI:     * SSDT
[DEBUG]  Found 1 CPU(s) with 6/6 physical/logical core(s) each.
[DEBUG]  PSS: 3401MHz power 80000 control 0x2e00 status 0x2e00
[DEBUG]  PSS: 3400MHz power 80000 control 0x2200 status 0x2200
[DEBUG]  PSS: 3300MHz power 76668 control 0x2100 status 0x2100
[DEBUG]  PSS: 2800MHz power 61362 control 0x1c00 status 0x1c00
[DEBUG]  PSS: 2300MHz power 47482 control 0x1700 status 0x1700
[DEBUG]  PSS: 1800MHz power 34956 control 0x1200 status 0x1200
[DEBUG]  PSS: 1300MHz power 23684 control 0xd00 status 0xd00
[DEBUG]  PSS: 800MHz power 13648 control 0x800 status 0x800
[DEBUG]  PSS: 3401MHz power 80000 control 0x2e00 status 0x2e00
[DEBUG]  PSS: 3400MHz power 80000 control 0x2200 status 0x2200
[DEBUG]  PSS: 3300MHz power 76668 control 0x2100 status 0x2100
[DEBUG]  PSS: 2800MHz power 61362 control 0x1c00 status 0x1c00
[DEBUG]  PSS: 2300MHz power 47482 control 0x1700 status 0x1700
[DEBUG]  PSS: 1800MHz power 34956 control 0x1200 status 0x1200
[DEBUG]  PSS: 1300MHz power 23684 control 0xd00 status 0xd00
[DEBUG]  PSS: 800MHz power 13648 control 0x800 status 0x800
[DEBUG]  PSS: 3401MHz power 80000 control 0x2e00 status 0x2e00
[DEBUG]  PSS: 3400MHz power 80000 control 0x2200 status 0x2200
[DEBUG]  PSS: 3300MHz power 76668 control 0x2100 status 0x2100
[DEBUG]  PSS: 2800MHz power 61362 control 0x1c00 status 0x1c00
[DEBUG]  PSS: 2300MHz power 47482 control 0x1700 status 0x1700
[DEBUG]  PSS: 1800MHz power 34956 control 0x1200 status 0x1200
[DEBUG]  PSS: 1300MHz power 23684 control 0xd00 status 0xd00
[DEBUG]  PSS: 800MHz power 13648 control 0x800 status 0x800
[DEBUG]  PSS: 3401MHz power 80000 control 0x2e00 status 0x2e00
[DEBUG]  PSS: 3400MHz power 80000 control 0x2200 status 0x2200
[DEBUG]  PSS: 3300MHz power 76668 control 0x2100 status 0x2100
[DEBUG]  PSS: 2800MHz power 61362 control 0x1c00 status 0x1c00
[DEBUG]  PSS: 2300MHz power 47482 control 0x1700 status 0x1700
[DEBUG]  PSS: 1800MHz power 34956 control 0x1200 status 0x1200
[DEBUG]  PSS: 1300MHz power 23684 control 0xd00 status 0xd00
[DEBUG]  PSS: 800MHz power 13648 control 0x800 status 0x800
[DEBUG]  PSS: 3401MHz power 80000 control 0x2e00 status 0x2e00
[DEBUG]  PSS: 3400MHz power 80000 control 0x2200 status 0x2200
[DEBUG]  PSS: 3300MHz power 76668 control 0x2100 status 0x2100
[DEBUG]  PSS: 2800MHz power 61362 control 0x1c00 status 0x1c00
[DEBUG]  PSS: 2300MHz power 47482 control 0x1700 status 0x1700
[DEBUG]  PSS: 1800MHz power 34956 control 0x1200 status 0x1200
[DEBUG]  PSS: 1300MHz power 23684 control 0xd00 status 0xd00
[DEBUG]  PSS: 800MHz power 13648 control 0x800 status 0x800
[DEBUG]  PSS: 3401MHz power 80000 control 0x2e00 status 0x2e00
[DEBUG]  PSS: 3400MHz power 80000 control 0x2200 status 0x2200
[DEBUG]  PSS: 3300MHz power 76668 control 0x2100 status 0x2100
[DEBUG]  PSS: 2800MHz power 61362 control 0x1c00 status 0x1c00
[DEBUG]  PSS: 2300MHz power 47482 control 0x1700 status 0x1700
[DEBUG]  PSS: 1800MHz power 34956 control 0x1200 status 0x1200
[DEBUG]  PSS: 1300MHz power 23684 control 0xd00 status 0xd00
[DEBUG]  PSS: 800MHz power 13648 control 0x800 status 0x800
[DEBUG]  PCI space above 4GB MMIO is at 0x106e800000, len = 0x6f91800000
[INFO ]  Returning default LPI constraint package
[INFO ]  \_SB.PCI0.PEPD: Intel Power Engine Plug-in
[INFO ]  \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
[INFO ]  \_SB_.PCI0.TPM: LPC TPM PNP: 0c31.0
[DEBUG]  ACPI: added table 2/32, length now 44
[DEBUG]  ACPI:    * MCFG
[DEBUG]  ACPI: added table 3/32, length now 48
[DEBUG]  ACPI:    * TPM2
[DEBUG]  TPM2 log created at 0x89bcc000
[DEBUG]  ACPI: added table 4/32, length now 52
[DEBUG]  ACPI:     * LPIT
[DEBUG]  ACPI: added table 5/32, length now 56
[DEBUG]  ACPI:    * MADT
[DEBUG]  SCI is IRQ9
[DEBUG]  ACPI: added table 6/32, length now 60
[DEBUG]  current = 89bdfee0
[DEBUG]  ACPI:    * DMAR
[DEBUG]  ACPI: added table 7/32, length now 64
[DEBUG]  ACPI: added table 8/32, length now 68
[DEBUG]  ACPI:    * HPET
[DEBUG]  ACPI: added table 9/32, length now 72
[INFO ]  ACPI: done.
[DEBUG]  ACPI tables: 16416 bytes.
[DEBUG]  smbios_write_tables: 89bc4000
[DEBUG]  SMBIOS firmware version is set to coreboot_version: '4.18-48-g881ce1bd97'
[DEBUG]  CFG EEPROM: HSI 0x3
[DEBUG]  CFG EEPROM: HSI 0x3
[INFO ]  Create SMBIOS type 16
[INFO ]  Create SMBIOS type 17
[INFO ]  Create SMBIOS type 20
[INFO ]  GENERIC: 0.0 (WIFI Device)
[DEBUG]  SMBIOS tables: 1689 bytes.
[DEBUG]  Writing table forward entry at 0x00000500
[DEBUG]  Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 761e
[DEBUG]  Writing coreboot table at 0x89c00000
[DEBUG]   0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
[DEBUG]   1. 0000000000001000-000000000009ffff: RAM
[DEBUG]   2. 00000000000a0000-00000000000fffff: RESERVED
[DEBUG]   3. 0000000000100000-0000000089bc3fff: RAM
[DEBUG]   4. 0000000089bc4000-0000000089c61fff: CONFIGURATION TABLES
[DEBUG]   5. 0000000089c62000-0000000089cddfff: RAMSTAGE
[DEBUG]   6. 0000000089cde000-0000000089ffffff: CONFIGURATION TABLES
[DEBUG]   7. 000000008a000000-000000008f7fffff: RESERVED
[DEBUG]   8. 000000008fe20000-000000008fe20fff: RESERVED
[DEBUG]   9. 00000000e0000000-00000000efffffff: RESERVED
[DEBUG]  10. 00000000fc000000-00000000fc000fff: RESERVED
[DEBUG]  11. 00000000fe000000-00000000fe00ffff: RESERVED
[DEBUG]  12. 00000000fed10000-00000000fed17fff: RESERVED
[DEBUG]  13. 00000000fed40000-00000000fed44fff: RESERVED
[DEBUG]  14. 00000000fed80000-00000000fed83fff: RESERVED
[DEBUG]  15. 00000000fed90000-00000000fed91fff: RESERVED
[DEBUG]  16. 00000000feda0000-00000000feda1fff: RESERVED
[DEBUG]  17. 00000000ff000000-00000000ffffffff: RESERVED
[DEBUG]  18. 0000000100000000-000000106e7fffff: RAM
[DEBUG]  Wrote coreboot table at: 0x89c00000, 0x540 bytes, checksum 92ac
[DEBUG]  coreboot table: 1368 bytes.
[DEBUG]  IMD ROOT    0. 0x89fff000 0x00001000
[DEBUG]  IMD SMALL   1. 0x89ffe000 0x00001000
[DEBUG]  FSP MEMORY  2. 0x89d0e000 0x002f0000
[DEBUG]  CONSOLE     3. 0x89cee000 0x00020000
[DEBUG]  RO MCACHE   4. 0x89ced000 0x00000388
[DEBUG]  TIME STAMP  5. 0x89cec000 0x00000910
[DEBUG]  MEM INFO    6. 0x89ceb000 0x00000768
[DEBUG]  AFTER CAR   7. 0x89cde000 0x0000d000
[DEBUG]  RAMSTAGE    8. 0x89c61000 0x0007d000
[DEBUG]  REFCODE     9. 0x89c2c000 0x00035000
[DEBUG]  SMM BACKUP 10. 0x89c1c000 0x00010000
[DEBUG]  IGD OPREGION11. 0x89c18000 0x000031a5
[DEBUG]  SMM COMBUFFER12. 0x89c08000 0x00010000
[DEBUG]  COREBOOT   13. 0x89c00000 0x00008000
[DEBUG]  ACPI       14. 0x89bdc000 0x00024000
[DEBUG]  TPM2 TCGLOG15. 0x89bcc000 0x00010000
[DEBUG]  SMBIOS     16. 0x89bc4000 0x00008000
[DEBUG]  IMD small region:
[DEBUG]    IMD ROOT    0. 0x89ffec00 0x00000400
[DEBUG]    FSP RUNTIME 1. 0x89ffebe0 0x00000004
[DEBUG]    FMAP        2. 0x89ffeac0 0x0000010a
[DEBUG]    POWER STATE 3. 0x89ffea60 0x00000044
[DEBUG]    ROMSTAGE    4. 0x89ffea40 0x00000004
[DEBUG]    ROMSTG STCK 5. 0x89ffe980 0x000000a8
[DEBUG]    ACPI GNVS   6. 0x89ffe940 0x00000038
[DEBUG]  BS: BS_WRITE_TABLES run times (exec / console): 49 / 830 ms
[DEBUG]  MTRR: Physical address space:
[DEBUG]  0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
[DEBUG]  0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
[DEBUG]  0x00000000000c0000 - 0x000000008f7fffff size 0x8f740000 type 6
[DEBUG]  0x000000008f800000 - 0x00000000ffffffff size 0x70800000 type 0
[DEBUG]  0x0000000100000000 - 0x000000106e7fffff size 0xf6e800000 type 6
[DEBUG]  MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG]  MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG]  CPU physical address size: 39 bits
[DEBUG]  MTRR: default type WB/UC MTRR counts: 4/8.
[DEBUG]  MTRR: WB selected as default type.
[DEBUG]  MTRR: 0 base 0x000000008f800000 mask 0x0000007fff800000 type 0
[DEBUG]  MTRR: 1 base 0x0000000090000000 mask 0x0000007ff0000000 type 0
[DEBUG]  MTRR: 2 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
[DEBUG]  MTRR: 3 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0
[DEBUG]  MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG]  MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG]  MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG]  CPU physical address size: 39 bits
[DEBUG]  MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG]  CPU physical address size: 39 bits
[DEBUG]  MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG]  MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG]  MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG]  CPU physical address size: 39 bits
[DEBUG]  MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG]  CPU physical address size: 39 bits
[DEBUG]  MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG]  MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26f 0x0606060606060606
[DEBUG]  CPU physical address size: 39 bits
[DEBUG]  MTRR: TEMPORARY Physical address space:
[DEBUG]  0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6
[DEBUG]  0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0
[DEBUG]  0x00000000000c0000 - 0x000000008f7fffff size 0x8f740000 type 6
[DEBUG]  0x000000008f800000 - 0x00000000feffffff size 0x6f800000 type 0
[DEBUG]  0x00000000ff000000 - 0x00000000ffffffff size 0x01000000 type 5
[DEBUG]  0x0000000100000000 - 0x000000106e7fffff size 0xf6e800000 type 6
[DEBUG]  MTRR: default type WB/UC MTRR counts: 10/9.
[DEBUG]  MTRR: UC selected as default type.
[DEBUG]  MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
[DEBUG]  MTRR: 1 base 0x0000000080000000 mask 0x0000007ff0000000 type 6
[DEBUG]  MTRR: 2 base 0x000000008f800000 mask 0x0000007fff800000 type 0
[DEBUG]  MTRR: 3 base 0x00000000ff000000 mask 0x0000007fff000000 type 5
[DEBUG]  MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
[DEBUG]  MTRR: 5 base 0x0000000200000000 mask 0x0000007e00000000 type 6
[DEBUG]  MTRR: 6 base 0x0000000400000000 mask 0x0000007c00000000 type 6
[DEBUG]  MTRR: 7 base 0x0000000800000000 mask 0x0000007800000000 type 6
[DEBUG]  MTRR: 8 base 0x0000001000000000 mask 0x0000007f80000000 type 6

[DEBUG]  MTRR check
[DEBUG]  Fixed MTRRs   : Enabled
[DEBUG]  Variable MTRRs: Enabled

[INFO ]  POST: 0x93
[DEBUG]  BS: BS_WRITE_TABLES exit times (exec / console): 311 / 305 ms
[INFO ]  POST: 0x7a
[INFO ]  CBFS: Found 'fallback/payload' @0x151500 size 0x1e4f90 in mcache @0x89ced318
[DEBUG]  Checking segment from ROM address 0xff8a172c
[DEBUG]  Checking segment from ROM address 0xff8a1748
[DEBUG]  Loading segment from ROM address 0xff8a172c
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x00800000 memsize 0x1000000 srcaddr 0xff8a1764 filesize 0x1e4f58
[DEBUG]  Loading Segment: addr: 0x00800000 memsz: 0x0000000001000000 filesz: 0x00000000001e4f58
[DEBUG]  using LZMA
[DEBUG]  Loading segment from ROM address 0xff8a1748
[DEBUG]    Entry Point 0x00805420
[DEBUG]  BS: BS_PAYLOAD_LOAD run times (exec / console): 1090 / 68 ms
[INFO ]  POST: 0x95
[INFO ]  POST: 0xa3
[INFO ]  POST: 0x88
[INFO ]  POST: 0x89
[DEBUG]  Finalizing chipset.
[DEBUG]  apm_control: Finalizing SMM.
[DEBUG]  APMC done.
[INFO ]  POST: 0xfe
[DEBUG]  BS: BS_PAYLOAD_LOAD exit times (exec / console): 9 / 25 ms
[DEBUG]  BS: BS_PAYLOAD_BOOT entry times (exec / console): 1 / 0 ms
[INFO ]  POST: 0x7b
[DEBUG]  mp_park_aps done after 0 msecs.
[DEBUG]  Jumping to boot code at 0x00805420(0x89c00000)
[INFO ]  POST: 0xf8