Nick: heijligen E-mail: none Board: unknown Contents: [NOTE ] coreboot-4.17-1747-gd91f3a4eaf Wed Oct 12 16:55:58 UTC 2022 bootblock starting (log level: 7)... [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x300000. [DEBUG] FMAP: base = 0xffc00000 size = 0x400000 #areas = 3 [DEBUG] FMAP: area COREBOOT found @ 300200 (1048064 bytes) [INFO ] CBFS: mcache @0xfefc2e00 built for 15 files, used 0x31c of 0x4000 bytes [WARN ] CBFS: 'coreboot-stages' not found. [INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0xc7a8 in mcache @0xfefc2e2c [DEBUG] BS: bootblock times (exec / console): total (unknown) / 50 ms [DEBUG] PROG_RUN: Setting MTRR to cache XIP stage. base: 0xfff00000, size: 0x00010000 [NOTE ] coreboot-4.17-1747-gd91f3a4eaf Wed Oct 12 16:55:58 UTC 2022 romstage starting (log level: 7)... [DEBUG] SMBus controller enabled [DEBUG] Setting up static southbridge registers... done. [DEBUG] Disabling Watchdog reboot... done. [INFO ] Mobile Intel(R) 82945GM/GME Express Chipset [DEBUG] (G)MCH capable of up to FSB 800 MHz [DEBUG] (G)MCH capable of up to DDR2-667 [DEBUG] Setting up static northbridge registers... done. [DEBUG] Waiting for MCHBAR to come up...ok [DEBUG] Setting up RAM controller. [DEBUG] This mainboard supports Dual Channel Operation. [DEBUG] Reading SPD using i2c block operation. [DEBUG] DDR II Channel 0 Socket 0: x8DDS [DEBUG] DIMM 0 side 0 = 1024 MB [DEBUG] DIMM 0 side 1 = 1024 MB [DEBUG] DDR II Channel 0 Socket 1: N/A [DEBUG] Reading SPD using i2c block operation. [DEBUG] DDR II Channel 1 Socket 0: x8DDS [DEBUG] DIMM 2 side 0 = 1024 MB [DEBUG] DIMM 2 side 1 = 1024 MB [DEBUG] DDR II Channel 1 Socket 1: N/A [DEBUG] Memory will be driven at 667MT with CAS=5 clocks [DEBUG] tRAS = 15 cycles [DEBUG] tRP = 5 cycles [DEBUG] tRCD = 5 cycles [DEBUG] tWR = 5 cycles [DEBUG] tRFC = 43 cycles [DEBUG] Refresh: 7.8us [DEBUG] SLP S4# Assertion Width Violation. [DEBUG] Reset required. [INFO ] full_reset() called! [NOTE ] coreboot-4.17-1747-gd91f3a4eaf Wed Oct 12 16:55:58 UTC 2022 bootblock starting (log level: 7)... [DEBUG] FMAP: Found "FLASH" version 1.1 at 0x300000. [DEBUG] FMAP: base = 0xffc00000 size = 0x400000 #areas = 3 [DEBUG] FMAP: area COREBOOT found @ 300200 (1048064 bytes) [INFO ] CBFS: mcache @0xfefc2e00 built for 15 files, used 0x31c of 0x4000 bytes [WARN ] CBFS: 'coreboot-stages' not found. [INFO ] CBFS: Found 'fallback/romstage' @0x80 size 0xc7a8 in mcache @0xfefc2e2c [DEBUG] BS: bootblock times (exec / console): total (unknown) / 50 ms [DEBUG] PROG_RUN: Setting MTRR to cache XIP stage. base: 0xfff00000, size: 0x00010000 [NOTE ] coreboot-4.17-1747-gd91f3a4eaf Wed Oct 12 16:55:58 UTC 2022 romstage starting (log level: 7)... [DEBUG] SMBus controller enabled [DEBUG] Setting up static southbridge registers... done. [DEBUG] Disabling Watchdog reboot... done. [INFO ] Mobile Intel(R) 82945GM/GME Express Chipset [DEBUG] (G)MCH capable of up to FSB 800 MHz [DEBUG] (G)MCH capable of up to DDR2-667 [DEBUG] Setting up static northbridge registers... done. [DEBUG] Waiting for MCHBAR to come up...ok [DEBUG] Setting up RAM controller. [DEBUG] This mainboard supports Dual Channel Operation. [DEBUG] Reading SPD using i2c block operation. [DEBUG] DDR II Channel 0 Socket 0: x8DDS [DEBUG] DIMM 0 side 0 = 1024 MB [DEBUG] DIMM 0 side 1 = 1024 MB [DEBUG] DDR II Channel 0 Socket 1: N/A [DEBUG] Reading SPD using i2c block operation. [DEBUG] DDR II Channel 1 Socket 0: x8DDS [DEBUG] DIMM 2 side 0 = 1024 MB [DEBUG] DIMM 2 side 1 = 1024 MB [DEBUG] DDR II Channel 1 Socket 1: N/A [DEBUG] Memory will be driven at 667MT with CAS=5 clocks [DEBUG] tRAS = 15 cycles [DEBUG] tRP = 5 cycles [DEBUG] tRCD = 5 cycles [DEBUG] tWR = 5 cycles [DEBUG] tRFC = 43 cycles [DEBUG] Refresh: 7.8us [DEBUG] Setting Graphics Frequency... [DEBUG] FSB: 667 MHz Voltage: 1.05V Render: 250MHz Display: 200MHz [DEBUG] Setting Memory Frequency... CLKCFG = 0x00010023, CLKCFG = 0x00010043, ok [DEBUG] Setting mode of operation for memory channels...Dual Channel Interleaved. [DEBUG] Programming Clock Crossing...MEM=667 FSB=667... ok [DEBUG] Setting RAM size... [DEBUG] C0DRB = 0x40404020 [DEBUG] C1DRB = 0x40404020 [DEBUG] TOLUD = 0x00d0 [DEBUG] Setting row attributes... [DEBUG] C0DRA = 0x0033 [DEBUG] C1DRA = 0x0033 [DEBUG] one dimm per channel config.. [DEBUG] Initializing System Memory IO... [DEBUG] Programming Dual Channel RCOMP [DEBUG] Table Index: 18 [DEBUG] Programming DLL Timings... [DEBUG] Enabling System Memory IO... [DEBUG] jedec enable sequence: bank 0 [DEBUG] jedec enable sequence: bank 1 [DEBUG] bankaddr from bank size of rank 0 [DEBUG] jedec enable sequence: bank 4 [DEBUG] jedec enable sequence: bank 5 [DEBUG] bankaddr from bank size of rank 4 [DEBUG] RAM initialization finished. [DEBUG] Setting up Egress Port RCRB [DEBUG] Loading port arbitration table ...ok [DEBUG] Wait for VC1 negotiation ...ok [DEBUG] Setting up DMI RCRB [DEBUG] Wait for VC1 negotiation ...done.. [DEBUG] Internal graphics: enabled [DEBUG] Waiting for DMI hardware...ok [DEBUG] Enabling PCI Express x16 Link [DEBUG] SLOTSTS: 0000 [DEBUG] Disabling PCI Express x16 Link [DEBUG] Wait for link to enter detect state... ok [DEBUG] Setting up Root Complex Topology [DEBUG] CBMEM: [DEBUG] IMD: root @ 0xcf3ff000 254 entries. [DEBUG] IMD: root @ 0xcf3fec00 62 entries. [DEBUG] FMAP: area COREBOOT found @ 300200 (1048064 bytes) [DEBUG] External stage cache: [DEBUG] IMD: root @ 0xcf7ff000 254 entries. [DEBUG] IMD: root @ 0xcf7fec00 62 entries. [DEBUG] SMM Memory Map [DEBUG] SMRAM : 0xcf600000 0x200000 [DEBUG] Subregion 0: 0xcf600000 0x100000 [DEBUG] Subregion 1: 0xcf700000 0x100000 [DEBUG] Subregion 2: 0xcf800000 0x0 [DEBUG] Normal boot [INFO ] CBFS: Found 'fallback/postcar' @0x3b2c0 size 0x5bbc in mcache @0xfefc2fec [DEBUG] Loading module at 0xcf3d0000 with entry 0xcf3d0031. filesize: 0x57e0 memsize: 0xbb18 [DEBUG] Processing 231 relocs. Offset value of 0xcd3d0000 [DEBUG] BS: romstage times (exec / console): total (unknown) / 358 ms [NOTE ] coreboot-4.17-1747-gd91f3a4eaf Wed Oct 12 16:55:58 UTC 2022 postcar starting (log level: 7)... [DEBUG] Normal boot [DEBUG] FMAP: area COREBOOT found @ 300200 (1048064 bytes) [INFO ] CBFS: Found 'fallback/ramstage' @0x24900 size 0x13738 in mcache @0xcf3dd0dc [DEBUG] Loading module at 0xcf391000 with entry 0xcf391000. filesize: 0x26970 memsize: 0x3d5d0 [DEBUG] Processing 2893 relocs. Offset value of 0xcb391000 [DEBUG] BS: postcar times (exec / console): total (unknown) / 42 ms [NOTE ] coreboot-4.17-1747-gd91f3a4eaf Wed Oct 12 16:55:58 UTC 2022 ramstage starting (log level: 7)... [DEBUG] Normal boot [INFO ] Enumerating buses... [DEBUG] Root Device scanning... [DEBUG] CPU_CLUSTER: 0 enabled [DEBUG] DOMAIN: 0000 enabled [DEBUG] DOMAIN: 0000 scanning... [DEBUG] PCI: pci_scan_bus for bus 00 [DEBUG] PCI: 00:00.0 [8086/27ac] enabled [DEBUG] PCI: 00:02.0 [8086/27ae] enabled [DEBUG] PCI: 00:02.1 [8086/27a6] enabled [DEBUG] PCI: 00:1b.0 [8086/27d8] enabled [DEBUG] PCI: 00:1c.0 [8086/27d0] enabled [DEBUG] PCI: 00:1c.1 [8086/27d2] enabled [DEBUG] PCI: 00:1c.2 [8086/27d4] enabled [DEBUG] PCI: 00:1c.3: Disabling device [DEBUG] PCI: 00:1c.3 [8086/27d6] disabled [DEBUG] PCI: 00:1c.4: Disabling device [DEBUG] PCI: 00:1c.4 [8086/27e0] disabled [DEBUG] PCI: 00:1c.5: Disabling device [DEBUG] PCI: 00:1c.3: Disabling device [DEBUG] PCI: 00:1c.3: Disabling device [DEBUG] PCI: 00:1c.4: Disabling device [DEBUG] PCI: 00:1c.4: Disabling device [DEBUG] PCI: 00:1c.5: Disabling device [DEBUG] PCI: 00:1c.5: Disabling device [DEBUG] PCI: 00:1c.5 [8086/27e2] disabled [DEBUG] PCI: 00:1d.0 [8086/27c8] enabled [DEBUG] PCI: 00:1d.1 [8086/27c9] enabled [DEBUG] PCI: 00:1d.2 [8086/27ca] enabled [DEBUG] PCI: 00:1d.3 [8086/27cb] enabled [DEBUG] PCI: 00:1d.7 [8086/27cc] enabled [DEBUG] PCI: 00:1e.0 [8086/244e] enabled [DEBUG] PCI: 00:1e.2: Disabling device [DEBUG] PCI: 00:1e.2: Disabling device [DEBUG] PCI: 00:1e.2 [8086/27de] disabled [DEBUG] PCI: 00:1e.3: Disabling device [DEBUG] PCI: 00:1e.3: Disabling device [DEBUG] PCI: 00:1e.3 [8086/27dd] disabled [DEBUG] PCI: 00:1f.0 [8086/27b8] enabled [DEBUG] PCI: 00:1f.1: Disabling device [DEBUG] PCI: 00:1f.1: Disabling device [DEBUG] PCI: 00:1f.1 [8086/27df] disabled [DEBUG] Set SATA mode early [DEBUG] Set SATA mode early [DEBUG] PCI: 00:1f.2 [8086/27c0] enabled [DEBUG] PCI: 00:1f.3 [8086/27da] enabled [WARN ] PCI: Leftover static devices: [WARN ] PCI: 00:01.0 [WARN ] PCI: Check your devicetree.cb. [DEBUG] PCI: 00:1c.0 scanning... [DEBUG] PCI: pci_scan_bus for bus 01 [DEBUG] PCI: 01:00.0 [10ec/8168] enabled [DEBUG] scan_bus: bus PCI: 00:1c.0 finished in 8 msecs [DEBUG] PCI: 00:1c.1 scanning... [DEBUG] PCI: pci_scan_bus for bus 02 [DEBUG] PCI: 02:00.0 [10ec/8168] enabled [DEBUG] scan_bus: bus PCI: 00:1c.1 finished in 8 msecs [DEBUG] PCI: 00:1c.2 scanning... [DEBUG] PCI: pci_scan_bus for bus 03 [DEBUG] PCI: 03:00.0 [10ec/8168] enabled [DEBUG] scan_bus: bus PCI: 00:1c.2 finished in 8 msecs [DEBUG] PCI: 00:1e.0 scanning... [DEBUG] PCI: pci_scan_bus for bus 04 [DEBUG] PCI: 04:00.0 [104c/8023] enabled [DEBUG] scan_bus: bus PCI: 00:1e.0 finished in 8 msecs [DEBUG] PCI: 00:1f.0 scanning... [DEBUG] PNP: 002e.0 disabled [DEBUG] PNP: 002e.1 enabled [DEBUG] PNP: 002e.2 enabled [DEBUG] PNP: 002e.3 enabled [DEBUG] PNP: 002e.5 enabled [DEBUG] PNP: 002e.7 enabled [DEBUG] PNP: 002e.8 enabled [DEBUG] PNP: 002e.9 enabled [DEBUG] PNP: 002e.a disabled [DEBUG] PNP: 002e.b enabled [DEBUG] PNP: 004e.0 disabled [DEBUG] PNP: 004e.1 disabled [DEBUG] PNP: 004e.2 enabled [DEBUG] PNP: 004e.3 enabled [DEBUG] PNP: 004e.5 disabled [DEBUG] PNP: 004e.7 disabled [DEBUG] PNP: 004e.8 disabled [DEBUG] PNP: 004e.9 disabled [DEBUG] PNP: 004e.a disabled [DEBUG] PNP: 004e.b disabled [DEBUG] scan_bus: bus PCI: 00:1f.0 finished in 65 msecs [DEBUG] PCI: 00:1f.3 scanning... [DEBUG] scan_bus: bus PCI: 00:1f.3 finished in 0 msecs [DEBUG] scan_bus: bus DOMAIN: 0000 finished in 335 msecs [DEBUG] scan_bus: bus Root Device finished in 351 msecs [INFO ] done [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 365 ms [DEBUG] found VGA at PCI: 00:02.0 [DEBUG] Setting up VGA for PCI: 00:02.0 [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device [INFO ] Allocating resources... [INFO ] Reading resources... [DEBUG] pci_tolm: 0xffffffff [DEBUG] IGD decoded, subtracting 8M UMA [DEBUG] TSEG decoded, subtracting 2M [DEBUG] Unused RAM between cbmem_top and TOM: 0x800K [INFO ] Available memory: 3395584K (3316M) [DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. [INFO ] Done reading resources. [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === [DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff [DEBUG] PCI: 01:00.0 10 * [0x0 - 0xff] io [DEBUG] PCI: 00:1c.0 io: size: 1000 align: 12 gran: 12 limit: ffff done [DEBUG] PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff [DEBUG] PCI: 01:00.0 30 * [0x0 - 0x1ffff] mem [DEBUG] PCI: 01:00.0 18 * [0x20000 - 0x20fff] mem [DEBUG] PCI: 00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done [DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff [DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done [DEBUG] PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff [DEBUG] PCI: 02:00.0 10 * [0x0 - 0xff] io [DEBUG] PCI: 00:1c.1 io: size: 1000 align: 12 gran: 12 limit: ffff done [DEBUG] PCI: 00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff [DEBUG] PCI: 02:00.0 30 * [0x0 - 0x1ffff] mem [DEBUG] PCI: 02:00.0 18 * [0x20000 - 0x20fff] mem [DEBUG] PCI: 00:1c.1 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done [DEBUG] PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff [DEBUG] PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done [DEBUG] PCI: 00:1c.2 io: size: 0 align: 12 gran: 12 limit: ffff [DEBUG] PCI: 03:00.0 10 * [0x0 - 0xff] io [DEBUG] PCI: 00:1c.2 io: size: 1000 align: 12 gran: 12 limit: ffff done [DEBUG] PCI: 00:1c.2 mem: size: 0 align: 20 gran: 20 limit: ffffffff [DEBUG] PCI: 03:00.0 30 * [0x0 - 0x1ffff] mem [DEBUG] PCI: 03:00.0 18 * [0x20000 - 0x20fff] mem [DEBUG] PCI: 00:1c.2 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done [DEBUG] PCI: 00:1c.2 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff [DEBUG] PCI: 00:1c.2 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done [DEBUG] PCI: 00:1e.0 io: size: 0 align: 12 gran: 12 limit: ffff [DEBUG] PCI: 00:1e.0 io: size: 0 align: 12 gran: 12 limit: ffff done [DEBUG] PCI: 00:1e.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff [DEBUG] PCI: 04:00.0 14 * [0x0 - 0x3fff] mem [DEBUG] PCI: 04:00.0 10 * [0x4000 - 0x47ff] mem [DEBUG] PCI: 00:1e.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done [DEBUG] PCI: 00:1e.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff [DEBUG] PCI: 00:1e.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff [DEBUG] update_constraints: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed) [DEBUG] update_constraints: PNP: 002e.1 60 base 00000378 limit 0000037f io (fixed) [DEBUG] update_constraints: PNP: 002e.2 60 base 000003f8 limit 000003ff io (fixed) [DEBUG] update_constraints: PNP: 002e.3 60 base 000002f8 limit 000002ff io (fixed) [DEBUG] update_constraints: PNP: 002e.5 60 base 00000060 limit 00000060 io (fixed) [DEBUG] update_constraints: PNP: 002e.5 62 base 00000064 limit 00000064 io (fixed) [DEBUG] update_constraints: PNP: 002e.7 60 base 00000220 limit 00000220 io (fixed) [DEBUG] update_constraints: PNP: 002e.7 62 base 00000330 limit 00000331 io (fixed) [DEBUG] update_constraints: PNP: 002e.b 60 base 00000a00 limit 00000a07 io (fixed) [DEBUG] update_constraints: PNP: 004e.2 60 base 000003e8 limit 000003ef io (fixed) [DEBUG] update_constraints: PNP: 004e.3 60 base 000002e8 limit 000002ef io (fixed) [DEBUG] update_constraints: PCI: 00:1f.3 20 base 00000400 limit 0000041f io (fixed) [INFO ] DOMAIN: 0000: Resource ranges: [INFO ] * Base: 1000, Size: f000, Tag: 100 [DEBUG] PCI: 00:1c.0 1c * [0x1000 - 0x1fff] limit: 1fff io [DEBUG] PCI: 00:1c.1 1c * [0x2000 - 0x2fff] limit: 2fff io [DEBUG] PCI: 00:1c.2 1c * [0x3000 - 0x3fff] limit: 3fff io [DEBUG] PCI: 00:1d.0 20 * [0x4000 - 0x401f] limit: 401f io [DEBUG] PCI: 00:1d.1 20 * [0x4020 - 0x403f] limit: 403f io [DEBUG] PCI: 00:1d.2 20 * [0x4040 - 0x405f] limit: 405f io [DEBUG] PCI: 00:1d.3 20 * [0x4060 - 0x407f] limit: 407f io [DEBUG] PCI: 00:1f.2 20 * [0x4080 - 0x408f] limit: 408f io [DEBUG] PCI: 00:02.0 14 * [0x4090 - 0x4097] limit: 4097 io [DEBUG] PCI: 00:1f.2 10 * [0x4098 - 0x409f] limit: 409f io [DEBUG] PCI: 00:1f.2 18 * [0x40a0 - 0x40a7] limit: 40a7 io [DEBUG] PCI: 00:1f.2 14 * [0x40a8 - 0x40ab] limit: 40ab io [DEBUG] PCI: 00:1f.2 1c * [0x40ac - 0x40af] limit: 40af io [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff [DEBUG] update_constraints: DOMAIN: 0000 03 base 00000000 limit 0009ffff mem (fixed) [DEBUG] update_constraints: DOMAIN: 0000 04 base 00100000 limit cfffffff mem (fixed) [DEBUG] update_constraints: DOMAIN: 0000 05 base cf800000 limit cfffffff mem (fixed) [DEBUG] update_constraints: DOMAIN: 0000 06 base cf600000 limit cf7fffff mem (fixed) [DEBUG] update_constraints: DOMAIN: 0000 07 base cf400000 limit cf5fffff mem (fixed) [DEBUG] update_constraints: DOMAIN: 0000 08 base 000a0000 limit 000bffff mem (fixed) [DEBUG] update_constraints: DOMAIN: 0000 09 base 000c0000 limit 000fffff mem (fixed) [DEBUG] update_constraints: PCI: 00:00.0 48 base f0000000 limit f3ffffff mem (fixed) [DEBUG] update_constraints: PCI: 00:1f.0 10000100 base ff800000 limit ffffffff mem (fixed) [DEBUG] update_constraints: PCI: 00:1f.0 03 base fec00000 limit fec00fff mem (fixed) [INFO ] DOMAIN: 0000: Resource ranges: [INFO ] * Base: d0000000, Size: 20000000, Tag: 200 [INFO ] * Base: f4000000, Size: ac00000, Tag: 200 [INFO ] * Base: fec01000, Size: bff000, Tag: 200 [INFO ] * Base: 100000000, Size: f00000000, Tag: 100200 [DEBUG] PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] limit: dfffffff prefmem [DEBUG] PCI: 00:1c.0 20 * [0xe0000000 - 0xe00fffff] limit: e00fffff mem [DEBUG] PCI: 00:1c.1 20 * [0xe0100000 - 0xe01fffff] limit: e01fffff mem [DEBUG] PCI: 00:1c.2 20 * [0xe0200000 - 0xe02fffff] limit: e02fffff mem [DEBUG] PCI: 00:1e.0 20 * [0xe0300000 - 0xe03fffff] limit: e03fffff mem [DEBUG] PCI: 00:02.0 10 * [0xe0400000 - 0xe047ffff] limit: e047ffff mem [DEBUG] PCI: 00:02.1 10 * [0xe0480000 - 0xe04fffff] limit: e04fffff mem [DEBUG] PCI: 00:02.0 1c * [0xe0500000 - 0xe053ffff] limit: e053ffff mem [DEBUG] PCI: 00:1b.0 10 * [0xe0540000 - 0xe0543fff] limit: e0543fff mem [DEBUG] PCI: 00:1d.7 10 * [0xe0544000 - 0xe05443ff] limit: e05443ff mem [DEBUG] PCI: 00:1f.2 24 * [0xe0545000 - 0xe05453ff] limit: e05453ff mem [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done [DEBUG] PCI: 00:1c.0 io: base: 1000 size: 1000 align: 12 gran: 12 limit: 1fff [INFO ] PCI: 00:1c.0: Resource ranges: [INFO ] * Base: 1000, Size: 1000, Tag: 100 [DEBUG] PCI: 01:00.0 10 * [0x1000 - 0x10ff] limit: 10ff io [DEBUG] PCI: 00:1c.0 io: base: 1000 size: 1000 align: 12 gran: 12 limit: 1fff done [DEBUG] PCI: 00:1c.0 mem: base: e0000000 size: 100000 align: 20 gran: 20 limit: e00fffff [INFO ] PCI: 00:1c.0: Resource ranges: [INFO ] * Base: e0000000, Size: 100000, Tag: 200 [DEBUG] PCI: 01:00.0 30 * [0xe0000000 - 0xe001ffff] limit: e001ffff mem [DEBUG] PCI: 01:00.0 18 * [0xe0020000 - 0xe0020fff] limit: e0020fff mem [DEBUG] PCI: 00:1c.0 mem: base: e0000000 size: 100000 align: 20 gran: 20 limit: e00fffff done [DEBUG] PCI: 00:1c.1 io: base: 2000 size: 1000 align: 12 gran: 12 limit: 2fff [INFO ] PCI: 00:1c.1: Resource ranges: [INFO ] * Base: 2000, Size: 1000, Tag: 100 [DEBUG] PCI: 02:00.0 10 * [0x2000 - 0x20ff] limit: 20ff io [DEBUG] PCI: 00:1c.1 io: base: 2000 size: 1000 align: 12 gran: 12 limit: 2fff done [DEBUG] PCI: 00:1c.1 mem: base: e0100000 size: 100000 align: 20 gran: 20 limit: e01fffff [INFO ] PCI: 00:1c.1: Resource ranges: [INFO ] * Base: e0100000, Size: 100000, Tag: 200 [DEBUG] PCI: 02:00.0 30 * [0xe0100000 - 0xe011ffff] limit: e011ffff mem [DEBUG] PCI: 02:00.0 18 * [0xe0120000 - 0xe0120fff] limit: e0120fff mem [DEBUG] PCI: 00:1c.1 mem: base: e0100000 size: 100000 align: 20 gran: 20 limit: e01fffff done [DEBUG] PCI: 00:1c.2 io: base: 3000 size: 1000 align: 12 gran: 12 limit: 3fff [INFO ] PCI: 00:1c.2: Resource ranges: [INFO ] * Base: 3000, Size: 1000, Tag: 100 [DEBUG] PCI: 03:00.0 10 * [0x3000 - 0x30ff] limit: 30ff io [DEBUG] PCI: 00:1c.2 io: base: 3000 size: 1000 align: 12 gran: 12 limit: 3fff done [DEBUG] PCI: 00:1c.2 mem: base: e0200000 size: 100000 align: 20 gran: 20 limit: e02fffff [INFO ] PCI: 00:1c.2: Resource ranges: [INFO ] * Base: e0200000, Size: 100000, Tag: 200 [DEBUG] PCI: 03:00.0 30 * [0xe0200000 - 0xe021ffff] limit: e021ffff mem [DEBUG] PCI: 03:00.0 18 * [0xe0220000 - 0xe0220fff] limit: e0220fff mem [DEBUG] PCI: 00:1c.2 mem: base: e0200000 size: 100000 align: 20 gran: 20 limit: e02fffff done [DEBUG] PCI: 00:1e.0 mem: base: e0300000 size: 100000 align: 20 gran: 20 limit: e03fffff [INFO ] PCI: 00:1e.0: Resource ranges: [INFO ] * Base: e0300000, Size: 100000, Tag: 200 [DEBUG] PCI: 04:00.0 14 * [0xe0300000 - 0xe0303fff] limit: e0303fff mem [DEBUG] PCI: 04:00.0 10 * [0xe0304000 - 0xe03047ff] limit: e03047ff mem [DEBUG] PCI: 00:1e.0 mem: base: e0300000 size: 100000 align: 20 gran: 20 limit: e03fffff done [INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete === [DEBUG] DOMAIN: 0000 03 <- [0x0000000000000000 - 0x000000000009ffff] size 0x000a0000 gran 0x00 mem [DEBUG] DOMAIN: 0000 04 <- [0x0000000000100000 - 0x00000000cfffffff] size 0xcff00000 gran 0x00 mem [DEBUG] DOMAIN: 0000 05 <- [0x00000000cf800000 - 0x00000000cfffffff] size 0x00800000 gran 0x00 mem [DEBUG] DOMAIN: 0000 06 <- [0x00000000cf600000 - 0x00000000cf7fffff] size 0x00200000 gran 0x00 mem [DEBUG] DOMAIN: 0000 07 <- [0x00000000cf400000 - 0x00000000cf5fffff] size 0x00200000 gran 0x00 mem [DEBUG] DOMAIN: 0000 08 <- [0x00000000000a0000 - 0x00000000000bffff] size 0x00020000 gran 0x00 mem [DEBUG] DOMAIN: 0000 09 <- [0x00000000000c0000 - 0x00000000000fffff] size 0x00040000 gran 0x00 mem [DEBUG] PCI: 00:02.0 10 <- [0x00000000e0400000 - 0x00000000e047ffff] size 0x00080000 gran 0x13 mem [DEBUG] PCI: 00:02.0 14 <- [0x0000000000004090 - 0x0000000000004097] size 0x00000008 gran 0x03 io [DEBUG] PCI: 00:02.0 18 <- [0x00000000d0000000 - 0x00000000dfffffff] size 0x10000000 gran 0x1c prefmem [DEBUG] PCI: 00:02.0 1c <- [0x00000000e0500000 - 0x00000000e053ffff] size 0x00040000 gran 0x12 mem [DEBUG] PCI: 00:02.1 10 <- [0x00000000e0480000 - 0x00000000e04fffff] size 0x00080000 gran 0x13 mem [DEBUG] PCI: 00:1b.0 10 <- [0x00000000e0540000 - 0x00000000e0543fff] size 0x00004000 gran 0x0e mem64 [DEBUG] PCI: 00:1c.0 1c <- [0x0000000000001000 - 0x0000000000001fff] size 0x00001000 gran 0x0c bus 01 io [DEBUG] PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem [DEBUG] PCI: 00:1c.0 20 <- [0x00000000e0000000 - 0x00000000e00fffff] size 0x00100000 gran 0x14 bus 01 mem [DEBUG] PCI: 01:00.0 10 <- [0x0000000000001000 - 0x00000000000010ff] size 0x00000100 gran 0x08 io [DEBUG] PCI: 01:00.0 18 <- [0x00000000e0020000 - 0x00000000e0020fff] size 0x00001000 gran 0x0c mem64 [DEBUG] PCI: 01:00.0 30 <- [0x00000000e0000000 - 0x00000000e001ffff] size 0x00020000 gran 0x11 romem [DEBUG] PCI: 00:1c.1 1c <- [0x0000000000002000 - 0x0000000000002fff] size 0x00001000 gran 0x0c bus 02 io [DEBUG] PCI: 00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem [DEBUG] PCI: 00:1c.1 20 <- [0x00000000e0100000 - 0x00000000e01fffff] size 0x00100000 gran 0x14 bus 02 mem [DEBUG] PCI: 02:00.0 10 <- [0x0000000000002000 - 0x00000000000020ff] size 0x00000100 gran 0x08 io [DEBUG] PCI: 02:00.0 18 <- [0x00000000e0120000 - 0x00000000e0120fff] size 0x00001000 gran 0x0c mem64 [DEBUG] PCI: 02:00.0 30 <- [0x00000000e0100000 - 0x00000000e011ffff] size 0x00020000 gran 0x11 romem [DEBUG] PCI: 00:1c.2 1c <- [0x0000000000003000 - 0x0000000000003fff] size 0x00001000 gran 0x0c bus 03 io [DEBUG] PCI: 00:1c.2 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 03 prefmem [DEBUG] PCI: 00:1c.2 20 <- [0x00000000e0200000 - 0x00000000e02fffff] size 0x00100000 gran 0x14 bus 03 mem [DEBUG] PCI: 03:00.0 10 <- [0x0000000000003000 - 0x00000000000030ff] size 0x00000100 gran 0x08 io [DEBUG] PCI: 03:00.0 18 <- [0x00000000e0220000 - 0x00000000e0220fff] size 0x00001000 gran 0x0c mem64 [DEBUG] PCI: 03:00.0 30 <- [0x00000000e0200000 - 0x00000000e021ffff] size 0x00020000 gran 0x11 romem [DEBUG] PCI: 00:1d.0 20 <- [0x0000000000004000 - 0x000000000000401f] size 0x00000020 gran 0x05 io [DEBUG] PCI: 00:1d.1 20 <- [0x0000000000004020 - 0x000000000000403f] size 0x00000020 gran 0x05 io [DEBUG] PCI: 00:1d.2 20 <- [0x0000000000004040 - 0x000000000000405f] size 0x00000020 gran 0x05 io [DEBUG] PCI: 00:1d.3 20 <- [0x0000000000004060 - 0x000000000000407f] size 0x00000020 gran 0x05 io [DEBUG] PCI: 00:1d.7 10 <- [0x00000000e0544000 - 0x00000000e05443ff] size 0x00000400 gran 0x0a mem [DEBUG] PCI: 00:1e.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 04 io [DEBUG] PCI: 00:1e.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 04 prefmem [DEBUG] PCI: 00:1e.0 20 <- [0x00000000e0300000 - 0x00000000e03fffff] size 0x00100000 gran 0x14 bus 04 mem [DEBUG] PCI: 04:00.0 10 <- [0x00000000e0304000 - 0x00000000e03047ff] size 0x00000800 gran 0x0b mem [DEBUG] PCI: 04:00.0 14 <- [0x00000000e0300000 - 0x00000000e0303fff] size 0x00004000 gran 0x0e mem [DEBUG] PNP: 002e.1 60 <- [0x0000000000000378 - 0x000000000000037f] size 0x00000008 gran 0x03 io [DEBUG] PNP: 002e.1 70 <- [0x0000000000000005 - 0x0000000000000005] size 0x00000001 gran 0x00 irq [ERROR] PNP: 002e.1 74 drq size: 0x0000000001 not assigned in devicetree [DEBUG] PNP: 002e.2 60 <- [0x00000000000003f8 - 0x00000000000003ff] size 0x00000008 gran 0x03 io [DEBUG] PNP: 002e.2 70 <- [0x0000000000000004 - 0x0000000000000004] size 0x00000001 gran 0x00 irq [DEBUG] PNP: 002e.3 60 <- [0x00000000000002f8 - 0x00000000000002ff] size 0x00000008 gran 0x03 io [DEBUG] PNP: 002e.3 70 <- [0x0000000000000003 - 0x0000000000000003] size 0x00000001 gran 0x00 irq [DEBUG] PNP: 002e.3 f1 <- [0x0000000000000004 - 0x0000000000000004] size 0x00000001 gran 0x00 irq [DEBUG] PNP: 002e.5 60 <- [0x0000000000000060 - 0x0000000000000060] size 0x00000001 gran 0x00 io [DEBUG] PNP: 002e.5 62 <- [0x0000000000000064 - 0x0000000000000064] size 0x00000001 gran 0x00 io [DEBUG] PNP: 002e.5 70 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 irq [DEBUG] PNP: 002e.5 72 <- [0x000000000000000c - 0x000000000000000c] size 0x00000001 gran 0x00 irq [DEBUG] PNP: 002e.5 f0 <- [0x0000000000000082 - 0x0000000000000082] size 0x00000001 gran 0x00 irq [DEBUG] PNP: 002e.7 60 <- [0x0000000000000220 - 0x0000000000000220] size 0x00000001 gran 0x00 io [DEBUG] PNP: 002e.7 62 <- [0x0000000000000330 - 0x0000000000000331] size 0x00000002 gran 0x01 io [DEBUG] PNP: 002e.7 70 <- [0x0000000000000009 - 0x0000000000000009] size 0x00000001 gran 0x00 irq [DEBUG] PNP: 002e.9 30 <- [0x0000000000000003 - 0x0000000000000003] size 0x00000001 gran 0x00 irq [DEBUG] PNP: 002e.9 f0 <- [0x00000000000000fb - 0x00000000000000fb] size 0x00000001 gran 0x00 irq [DEBUG] PNP: 002e.9 f1 <- [0x0000000000000066 - 0x0000000000000066] size 0x00000001 gran 0x00 irq [DEBUG] PNP: 002e.b 60 <- [0x0000000000000a00 - 0x0000000000000a07] size 0x00000008 gran 0x03 io [DEBUG] PNP: 002e.b 70 <- [0x0000000000000000 - 0x0000000000000000] size 0x00000001 gran 0x00 irq [DEBUG] PNP: 004e.2 60 <- [0x00000000000003e8 - 0x00000000000003ef] size 0x00000008 gran 0x03 io [DEBUG] PNP: 004e.2 70 <- [0x0000000000000006 - 0x0000000000000006] size 0x00000001 gran 0x00 irq [DEBUG] PNP: 004e.3 60 <- [0x00000000000002e8 - 0x00000000000002ef] size 0x00000008 gran 0x03 io [DEBUG] PNP: 004e.3 70 <- [0x0000000000000006 - 0x0000000000000006] size 0x00000001 gran 0x00 irq [DEBUG] PNP: 004e.3 f1 <- [0x0000000000000004 - 0x0000000000000004] size 0x00000001 gran 0x00 irq [DEBUG] PCI: 00:1f.2 10 <- [0x0000000000004098 - 0x000000000000409f] size 0x00000008 gran 0x03 io [DEBUG] PCI: 00:1f.2 14 <- [0x00000000000040a8 - 0x00000000000040ab] size 0x00000004 gran 0x02 io [DEBUG] PCI: 00:1f.2 18 <- [0x00000000000040a0 - 0x00000000000040a7] size 0x00000008 gran 0x03 io [DEBUG] PCI: 00:1f.2 1c <- [0x00000000000040ac - 0x00000000000040af] size 0x00000004 gran 0x02 io [DEBUG] PCI: 00:1f.2 20 <- [0x0000000000004080 - 0x000000000000408f] size 0x00000010 gran 0x04 io [DEBUG] PCI: 00:1f.2 24 <- [0x00000000e0545000 - 0x00000000e05453ff] size 0x00000400 gran 0x0a mem [INFO ] Done setting resources. [INFO ] Done allocating resources. [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 3 / 1662 ms [INFO ] Enabling resources... [DEBUG] PCI: 00:00.0 subsystem <- 8086/27ac [DEBUG] PCI: 00:00.0 cmd <- 06 [DEBUG] PCI: 00:02.0 subsystem <- 8086/27ae [DEBUG] PCI: 00:02.0 cmd <- 03 [DEBUG] PCI: 00:02.1 subsystem <- 8086/27a6 [DEBUG] PCI: 00:02.1 cmd <- 02 [DEBUG] PCI: 00:1b.0 subsystem <- 8086/27d8 [DEBUG] PCI: 00:1b.0 cmd <- 102 [DEBUG] PCI: 00:1c.0 bridge ctrl <- 0013 [DEBUG] PCI: 00:1c.0 subsystem <- 8086/27d0 [DEBUG] PCI: 00:1c.0 cmd <- 107 [DEBUG] PCI: 00:1c.1 bridge ctrl <- 0013 [DEBUG] PCI: 00:1c.1 subsystem <- 8086/27d2 [DEBUG] PCI: 00:1c.1 cmd <- 107 [DEBUG] PCI: 00:1c.2 bridge ctrl <- 0013 [DEBUG] PCI: 00:1c.2 subsystem <- 8086/27d4 [DEBUG] PCI: 00:1c.2 cmd <- 107 [DEBUG] PCI: 00:1d.0 subsystem <- 8086/27c8 [DEBUG] PCI: 00:1d.0 cmd <- 01 [DEBUG] PCI: 00:1d.1 subsystem <- 8086/27c9 [DEBUG] PCI: 00:1d.1 cmd <- 01 [DEBUG] PCI: 00:1d.2 subsystem <- 8086/27ca [DEBUG] PCI: 00:1d.2 cmd <- 01 [DEBUG] PCI: 00:1d.3 subsystem <- 8086/27cb [DEBUG] PCI: 00:1d.3 cmd <- 01 [DEBUG] PCI: 00:1d.7 subsystem <- 8086/27cc [DEBUG] PCI: 00:1d.7 cmd <- 102 [DEBUG] PCI: 00:1e.0 bridge ctrl <- 0013 [DEBUG] PCI: 00:1e.0 subsystem <- 8086/244e [DEBUG] PCI: 00:1e.0 cmd <- 106 [DEBUG] PCI: 00:1f.0 subsystem <- 8086/27b8 [DEBUG] PCI: 00:1f.0 cmd <- 107 [DEBUG] PCI: 00:1f.2 subsystem <- 8086/27c0 [DEBUG] PCI: 00:1f.2 cmd <- 03 [DEBUG] PCI: 00:1f.3 subsystem <- 8086/27da [DEBUG] PCI: 00:1f.3 cmd <- 101 [DEBUG] PCI: 01:00.0 cmd <- 03 [DEBUG] PCI: 02:00.0 cmd <- 03 [DEBUG] PCI: 03:00.0 cmd <- 03 [DEBUG] PCI: 04:00.0 subsystem <- 104c/8023 [DEBUG] PCI: 04:00.0 cmd <- 102 [INFO ] done. [DEBUG] BS: BS_DEV_ENABLE run times (exec / console): 0 / 172 ms [INFO ] Initializing devices... [DEBUG] CPU_CLUSTER: 0 init [DEBUG] FMAP: area COREBOOT found @ 300200 (1048064 bytes) [INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0xc8c0 size 0x18000 in mcache @0xcf3dd0ac [DEBUG] microcode: sig=0x6fb pf=0x20 revision=0x0 [INFO ] microcode: load microcode patch [INFO ] microcode: updated to revision 0xba date=2010-10-03 [DEBUG] MTRR: Physical address space: [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6 [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0 [DEBUG] 0x00000000000c0000 - 0x00000000cf3fffff size 0xcf340000 type 6 [DEBUG] 0x00000000cf400000 - 0x00000000cfffffff size 0x00c00000 type 0 [DEBUG] 0x00000000d0000000 - 0x00000000dfffffff size 0x10000000 type 1 [DEBUG] 0x00000000e0000000 - 0x00000000ffffffff size 0x20000000 type 0 [DEBUG] MTRR: Fixed MSR 0x250 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x258 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x259 0x0000000000000000 [DEBUG] MTRR: Fixed MSR 0x268 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x269 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x26a 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x26b 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x26c 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x26d 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x26e 0x0606060606060606 [DEBUG] MTRR: Fixed MSR 0x26f 0x0606060606060606 [DEBUG] CPU physical address size: 36 bits [DEBUG] MTRR: default type WB/UC MTRR counts: 4/6. [DEBUG] MTRR: WB selected as default type. [DEBUG] MTRR: 0 base 0x00000000cf400000 mask 0x0000000fffc00000 type 0 [DEBUG] MTRR: 1 base 0x00000000cf800000 mask 0x0000000fff800000 type 0 [DEBUG] MTRR: 2 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 [DEBUG] MTRR: 3 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0 [DEBUG] MTRR check [DEBUG] Fixed MTRRs : Enabled [DEBUG] Variable MTRRs: Enabled [DEBUG] CPU has 2 cores. [DEBUG] Setting up SMI for CPU [INFO ] Will perform SMM setup. [INFO ] CPU: Intel(R) Core(TM)2 Duo CPU T7400 @ 2.16GHz. [INFO ] LAPIC 0x0 in XAPIC mode. [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178 [DEBUG] Processing 18 relocs. Offset value of 0x00030000 [DEBUG] Attempting to start 1 APs [DEBUG] Waiting for 10ms after sending INIT. [DEBUG] Waiting for SIPI to complete... [INFO ] LAPIC 0x1 in XAPIC mode. [DEBUG] done. [INFO ] AP: slot 1 apic_id 1, MCU rev: 0x000000ba [DEBUG] Waiting for SIPI to complete... [DEBUG] done. [DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e0 memsize: 0x1e0 [DEBUG] Processing 11 relocs. Offset value of 0x00038000 [DEBUG] smm_module_setup_stub: stack_top = 0xcf600800 [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400 [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x80 [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000 [DEBUG] SMM Module: stub loaded at 38000. Will call 0xcf3a27c6 [DEBUG] Installing permanent SMM handler to 0xcf600000 [DEBUG] FX_SAVE [0xcf6ffc00-0xcf700000] [DEBUG] HANDLER [0xcf6ff000-0xcf6ff688] [DEBUG] CPU 0 [DEBUG] ss0 [0xcf6fec00-0xcf6ff000] [DEBUG] stub0 [0xcf6f7000-0xcf6f71e0] [DEBUG] CPU 1 [DEBUG] ss1 [0xcf6fe800-0xcf6fec00] [DEBUG] stub1 [0xcf6f6c00-0xcf6f6de0] [DEBUG] stacks [0xcf600000-0xcf600800] [DEBUG] Loading module at 0xcf6ff000 with entry 0xcf6ff078. filesize: 0x678 memsize: 0x688 [DEBUG] Processing 28 relocs. Offset value of 0xcf6ff000 [DEBUG] Loading module at 0xcf6f7000 with entry 0xcf6f7000. filesize: 0x1e0 memsize: 0x1e0 [DEBUG] Processing 11 relocs. Offset value of 0xcf6f7000 [DEBUG] smm_module_setup_stub: stack_top = 0xcf600800 [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400 [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x80 [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x100000 [DEBUG] SMM Module: placing smm entry code at cf6f6c00, cpu # 0x1 [DEBUG] SMM Module: stub loaded at cf6f7000. Will call 0xcf6ff078 [DEBUG] Initializing southbridge SMI... [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0xcf6ef000, cpu = 0 [DEBUG] In relocation handler: cpu 0 [DEBUG] New SMBASE=0xcf6ef000 [WARN ] SMRR not enabled, skip writing SMRR... [DEBUG] Relocation complete. [DEBUG] VMX status: enabled [DEBUG] VMX status: enabled [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0xcf6eec00, cpu = 1 [DEBUG] In relocation handler: cpu 1 [DEBUG] New SMBASE=0xcf6eec00 [DEBUG] Writing SMRR. base = 0xcf600000, mask=0xffe00800 [DEBUG] Relocation complete. [INFO ] Initializing CPU #0 [DEBUG] CPU: vendor Intel device 6fb [DEBUG] CPU: family 06, model 0f, stepping 0b [INFO ] CPU: Intel(R) Core(TM)2 Duo CPU T7400 @ 2.16GHz. [INFO ] CPU #0 initialized [INFO ] Initializing CPU #1 [DEBUG] CPU: vendor Intel device 6fb [DEBUG] CPU: family 06, model 0f, stepping 0b [INFO ] CPU: Intel(R) Core(TM)2 Duo CPU T7400 @ 2.16GHz. [INFO ] CPU #1 initialized [DEBUG] CPU 1 going down... [INFO ] bsp_do_flight_plan done after 254 msecs. [DEBUG] Initializing southbridge SMI... [DEBUG] SMI_STS: TCO [DEBUG] GPE0_STS: GPIO15 GPIO14 GPIO11 GPIO10 GPIO9 GPIO8 GPIO6 GPIO1 GPIO0 [DEBUG] ALT_GP_SMI_STS: GPI15 GPI14 GPI13 GPI12 GPI11 GPI10 GPI9 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 [DEBUG] TCO_STS: [DEBUG] Locking SMM. [DEBUG] CPU_CLUSTER: 0 init finished in 586 msecs [DEBUG] PCI: 00:02.0 init [WARN ] CBFS: 'vbt.bin' not found. [WARN ] CBFS: 'pci8086,27ae.rom' not found. [DEBUG] PCI Option ROM loading disabled for PCI: 00:02.0 [DEBUG] GMA: locate_vbt_vbios: 5412 1000 e1 58 72 [ERROR] GMA: VBT couldn't be found [WARN ] CBFS: 'pci8086,27ae.rom' not found. [DEBUG] PCI Option ROM loading disabled for PCI: 00:02.0 [DEBUG] PCI: 00:02.0 init finished in 33 msecs [DEBUG] PCI: 00:02.1 init [DEBUG] PCI: 00:02.1 init finished in 0 msecs [DEBUG] PCI: 00:1b.0 init [DEBUG] Azalia: codec type: Azalia [DEBUG] Azalia: base = e0540000 [DEBUG] Azalia: codec_mask = 04 [DEBUG] azalia_audio: Initializing codec #2 [DEBUG] azalia_audio: codec viddid: 10ec0888 [DEBUG] azalia_audio: No verb! [DEBUG] PCI: 00:1b.0 init finished in 26 msecs [DEBUG] PCI: 00:1c.0 init [DEBUG] Initializing ICH7 PCIe bridge. [DEBUG] PCI: 00:1c.0 init finished in 4 msecs [DEBUG] PCI: 00:1c.1 init [DEBUG] Initializing ICH7 PCIe bridge. [DEBUG] PCI: 00:1c.1 init finished in 4 msecs [DEBUG] PCI: 00:1c.2 init [DEBUG] Initializing ICH7 PCIe bridge. [DEBUG] PCI: 00:1c.2 init finished in 4 msecs [DEBUG] PCI: 00:1d.0 init [DEBUG] UHCI: Setting up controller.. done. [DEBUG] PCI: 00:1d.0 init finished in 4 msecs [DEBUG] PCI: 00:1d.1 init [DEBUG] UHCI: Setting up controller.. done. [DEBUG] PCI: 00:1d.1 init finished in 4 msecs [DEBUG] PCI: 00:1d.2 init [DEBUG] UHCI: Setting up controller.. done. [DEBUG] PCI: 00:1d.2 init finished in 4 msecs [DEBUG] PCI: 00:1d.3 init [DEBUG] UHCI: Setting up controller.. done. [DEBUG] PCI: 00:1d.3 init finished in 4 msecs [DEBUG] PCI: 00:1d.7 init [DEBUG] EHCI: Setting up controller.. done. [DEBUG] PCI: 00:1d.7 init finished in 4 msecs [DEBUG] PCI: 00:1e.0 init [DEBUG] PCI: 00:1e.0 init finished in 0 msecs [DEBUG] PCI: 00:1f.0 init [DEBUG] i82801gx: lpc_init [DEBUG] IOAPIC: Initializing IOAPIC at 0xfec00000 [DEBUG] IOAPIC: ID = 0x02 [DEBUG] IOAPIC: 24 interrupts [DEBUG] IOAPIC: Clearing IOAPIC at 0xfec00000 [DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00 [INFO ] Set power on after power failure. [INFO ] NMI sources disabled. [DEBUG] rtc_failed = 0x0 [DEBUG] RTC Init [DEBUG] apm_control: Disabling ACPI. [DEBUG] APMC done. [DEBUG] PCI: 00:1f.0 init finished in 44 msecs [DEBUG] PCI: 00:1f.2 init [DEBUG] i82801gx_sata: initializing... [DEBUG] SATA controller in combined mode. [DEBUG] PCI: 00:1f.2 init finished in 8 msecs [DEBUG] PCI: 01:00.0 init [DEBUG] PCI: 01:00.0 init finished in 0 msecs [DEBUG] PCI: 02:00.0 init [DEBUG] PCI: 02:00.0 init finished in 0 msecs [DEBUG] PCI: 03:00.0 init [DEBUG] PCI: 03:00.0 init finished in 0 msecs [DEBUG] PCI: 04:00.0 init [DEBUG] PCI: 04:00.0 init finished in 0 msecs [DEBUG] PNP: 002e.1 init [DEBUG] PNP: 002e.1 init finished in 0 msecs [DEBUG] PNP: 002e.2 init [DEBUG] PNP: 002e.2 init finished in 0 msecs [DEBUG] PNP: 002e.3 init [DEBUG] PNP: 002e.3 init finished in 0 msecs [DEBUG] PNP: 002e.5 init [DEBUG] PNP: 002e.5 init finished in 0 msecs [DEBUG] PNP: 002e.7 init [DEBUG] PNP: 002e.7 init finished in 0 msecs [DEBUG] PNP: 002e.8 init [DEBUG] PNP: 002e.8 init finished in 0 msecs [DEBUG] PNP: 002e.9 init [DEBUG] PNP: 002e.9 init finished in 0 msecs [DEBUG] PNP: 002e.b init [DEBUG] PNP: 002e.b init finished in 0 msecs [DEBUG] PNP: 004e.2 init [DEBUG] PNP: 004e.2 init finished in 0 msecs [DEBUG] PNP: 004e.3 init [DEBUG] PNP: 004e.3 init finished in 0 msecs [INFO ] Devices initialized [DEBUG] BS: BS_DEV_INIT run times (exec / console): 96 / 873 ms [INFO ] Finalize devices... [DEBUG] PCI: 00:1f.0 final [INFO ] Devices finalized [DEBUG] BS: BS_POST_DEVICE run times (exec / console): 0 / 9 ms [INFO ] Copying Interrupt Routing Table to 0x000f0000... done. [INFO ] Copying Interrupt Routing Table to 0xcf377000... done. [DEBUG] PIRQ table: 320 bytes. [DEBUG] Wrote the mp table end at: 0x000f0410 - 0x000f059c [DEBUG] Wrote the mp table end at: 0xcf376010 - 0xcf37619c [DEBUG] MP table: 412 bytes. [INFO ] CBFS: Found 'fallback/dsdt.aml' @0x38680 size 0x23f8 in mcache @0xcf3dd198 [WARN ] CBFS: 'fallback/slic' not found. [INFO ] ACPI: Writing ACPI tables at cf352000. [DEBUG] ACPI: * FACS [DEBUG] ACPI: * DSDT [DEBUG] ACPI: * FADT [DEBUG] ACPI: added table 1/32, length now 40 [DEBUG] ACPI: * SSDT [DEBUG] Found 1 CPU(s) with 2 core(s) each. [DEBUG] clocks between 1000 and 2166 MHz. [DEBUG] adding 4 P-States between busratio 6 and d, incl. P0 [DEBUG] PSS: 2166MHz power 35000 control 0xd29 status 0xd29 [DEBUG] PSS: 1666MHz power 31666 control 0xa21 status 0xa21 [DEBUG] PSS: 1333MHz power 28333 control 0x81a status 0x81a [DEBUG] PSS: 1000MHz power 25000 control 0x613 status 0x613 [DEBUG] clocks between 1000 and 2166 MHz. [DEBUG] adding 4 P-States between busratio 6 and d, incl. P0 [DEBUG] PSS: 2166MHz power 35000 control 0xd29 status 0xd29 [DEBUG] PSS: 1666MHz power 31666 control 0xa21 status 0xa21 [DEBUG] PSS: 1333MHz power 28333 control 0x81a status 0x81a [DEBUG] PSS: 1000MHz power 25000 control 0x613 status 0x613 [DEBUG] Generating ACPI PIRQ entries [DEBUG] ACPI: added table 2/32, length now 44 [DEBUG] ACPI: * MCFG [DEBUG] ACPI: added table 3/32, length now 48 [DEBUG] ACPI: * MADT [DEBUG] ACPI: added table 4/32, length now 52 [DEBUG] current = cf354e80 [DEBUG] ACPI: * HPET [DEBUG] ACPI: added table 5/32, length now 56 [INFO ] ACPI: done. [DEBUG] ACPI tables: 11968 bytes. [DEBUG] smbios_write_tables: cf34a000 [DEBUG] SMBIOS firmware version is set to coreboot_version: '4.17-1747-gd91f3a4eaf' [DEBUG] SMBIOS tables: 577 bytes. [DEBUG] Writing table forward entry at 0x00000500 [DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum b0a6 [DEBUG] Writing coreboot table at 0xcf378000 [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES [DEBUG] 1. 0000000000001000-000000000009ffff: RAM [DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED [DEBUG] 3. 0000000000100000-00000000cf349fff: RAM [DEBUG] 4. 00000000cf34a000-00000000cf390fff: CONFIGURATION TABLES [DEBUG] 5. 00000000cf391000-00000000cf3cefff: RAMSTAGE [DEBUG] 6. 00000000cf3cf000-00000000cf3fffff: CONFIGURATION TABLES [DEBUG] 7. 00000000cf400000-00000000cfffffff: RESERVED [DEBUG] 8. 00000000f0000000-00000000f3ffffff: RESERVED [DEBUG] Wrote coreboot table at: 0xcf378000, 0x364 bytes, checksum 25ff [DEBUG] coreboot table: 892 bytes. [DEBUG] IMD ROOT 0. 0xcf3ff000 0x00001000 [DEBUG] I[