Nick: hell
E-mail: NULL
Board: HP ProBook 6550b
Contents: 
[NOTE ]  coreboot-4.15-1556-g9d458a95bd-dirty Mon Feb 14 19:27:41 UTC 2022 bootblock starting (log level: 8)...
[DEBUG]  FMAP: Found "FLASH" version 1.1 at 0x210000.
[DEBUG]  FMAP: base = 0xffc00000 size = 0x400000 #areas = 4
[DEBUG]  FMAP: area COREBOOT found @ 210200 (2031104 bytes)
[INFO ]  CBFS: mcache @0xfefc2e00 built for 14 files, used 0x328 of 0x4000 bytes
[INFO ]  CBFS: Found 'fallback/romstage' @0x80 size 0x112a8 in mcache @0xfefc2e2c
[DEBUG]  BS: bootblock times (exec / console): total (unknown) / 45 ms


[NOTE ]  coreboot-4.15-1556-g9d458a95bd-dirty Mon Feb 14 19:27:41 UTC 2022 romstage starting (log level: 8)...
[DEBUG]  Setting up static southbridge registers... done.
[DEBUG]  Disabling Watchdog reboot... done.
[DEBUG]  Setting up static northbridge registers... done.
[DEBUG]  SMBus controller enabled
[DEBUG]  Setting up Chipset Initialization Registers (CIR)
[DEBUG]  Scratchpad MCHBAR8(0x2ca8): 0x0000
[INFO ]  Intel ME early init
[INFO ]  Intel ME firmware is ready
[DEBUG]  ME: Requested 32MB UMA
[DEBUG]  CAPID0[0] = 0x010c0009
[DEBUG]  CAPID0[1] = 0x00b16126
[DEBUG]  CAPID0[2] = 0x00400088
[DEBUG]  Revision ID: 0x18
[DEBUG]  Device ID: 0x44
[DEBUG]  FMAP: area RW_MRC_CACHE found @ 200000 (65536 bytes)
[ERROR]  MRC: no data in 'RW_MRC_CACHE'
[SPEW ]  reg2ca9_bit0 = 0
[SPEW ]  reg274265[0][0] = 5
[SPEW ]  reg274265[0][1] = 5
[SPEW ]  reg274265[0][2] = e
[SPEW ]  reg274265[1][0] = 5
[SPEW ]  reg274265[1][1] = 5
[SPEW ]  reg274265[1][2] = e
[SPEW ]  [6dc] <= 23faff
[SPEW ]  [6e8] <= 23faff
[DEBUG]  Issuing a CPU reset


[NOTE ]  coreboot-4.15-1556-g9d458a95bd-dirty Mon Feb 14 19:27:41 UTC 2022 bootblock starting (log level: 8)...
[DEBUG]  FMAP: Found "FLASH" version 1.1 at 0x210000.
[DEBUG]  FMAP: base = 0xffc00000 size = 0x400000 #areas = 4
[DEBUG]  FMAP: area COREBOOT found @ 210200 (2031104 bytes)
[INFO ]  CBFS: mcache @0xfefc2e00 built for 14 files, used 0x328 of 0x4000 bytes
[INFO ]  CBFS: Found 'fallback/romstage' @0x80 size 0x112a8 in mcache @0xfefc2e2c
[DEBUG]  BS: bootblock times (exec / console): total (unknown) / 45 ms


[NOTE ]  coreboot-4.15-1556-g9d458a95bd-dirty Mon Feb 14 19:27:41 UTC 2022 romstage starting (log level: 8)...
[DEBUG]  Setting up static southbridge registers... done.
[DEBUG]  Disabling Watchdog reboot... done.
[DEBUG]  Setting up static northbridge registers... done.
[DEBUG]  SMBus controller enabled
[DEBUG]  Setting up Chipset Initialization Registers (CIR)
[DEBUG]  Scratchpad MCHBAR8(0x2ca8): 0x0004
[INFO ]  Intel ME early init
[INFO ]  Intel ME firmware is ready
[DEBUG]  ME: Requested 32MB UMA
[DEBUG]  CAPID0[0] = 0x010c0009
[DEBUG]  CAPID0[1] = 0x00b16126
[DEBUG]  CAPID0[2] = 0x00400088
[DEBUG]  Revision ID: 0x18
[DEBUG]  Device ID: 0x44
[DEBUG]  FMAP: area RW_MRC_CACHE found @ 200000 (65536 bytes)
[ERROR]  MRC: no data in 'RW_MRC_CACHE'
[DEBUG]  i = 0, result = 0xc017
[DEBUG]  i = 1, result = 0xc01b
[DEBUG]  385: EGAV: 0
[DEBUG]  388: EGAV: ff
[DEBUG]  390: EGAV: ff
[DEBUG]  i = 0, result = 0xc037
[DEBUG]  i = 1, result = 0xc03b
[DEBUG]  385: EGAV: 0
[DEBUG]  388: EGAV: ff
[DEBUG]  390: EGAV: ff
[DEBUG]  i = 0, result = 0xc017
[DEBUG]  i = 1, result = 0xc01b
[DEBUG]  385: EGAV: 0
[DEBUG]  388: EGAV: ff
[DEBUG]  390: EGAV: ff
[DEBUG]  i = 0, result = 0xc037
[DEBUG]  i = 1, result = 0xc03b
[DEBUG]  385: EGAV: 0
[DEBUG]  388: EGAV: ff
[DEBUG]  390: EGAV: ff
[SPEW ]  Timings 3061:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   21 (  32)  139 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   21 (  32)  125 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   21 (  32)  146 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   21 (  32)  110 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   21 (  32)  211 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   21 (  32)  201 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   21 (  32)  202 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   21 (  32)  139 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   21 (  32)  123 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   21 (  32)  144 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   21 (  32)  107 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   21 (  32)  209 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   21 (  32)  196 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   21 (  32)  198 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   21 (  32)  144 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   21 (  32)  134 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   21 (  32)  154 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   21 (  32)  115 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   21 (  32)  213 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   21 (  32)  172 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   21 (  32)  199 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   21 (  32)  197 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   21 (  32)  139 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   21 (  32)  129 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   21 (  32)  147 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   21 (  32)  113 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   21 (  32)  209 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   21 (  32)  192 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   21 (  32)  194 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =    0 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  ################################################################
[SPEW ]  # Training step 1: Sweep reg178 to choose a center value       #
[SPEW ]  ################################################################

[SPEW ]  reg178_min  = 3
[SPEW ]  reg178_max  = 60
[SPEW ]  reg178_step = 4

[SPEW ]  REG_178 = 3

[SPEW ]  REG_178 = 7

[SPEW ]  REG_178 = 11

[SPEW ]  REG_178 = 15

[SPEW ]  REG_178 = 19

[SPEW ]  REG_178 = 23

[SPEW ]  REG_178 = 27

[SPEW ]  REG_178 = 31

[SPEW ]  REG_178 = 35

[SPEW ]  REG_178 = 39

[SPEW ]  REG_178 = 43

[SPEW ]  REG_178 = 47

[SPEW ]  REG_178 = 51

[SPEW ]  REG_178 = 55

[SPEW ]  REG_178 = 59

[DEBUG]  r178	   0   1   2   3   4   5   6   7	   0   1   2   3   4   5   6   7
[DEBUG]  3	  24  22  27  27  27  25  25  24	  23  20  26  26  26  27  26  24	  30  27  30  31  28  28  26  24	  27  27  28  29  28  29  26  25
[DEBUG]  7	  25  24  28  29  29  27  27  26	  26  22  29  28  28  27  27  26	  31  30  32  31  31  31  28  28	  29  28  29  30  31  32  29  28
[DEBUG]  11	  29  25  30  31  30  30  29  27	  27  25  30  30  29  31  30  29	  32  31  35  32  33  34  30  29	  30  31  32  32  32  35  31  29
[DEBUG]  15	  30  27  31  32  32  33  31  31	  29  27  32  31  31  33  32  30	  33  34  36  34  34  36  32  31	  31  33  35  33  33  37  33  31
[DEBUG]  19	  32  29  31  33  34  36  33  32	  30  28  32  32  32  36  34  32	  34  35  38  35  36  38  33  32	  32  34  36  34  35  38  35  32
[DEBUG]  23	  32  30  33  34  34  38  34  34	  32  30  34  34  33  38  36  34	  34  37  39  37  38  39  35  33	  34  37  38  36  36  39  35  33
[DEBUG]  27	  34  29  35  34  36  39  36  37	  33  30  34  34  34  39  36  37	  36  39  40  37  39  40  36  34	  34  38  39  36  37  40  38  34
[DEBUG]  31	  34  28  33  34  36  39  35  36	  32  29  33  35  34  39  38  36	  35  39  39  37  39  40  36  33	  35  38  39  37  37  38  39  35
[DEBUG]  35	  32  25  32  34  34  37  33  34	  31  28  33  33  33  38  36  33	  34  37  38  36  36  39  35  32	  34  37  38  37  35  38  37  34
[DEBUG]  39	  31  24  31  33  34  36  33  33	  30  27  32  33  32  37  34  32	  33  35  37  34  35  38  33  31	  33  35  37  34  33  37  36  32
[DEBUG]  43	  30  22  31  32  32  34  31  31	  29  26  31  31  31  35  33  31	  31  34  35  34  33  37  33  31	  32  33  35  34  33  33  34  32
[DEBUG]  47	  28  20  30  31  31  32  30  29	  28  22  30  30  31  33  31  30	  31  32  34  32  32  34  31  30	  31  32  34  32  32  32  32  30
[DEBUG]  51	  27  18  28  31  30  31  28  27	  26  22  28  30  29  30  30  27	  29  30  32  32  31  33  30  28	  29  30  31  32  30  32  30  29
[DEBUG]  55	  24  18  27  29  28  27  26  26	  22  21  27  28  28  27  27  25	  28  27  30  31  28  30  27  26	  28  27  29  30  29  29  29  27
[DEBUG]  59	  24  16  24  28  26  25  25  24	  21  19  26  26  25  25  26  24	  26  27  29  29  26  27  26  24	  26  27  27  29  26  28  26  25

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[DEBUG]  35	##................................##############
[DEBUG]  39	###...............................##############
[DEBUG]  43	###...............................##############
[DEBUG]  47	####..............................##############
[DEBUG]  51	#####............................###############
[DEBUG]  55	######...........................###############
[DEBUG]  59	########........................################
[DEBUG]  Lane 3:
[DEBUG]  3	######...........................###############
[DEBUG]  7	#####.............................##############
[DEBUG]  11	####...............................#############
[DEBUG]  15	###................................#############
[DEBUG]  19	##.................................#############
[DEBUG]  23	##..................................############
[DEBUG]  27	#..................................#############
[DEBUG]  31	#..................................#############
[DEBUG]  35	#..................................#############
[DEBUG]  39	##.................................#############
[DEBUG]  43	##................................##############
[DEBUG]  47	###...............................##############
[DEBUG]  51	###...............................##############
[DEBUG]  55	####.............................###############
[DEBUG]  59	#####............................###############
[DEBUG]  Lane 4:
[DEBUG]  3	#######...........................##############
[DEBUG]  7	#####.............................##############
[DEBUG]  11	####..............................##############
[DEBUG]  15	###................................#############
[DEBUG]  19	##..................................############
[DEBUG]  23	##..................................############
[DEBUG]  27	#....................................###########
[DEBUG]  31	#....................................###########
[DEBUG]  35	##..................................############
[DEBUG]  39	##..................................############
[DEBUG]  43	###................................#############
[DEBUG]  47	###...............................##############
[DEBUG]  51	####..............................##############
[DEBUG]  55	######............................##############
[DEBUG]  59	#######..........................###############
[DEBUG]  Lane 5:
[DEBUG]  3	##########.........................#############
[DEBUG]  7	#########...........................############
[DEBUG]  11	######..............................############
[DEBUG]  15	#####.................................##########
[DEBUG]  19	###....................................#########
[DEBUG]  23	##......................................########
[DEBUG]  27	##.......................................#######
[DEBUG]  31	##.......................................#######
[DEBUG]  35	###.....................................########
[DEBUG]  39	###....................................#########
[DEBUG]  43	####..................................##########
[DEBUG]  47	#####................................###########
[DEBUG]  51	######...............................###########
[DEBUG]  55	#########...........................############
[DEBUG]  59	##########.........................#############
[DEBUG]  Lane 6:
[DEBUG]  3	#########.........................##############
[DEBUG]  7	########...........................#############
[DEBUG]  11	######.............................#############
[DEBUG]  15	#####...............................############
[DEBUG]  19	####.................................###########
[DEBUG]  23	####..................................##########
[DEBUG]  27	###....................................#########
[DEBUG]  31	###...................................##########
[DEBUG]  35	####.................................###########
[DEBUG]  39	####.................................###########
[DEBUG]  43	#####...............................############
[DEBUG]  47	######..............................############
[DEBUG]  51	#######............................#############
[DEBUG]  55	#########..........................#############
[DEBUG]  59	#########.........................##############
[DEBUG]  Lane 7:
[DEBUG]  3	###########........................#############
[DEBUG]  7	#########..........................#############
[DEBUG]  11	#########...........................############
[DEBUG]  15	######...............................###########
[DEBUG]  19	#####................................###########
[DEBUG]  23	####..................................##########
[DEBUG]  27	###.....................................########
[DEBUG]  31	###....................................#########
[DEBUG]  35	####..................................##########
[DEBUG]  39	####.................................###########
[DEBUG]  43	#####...............................############
[DEBUG]  47	#######.............................############
[DEBUG]  51	########...........................#############
[DEBUG]  55	#########..........................#############
[DEBUG]  59	##########........................##############
[DEBUG]  C1R1:
[DEBUG]  Lane 0:
[DEBUG]  3	#########.......................################
[DEBUG]  7	#######..........................###############
[DEBUG]  11	######...........................###############
[DEBUG]  15	#####.............................##############
[DEBUG]  19	####..............................##############
[DEBUG]  23	###................................#############
[DEBUG]  27	##.................................#############
[DEBUG]  31	###................................#############
[DEBUG]  35	###...............................##############
[DEBUG]  39	####..............................##############
[DEBUG]  43	####.............................###############
[DEBUG]  47	#####............................###############
[DEBUG]  51	######..........................################
[DEBUG]  55	########......................##################
[DEBUG]  59	#########.....................##################
[DEBUG]  Lane 1:
[DEBUG]  3	##########....................##################
[DEBUG]  7	#########......................#################
[DEBUG]  11	########.........................###############
[DEBUG]  15	######...........................###############
[DEBUG]  19	#####............................###############
[DEBUG]  23	####..............................##############
[DEBUG]  27	####..............................##############
[DEBUG]  31	#####.............................##############
[DEBUG]  35	#####............................###############
[DEBUG]  39	######...........................###############
[DEBUG]  43	#######..........................###############
[DEBUG]  47	#########......................#################
[DEBUG]  51	#########......................#################
[DEBUG]  55	##########.....................#################
[DEBUG]  59	###########...................##################
[DEBUG]  Lane 2:
[DEBUG]  3	#######..........................###############
[DEBUG]  7	#####.............................##############
[DEBUG]  11	####..............................##############
[DEBUG]  15	###................................#############
[DEBUG]  19	###................................#############
[DEBUG]  23	##..................................############
[DEBUG]  27	##..................................############
[DEBUG]  31	##.................................#############
[DEBUG]  35	##.................................#############
[DEBUG]  39	###................................#############
[DEBUG]  43	###...............................##############
[DEBUG]  47	####..............................##############
[DEBUG]  51	#####............................###############
[DEBUG]  55	######...........................###############
[DEBUG]  59	#######..........................###############
[DEBUG]  Lane 3:
[DEBUG]  3	########..........................##############
[DEBUG]  7	######............................##############
[DEBUG]  11	####..............................##############
[DEBUG]  15	###...............................##############
[DEBUG]  19	###................................#############
[DEBUG]  23	##..................................############
[DEBUG]  27	##..................................############
[DEBUG]  31	#...................................############
[DEBUG]  35	##.................................#############
[DEBUG]  39	##.................................#############
[DEBUG]  43	###...............................##############
[DEBUG]  47	####..............................##############
[DEBUG]  51	####..............................##############
[DEBUG]  55	#####............................###############
[DEBUG]  59	#######..........................###############
[DEBUG]  Lane 4:
[DEBUG]  3	#######..........................###############
[DEBUG]  7	#####............................###############
[DEBUG]  11	####.............................###############
[DEBUG]  15	###...............................##############
[DEBUG]  19	##................................##############
[DEBUG]  23	##.................................#############
[DEBUG]  27	#..................................#############
[DEBUG]  31	#..................................#############
[DEBUG]  35	##.................................#############
[DEBUG]  39	##................................##############
[DEBUG]  43	###...............................##############
[DEBUG]  47	###...............................##############
[DEBUG]  51	####.............................###############
[DEBUG]  55	#####............................###############
[DEBUG]  59	#######.........................################
[DEBUG]  Lane 5:
[DEBUG]  3	#########...........................############
[DEBUG]  7	#########...........................############
[DEBUG]  11	######...............................###########
[DEBUG]  15	#####.................................##########
[DEBUG]  19	###....................................#########
[DEBUG]  23	##......................................########
[DEBUG]  27	##.......................................#######
[DEBUG]  31	##.......................................#######
[DEBUG]  35	###......................................#######
[DEBUG]  39	###.....................................########
[DEBUG]  43	####...................................#########
[DEBUG]  47	#####.................................##########
[DEBUG]  51	#######..............................###########
[DEBUG]  55	#########...........................############
[DEBUG]  59	##########.........................#############
[DEBUG]  Lane 6:
[DEBUG]  3	#########..........................#############
[DEBUG]  7	########...........................#############
[DEBUG]  11	######..............................############
[DEBUG]  15	#####................................###########
[DEBUG]  19	####..................................##########
[DEBUG]  23	###....................................#########
[DEBUG]  27	###....................................#########
[DEBUG]  31	##......................................########
[DEBUG]  35	###....................................#########
[DEBUG]  39	####..................................##########
[DEBUG]  43	####.................................###########
[DEBUG]  47	#####...............................############
[DEBUG]  51	######..............................############
[DEBUG]  55	########...........................#############
[DEBUG]  59	#########..........................#############
[DEBUG]  Lane 7:
[DEBUG]  3	##########........................##############
[DEBUG]  7	#########..........................#############
[DEBUG]  11	#######.............................############
[DEBUG]  15	######..............................############
[DEBUG]  19	#####................................###########
[DEBUG]  23	####..................................##########
[DEBUG]  27	###.....................................########
[DEBUG]  31	###....................................#########
[DEBUG]  35	####.................................###########
[DEBUG]  39	#####................................###########
[DEBUG]  43	#####...............................############
[DEBUG]  47	######..............................############
[DEBUG]  51	########...........................#############
[DEBUG]  55	#########.........................##############
[DEBUG]  59	##########........................##############
[SPEW ]  Timings 2548:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   32 (  32)  139 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   32 (  32)  125 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   32 (  32)  146 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   32 (  32)  110 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  211 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  177 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  201 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  202 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  139 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  123 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  144 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  107 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  209 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  177 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  196 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  198 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   32 (  32)  144 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   32 (  32)  134 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   32 (  32)  154 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   32 (  32)  115 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   32 (  32)  213 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   32 (  32)  172 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  199 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   32 (  32)  197 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  139 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   32 (  32)  129 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   32 (  32)  147 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   32 (  32)  113 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  209 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   32 (  32)  169 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  192 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   32 (  32)  194 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   56 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  reg178_center = 28
[DEBUG]  C0R0:
[DEBUG]  Lane 0:
[DEBUG]      smallest[0] = 3
[DEBUG]      largest[0]  = 34
[DEBUG]      smallest[1] = 2
[DEBUG]      largest[1]  = 35
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 150
[DEBUG]      offset      = 182

[DEBUG]  Lane 1:
[DEBUG]      smallest[0] = 6
[DEBUG]      largest[0]  = 36
[DEBUG]      smallest[1] = 3
[DEBUG]      largest[1]  = 39
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 136
[DEBUG]      offset      = 168

[DEBUG]  Lane 2:
[DEBUG]      smallest[0] = 6
[DEBUG]      largest[0]  = 40
[DEBUG]      smallest[1] = 4
[DEBUG]      largest[1]  = 41
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 157
[DEBUG]      offset      = 189

[DEBUG]  Lane 3:
[DEBUG]      smallest[0] = 3
[DEBUG]      largest[0]  = 34
[DEBUG]      smallest[1] = 1
[DEBUG]      largest[1]  = 36
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 121
[DEBUG]      offset      = 153

[DEBUG]  Lane 4:
[DEBUG]      smallest[0] = 4
[DEBUG]      largest[0]  = 36
[DEBUG]      smallest[1] = 3
[DEBUG]      largest[1]  = 38
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 222
[DEBUG]      offset      = 254

[DEBUG]  Lane 5:
[DEBUG]      smallest[0] = 5
[DEBUG]      largest[0]  = 38
[DEBUG]      smallest[1] = 2
[DEBUG]      largest[1]  = 40
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 188
[DEBUG]      offset      = 220

[DEBUG]  Lane 6:
[DEBUG]      smallest[0] = 6
[DEBUG]      largest[0]  = 35
[DEBUG]      smallest[1] = 3
[DEBUG]      largest[1]  = 37
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 212
[DEBUG]      offset      = 244

[DEBUG]  Lane 7:
[DEBUG]      smallest[0] = 5
[DEBUG]      largest[0]  = 33
[DEBUG]      smallest[1] = 2
[DEBUG]      largest[1]  = 33
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 213
[DEBUG]      offset      = 245

[DEBUG]  C0R1:
[DEBUG]  Lane 0:
[DEBUG]      smallest[0] = 4
[DEBUG]      largest[0]  = 33
[DEBUG]      smallest[1] = 2
[DEBUG]      largest[1]  = 35
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 150
[DEBUG]      offset      = 182

[DEBUG]  Lane 1:
[DEBUG]      smallest[0] = 6
[DEBUG]      largest[0]  = 36
[DEBUG]      smallest[1] = 3
[DEBUG]      largest[1]  = 39
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 134
[DEBUG]      offset      = 166

[DEBUG]  Lane 2:
[DEBUG]      smallest[0] = 8
[DEBUG]      largest[0]  = 39
[DEBUG]      smallest[1] = 4
[DEBUG]      largest[1]  = 41
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 155
[DEBUG]      offset      = 187

[DEBUG]  Lane 3:
[DEBUG]      smallest[0] = 3
[DEBUG]      largest[0]  = 34
[DEBUG]      smallest[1] = 1
[DEBUG]      largest[1]  = 37
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 118
[DEBUG]      offset      = 150

[DEBUG]  Lane 4:
[DEBUG]      smallest[0] = 4
[DEBUG]      largest[0]  = 35
[DEBUG]      smallest[1] = 3
[DEBUG]      largest[1]  = 37
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 220
[DEBUG]      offset      = 252

[DEBUG]  Lane 5:
[DEBUG]      smallest[0] = 5
[DEBUG]      largest[0]  = 39
[DEBUG]      smallest[1] = 3
[DEBUG]      largest[1]  = 40
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 188
[DEBUG]      offset      = 220

[DEBUG]  Lane 6:
[DEBUG]      smallest[0] = 5
[DEBUG]      largest[0]  = 35
[DEBUG]      smallest[1] = 3
[DEBUG]      largest[1]  = 39
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 207
[DEBUG]      offset      = 239

[DEBUG]  Lane 7:
[DEBUG]      smallest[0] = 5
[DEBUG]      largest[0]  = 33
[DEBUG]      smallest[1] = 2
[DEBUG]      largest[1]  = 35
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 209
[DEBUG]      offset      = 241

[DEBUG]  C1R0:
[DEBUG]  Lane 0:
[DEBUG]      smallest[0] = 6
[DEBUG]      largest[0]  = 34
[DEBUG]      smallest[1] = 4
[DEBUG]      largest[1]  = 35
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 155
[DEBUG]      offset      = 187

[DEBUG]  Lane 1:
[DEBUG]      smallest[0] = 9
[DEBUG]      largest[0]  = 33
[DEBUG]      smallest[1] = 6
[DEBUG]      largest[1]  = 30
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 145
[DEBUG]      offset      = 177

[DEBUG]  Lane 2:
[DEBUG]      smallest[0] = 4
[DEBUG]      largest[0]  = 33
[DEBUG]      smallest[1] = 2
[DEBUG]      largest[1]  = 33
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 165
[DEBUG]      offset      = 197

[DEBUG]  Lane 3:
[DEBUG]      smallest[0] = 4
[DEBUG]      largest[0]  = 34
[DEBUG]      smallest[1] = 1
[DEBUG]      largest[1]  = 34
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 126
[DEBUG]      offset      = 158

[DEBUG]  Lane 4:
[DEBUG]      smallest[0] = 4
[DEBUG]      largest[0]  = 33
[DEBUG]      smallest[1] = 2
[DEBUG]      largest[1]  = 35
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 224
[DEBUG]      offset      = 256

[DEBUG]  Lane 5:
[DEBUG]      smallest[0] = 6
[DEBUG]      largest[0]  = 35
[DEBUG]      smallest[1] = 3
[DEBUG]      largest[1]  = 39
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 183
[DEBUG]      offset      = 215

[DEBUG]  Lane 6:
[DEBUG]      smallest[0] = 6
[DEBUG]      largest[0]  = 34
[DEBUG]      smallest[1] = 4
[DEBUG]      largest[1]  = 36
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 210
[DEBUG]      offset      = 242

[DEBUG]  Lane 7:
[DEBUG]      smallest[0] = 9
[DEBUG]      largest[0]  = 35
[DEBUG]      smallest[1] = 4
[DEBUG]      largest[1]  = 37
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 208
[DEBUG]      offset      = 240

[DEBUG]  C1R1:
[DEBUG]  Lane 0:
[DEBUG]      smallest[0] = 6
[DEBUG]      largest[0]  = 32
[DEBUG]      smallest[1] = 3
[DEBUG]      largest[1]  = 33
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 150
[DEBUG]      offset      = 182

[DEBUG]  Lane 1:
[DEBUG]      smallest[0] = 8
[DEBUG]      largest[0]  = 32
[DEBUG]      smallest[1] = 5
[DEBUG]      largest[1]  = 32
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 140
[DEBUG]      offset      = 172

[DEBUG]  Lane 2:
[DEBUG]      smallest[0] = 4
[DEBUG]      largest[0]  = 33
[DEBUG]      smallest[1] = 2
[DEBUG]      largest[1]  = 34
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 158
[DEBUG]      offset      = 190

[DEBUG]  Lane 3:
[DEBUG]      smallest[0] = 4
[DEBUG]      largest[0]  = 33
[DEBUG]      smallest[1] = 2
[DEBUG]      largest[1]  = 34
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 124
[DEBUG]      offset      = 156

[DEBUG]  Lane 4:
[DEBUG]      smallest[0] = 4
[DEBUG]      largest[0]  = 32
[DEBUG]      smallest[1] = 2
[DEBUG]      largest[1]  = 34
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 220
[DEBUG]      offset      = 252

[DEBUG]  Lane 5:
[DEBUG]      smallest[0] = 6
[DEBUG]      largest[0]  = 36
[DEBUG]      smallest[1] = 3
[DEBUG]      largest[1]  = 40
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 180
[DEBUG]      offset      = 212

[DEBUG]  Lane 6:
[DEBUG]      smallest[0] = 6
[DEBUG]      largest[0]  = 35
[DEBUG]      smallest[1] = 3
[DEBUG]      largest[1]  = 38
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 203
[DEBUG]      offset      = 235

[DEBUG]  Lane 7:
[DEBUG]      smallest[0] = 7
[DEBUG]      largest[0]  = 35
[DEBUG]      smallest[1] = 4
[DEBUG]      largest[1]  = 36
[DEBUG]      timings[0]  = 32
[DEBUG]      timings[1]  = 205
[DEBUG]      offset      = 237

[SPEW ]  ################################################################
[SPEW ]  # Training step 2: Sweep reg178 while doing something else     #
[SPEW ]  ################################################################
[SPEW ]  REG_178 = 16
[DEBUG]  C1R0:

[DEBUG]  SWEEP
[DEBUG]  Tim	0 1 2 3 4 5 6 7 
[DEBUG]     0	# # # # # # # # 
[DEBUG]     1	# # # # # # # # 
[DEBUG]     2	# # # # # # # # 
[DEBUG]     3	# # . . . # # # 
[DEBUG]     4	# # . . . # # # 
[DEBUG]     5	. # . . . . . # 
[DEBUG]     6	. . . . . . . # 
[DEBUG]     7	. . . . . . . . 
[DEBUG]     8	. . . . . . . . 
[DEBUG]     9	. . . . . . . . 
[DEBUG]    10	. . . . . . . . 
[DEBUG]    11	. . . . . . . . 
[DEBUG]    12	. . . . . . . . 
[DEBUG]    13	. . . . . . . . 
[DEBUG]    14	. . . . . . . . 
[DEBUG]    15	. . . . . . . . 
[DEBUG]    16	. . . . . . . . 
[DEBUG]    17	. . . . . . . . 
[DEBUG]    18	. . . . . . . . 
[DEBUG]    19	. . . . . . . . 
[DEBUG]    20	. . . . . . . . 
[DEBUG]    21	. . . . . . . . 
[DEBUG]    22	. . . . . . . . 
[DEBUG]    23	. . . . . . . . 
[DEBUG]    24	. . . . . . . . 
[DEBUG]    25	. . . . . . . . 
[DEBUG]    26	. . . . . . . . 
[DEBUG]    27	. . . . . . . . 
[DEBUG]    28	. . . . . . . . 
[DEBUG]    29	. . . . . . . . 
[DEBUG]    30	. . . . . . . . 
[DEBUG]    31	. . . . . . . . 
[DEBUG]    32	. . . . . . . . 
[DEBUG]    33	. . . . . . . . 
[DEBUG]    34	. # . . . . . . 
[DEBUG]    35	# # # # # . . . 
[DEBUG]    36	# # # # # . # . 
[DEBUG]    37	# # # # # . # # 
[DEBUG]    38	# # # # # # # # 
[DEBUG]    39	# # # # # # # # 
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[DEBUG]    57	# # # # # # # # 
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[DEBUG]    61	# # # # # # # # 
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[DEBUG]    67	# # # # # # # # 
[DEBUG]    68	# # . . . # # # 
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[DEBUG]    99	. # # # # . . . 
[DEBUG]   100	# # # # # . . # 
[DEBUG]   101	# # # # # . # # 
[DEBUG]   102	# # # # # . # # 
[DEBUG]   103	# # # # # # # # 
[DEBUG]   104	# # # # # # # # 
[DEBUG]   105	# # # # # # # # 
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[DEBUG]   108	# # # # # # # # 
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[DEBUG]   118	# # # # # # # # 
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[DEBUG]   121	# # # # # # # # 
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[DEBUG]   123	# # # # # # # # 
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[DEBUG]   125	# # # # # # # # 
[DEBUG]   126	# # # # # # # # 
[DEBUG]   127	# # # # # # # # 
[DEBUG]  Smallest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]     5 128   6 119   3 136   3  97   3 195   5 156   5 183   7 183
[DEBUG]     5 128   7 120   3 136   3  97   3 195   5 156   5 183   7 183
[DEBUG]     5 128   7 120   3 136   3  97   3 195   5 156   5 183   7 183

[DEBUG]  Largest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]    34 157  33 146  33 166  34 128  34 226  37 188  35 213  36 212
[DEBUG]    34 157  33 146  33 166  34 128  34 226  37 188  35 213  36 212
[DEBUG]    34 157  33 146  33 166  34 128  34 226  37 188  35 213  36 212
[DEBUG]  C1R1:

[DEBUG]  SWEEP
[DEBUG]  Tim	0 1 2 3 4 5 6 7 
[DEBUG]     0	# # # # # # # # 
[DEBUG]     1	# # # # # # # # 
[DEBUG]     2	# # # # # # # # 
[DEBUG]     3	# # . . . # # # 
[DEBUG]     4	. # . . . # # # 
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[DEBUG]     6	. # . . . . . . 
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[DEBUG]    31	. . . . . . . . 
[DEBUG]    32	. . . . . . . . 
[DEBUG]    33	. . . . . . . . 
[DEBUG]    34	# # . . . . . . 
[DEBUG]    35	# # # # # . . . 
[DEBUG]    36	# # # # # . . . 
[DEBUG]    37	# # # # # . # # 
[DEBUG]    38	# # # # # # # # 
[DEBUG]    39	# # # # # # # # 
[DEBUG]    40	# # # # # # # # 
[DEBUG]    41	# # # # # # # # 
[DEBUG]    42	# # # # # # # # 
[DEBUG]    43	# # # # # # # # 
[DEBUG]    44	# # # # # # # # 
[DEBUG]    45	# # # # # # # # 
[DEBUG]    46	# # # # # # # # 
[DEBUG]    47	# # # # # # # # 
[DEBUG]    48	# # # # # # # # 
[DEBUG]    49	# # # # # # # # 
[DEBUG]    50	# # # # # # # # 
[DEBUG]    51	# # # # # # # # 
[DEBUG]    52	# # # # # # # # 
[DEBUG]    53	# # # # # # # # 
[DEBUG]    54	# # # # # # # # 
[DEBUG]    55	# # # # # # # # 
[DEBUG]    56	# # # # # # # # 
[DEBUG]    57	# # # # # # # # 
[DEBUG]    58	# # # # # # # # 
[DEBUG]    59	# # # # # # # # 
[DEBUG]    60	# # # # # # # # 
[DEBUG]    61	# # # # # # # # 
[DEBUG]    62	# # # # # # # # 
[DEBUG]    63	# # # # # # # # 
[DEBUG]    64	# # # # # # # # 
[DEBUG]    65	# # # # # # # # 
[DEBUG]    66	# # # # # # # # 
[DEBUG]    67	# # # # # # # # 
[DEBUG]    68	# # . . . # # # 
[DEBUG]    69	# # . . . # # # 
[DEBUG]    70	. # . . . . . # 
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[DEBUG]    88	. . . . . . . . 
[DEBUG]    89	. . . . . . . . 
[DEBUG]    90	. . . . . . . . 
[DEBUG]    91	. . . . . . . . 
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[DEBUG]    93	. . . . . . . . 
[DEBUG]    94	. . . . . . . . 
[DEBUG]    95	. . . . . . . . 
[DEBUG]    96	. . . . . . . . 
[DEBUG]    97	. . . . . . . . 
[DEBUG]    98	. # . . . . . . 
[DEBUG]    99	# # . . # . . . 
[DEBUG]   100	# # # # # . # # 
[DEBUG]   101	# # # # # . # # 
[DEBUG]   102	# # # # # . # # 
[DEBUG]   103	# # # # # # # # 
[DEBUG]   104	# # # # # # # # 
[DEBUG]   105	# # # # # # # # 
[DEBUG]   106	# # # # # # # # 
[DEBUG]   107	# # # # # # # # 
[DEBUG]   108	# # # # # # # # 
[DEBUG]   109	# # # # # # # # 
[DEBUG]   110	# # # # # # # # 
[DEBUG]   111	# # # # # # # # 
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[DEBUG]   114	# # # # # # # # 
[DEBUG]   115	# # # # # # # # 
[DEBUG]   116	# # # # # # # # 
[DEBUG]   117	# # # # # # # # 
[DEBUG]   118	# # # # # # # # 
[DEBUG]   119	# # # # # # # # 
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[DEBUG]   121	# # # # # # # # 
[DEBUG]   122	# # # # # # # # 
[DEBUG]   123	# # # # # # # # 
[DEBUG]   124	# # # # # # # # 
[DEBUG]   125	# # # # # # # # 
[DEBUG]   126	# # # # # # # # 
[DEBUG]   127	# # # # # # # # 
[DEBUG]  Smallest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]     4 122   6 114   3 129   3  95   3 191   5 153   5 176   6 179
[DEBUG]     4 122   7 115   3 129   3  95   3 191   5 153   5 176   6 179
[DEBUG]     4 122   7 115   3 129   3  95   3 191   5 153   5 176   6 179

[DEBUG]  Largest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]    33 151  32 140  34 160  34 126  33 221  37 185  36 207  35 208
[DEBUG]    33 151  32 140  34 160  34 126  33 221  37 185  35 206  35 208
[DEBUG]    33 151  32 140  33 159  34 126  33 221  37 185  35 206  35 208
[DEBUG]    33 151  32 140  33 159  34 126  33 221  37 185  35 206  35 208
[DEBUG]    33 151  32 140  33 159  34 126  33 221  37 185  35 206  35 208
[DEBUG]  C0R0:

[DEBUG]  SWEEP
[DEBUG]  Tim	0 1 2 3 4 5 6 7 
[DEBUG]     0	# # # # # # # # 
[DEBUG]     1	# # # # # # # # 
[DEBUG]     2	# # # # # # # # 
[DEBUG]     3	. # # . # # # # 
[DEBUG]     4	. . # . . . # . 
[DEBUG]     5	. . . . . . . . 
[DEBUG]     6	. . . . . . . . 
[DEBUG]     7	. . . . . . . . 
[DEBUG]     8	. . . . . . . . 
[DEBUG]     9	. . . . . . . . 
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[DEBUG]    11	. . . . . . . . 
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[DEBUG]    14	. . . . . . . . 
[DEBUG]    15	. . . . . . . . 
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[DEBUG]    21	. . . . . . . . 
[DEBUG]    22	. . . . . . . . 
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[DEBUG]    24	. . . . . . . . 
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[DEBUG]    29	. . . . . . . . 
[DEBUG]    30	. . . . . . . . 
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[DEBUG]    32	. . . . . . . . 
[DEBUG]    33	. . . . . . . . 
[DEBUG]    34	. . . . . . . . 
[DEBUG]    35	. . . . . . . # 
[DEBUG]    36	# . . . . . . # 
[DEBUG]    37	# . . # . . # # 
[DEBUG]    38	# . . # # . # # 
[DEBUG]    39	# . . # # . # # 
[DEBUG]    40	# # . # # . # # 
[DEBUG]    41	# # . # # # # # 
[DEBUG]    42	# # # # # # # # 
[DEBUG]    43	# # # # # # # # 
[DEBUG]    44	# # # # # # # # 
[DEBUG]    45	# # # # # # # # 
[DEBUG]    46	# # # # # # # # 
[DEBUG]    47	# # # # # # # # 
[DEBUG]    48	# # # # # # # # 
[DEBUG]    49	# # # # # # # # 
[DEBUG]    50	# # # # # # # # 
[DEBUG]    51	# # # # # # # # 
[DEBUG]    52	# # # # # # # # 
[DEBUG]    53	# # # # # # # # 
[DEBUG]    54	# # # # # # # # 
[DEBUG]    55	# # # # # # # # 
[DEBUG]    56	# # # # # # # # 
[DEBUG]    57	# # # # # # # # 
[DEBUG]    58	# # # # # # # # 
[DEBUG]    59	# # # # # # # # 
[DEBUG]    60	# # # # # # # # 
[DEBUG]    61	# # # # # # # # 
[DEBUG]    62	# # # # # # # # 
[DEBUG]    63	# # # # # # # # 
[DEBUG]    64	# # # # # # # # 
[DEBUG]    65	# # # # # # # # 
[DEBUG]    66	# # # # # # # # 
[DEBUG]    67	# # # . # # # # 
[DEBUG]    68	. # # . # # # # 
[DEBUG]    69	. # # . . . # . 
[DEBUG]    70	. . . . . . . . 
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[DEBUG]    73	. . . . . . . . 
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[DEBUG]    87	. . . . . . . . 
[DEBUG]    88	. . . . . . . . 
[DEBUG]    89	. . . . . . . . 
[DEBUG]    90	. . . . . . . . 
[DEBUG]    91	. . . . . . . . 
[DEBUG]    92	. . . . . . . . 
[DEBUG]    93	. . . . . . . . 
[DEBUG]    94	. . . . . . . . 
[DEBUG]    95	. . . . . . . . 
[DEBUG]    96	. . . . . . . . 
[DEBUG]    97	. . . . . . . . 
[DEBUG]    98	. . . . . . . . 
[DEBUG]    99	. . . . . . . # 
[DEBUG]   100	# . . # . . . # 
[DEBUG]   101	# . . # . . # # 
[DEBUG]   102	# # . # # . # # 
[DEBUG]   103	# # . # # . # # 
[DEBUG]   104	# # . # # . # # 
[DEBUG]   105	# # . # # # # # 
[DEBUG]   106	# # # # # # # # 
[DEBUG]   107	# # # # # # # # 
[DEBUG]   108	# # # # # # # # 
[DEBUG]   109	# # # # # # # # 
[DEBUG]   110	# # # # # # # # 
[DEBUG]   111	# # # # # # # # 
[DEBUG]   112	# # # # # # # # 
[DEBUG]   113	# # # # # # # # 
[DEBUG]   114	# # # # # # # # 
[DEBUG]   115	# # # # # # # # 
[DEBUG]   116	# # # # # # # # 
[DEBUG]   117	# # # # # # # # 
[DEBUG]   118	# # # # # # # # 
[DEBUG]   119	# # # # # # # # 
[DEBUG]   120	# # # # # # # # 
[DEBUG]   121	# # # # # # # # 
[DEBUG]   122	# # # # # # # # 
[DEBUG]   123	# # # # # # # # 
[DEBUG]   124	# # # # # # # # 
[DEBUG]   125	# # # # # # # # 
[DEBUG]   126	# # # # # # # # 
[DEBUG]   127	# # # # # # # # 
[DEBUG]  Smallest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]     2 120   4 108   5 130   2  91   3 193   4 160   5 185   4 185
[DEBUG]     3 121   4 108   5 130   2  91   3 193   4 160   5 185   4 185
[DEBUG]     3 121   4 108   5 130   2  91   4 194   4 160   5 185   4 185
[DEBUG]     3 121   4 108   5 130   2  91   4 194   4 160   5 185   4 185

[DEBUG]  Largest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]    35 153  37 141  41 166  35 124  37 227  40 196  36 216  34 215
[DEBUG]    35 153  37 141  41 166  35 124  37 227  40 196  36 216  34 215
[DEBUG]    35 153  37 141  41 166  35 124  37 227  40 196  36 216  34 215
[DEBUG]  C0R1:

[DEBUG]  SWEEP
[DEBUG]  Tim	0 1 2 3 4 5 6 7 
[DEBUG]     0	# # # # # # # # 
[DEBUG]     1	# # # # # # # # 
[DEBUG]     2	# # # . # # # # 
[DEBUG]     3	. # # . # # # # 
[DEBUG]     4	. # # . . # . . 
[DEBUG]     5	. . # . . . . . 
[DEBUG]     6	. . . . . . . . 
[DEBUG]     7	. . . . . . . . 
[DEBUG]     8	. . . . . . . . 
[DEBUG]     9	. . . . . . . . 
[DEBUG]    10	. . . . . . . . 
[DEBUG]    11	. . . . . . . . 
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[DEBUG]    15	. . . . . . . . 
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[DEBUG]    22	. . . . . . . . 
[DEBUG]    23	. . . . . . . . 
[DEBUG]    24	. . . . . . . . 
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[DEBUG]    27	. . . . . . . . 
[DEBUG]    28	. . . . . . . . 
[DEBUG]    29	. . . . . . . . 
[DEBUG]    30	. . . . . . . . 
[DEBUG]    31	. . . . . . . . 
[DEBUG]    32	. . . . . . . . 
[DEBUG]    33	. . . . . . . . 
[DEBUG]    34	. . . . . . . . 
[DEBUG]    35	# . . . . . . # 
[DEBUG]    36	# . . # . . . # 
[DEBUG]    37	# . . # # . # # 
[DEBUG]    38	# # . # # . # # 
[DEBUG]    39	# # . # # . # # 
[DEBUG]    40	# # . # # . # # 
[DEBUG]    41	# # # # # # # # 
[DEBUG]    42	# # # # # # # # 
[DEBUG]    43	# # # # # # # # 
[DEBUG]    44	# # # # # # # # 
[DEBUG]    45	# # # # # # # # 
[DEBUG]    46	# # # # # # # # 
[DEBUG]    47	# # # # # # # # 
[DEBUG]    48	# # # # # # # # 
[DEBUG]    49	# # # # # # # # 
[DEBUG]    50	# # # # # # # # 
[DEBUG]    51	# # # # # # # # 
[DEBUG]    52	# # # # # # # # 
[DEBUG]    53	# # # # # # # # 
[DEBUG]    54	# # # # # # # # 
[DEBUG]    55	# # # # # # # # 
[DEBUG]    56	# # # # # # # # 
[DEBUG]    57	# # # # # # # # 
[DEBUG]    58	# # # # # # # # 
[DEBUG]    59	# # # # # # # # 
[DEBUG]    60	# # # # # # # # 
[DEBUG]    61	# # # # # # # # 
[DEBUG]    62	# # # # # # # # 
[DEBUG]    63	# # # # # # # # 
[DEBUG]    64	# # # # # # # # 
[DEBUG]    65	# # # # # # # # 
[DEBUG]    66	# # # # # # # # 
[DEBUG]    67	# # # . # # # # 
[DEBUG]    68	. # # . # # # # 
[DEBUG]    69	. # # . . # # . 
[DEBUG]    70	. . # . . . . . 
[DEBUG]    71	. . . . . . . . 
[DEBUG]    72	. . . . . . . . 
[DEBUG]    73	. . . . . . . . 
[DEBUG]    74	. . . . . . . . 
[DEBUG]    75	. . . . . . . . 
[DEBUG]    76	. . . . . . . . 
[DEBUG]    77	. . . . . . . . 
[DEBUG]    78	. . . . . . . . 
[DEBUG]    79	. . . . . . . . 
[DEBUG]    80	. . . . . . . . 
[DEBUG]    81	. . . . . . . . 
[DEBUG]    82	. . . . . . . . 
[DEBUG]    83	. . . . . . . . 
[DEBUG]    84	. . . . . . . . 
[DEBUG]    85	. . . . . . . . 
[DEBUG]    86	. . . . . . . . 
[DEBUG]    87	. . . . . . . . 
[DEBUG]    88	. . . . . . . . 
[DEBUG]    89	. . . . . . . . 
[DEBUG]    90	. . . . . . . . 
[DEBUG]    91	. . . . . . . . 
[DEBUG]    92	. . . . . . . . 
[DEBUG]    93	. . . . . . . . 
[DEBUG]    94	. . . . . . . . 
[DEBUG]    95	. . . . . . . . 
[DEBUG]    96	. . . . . . . . 
[DEBUG]    97	. . . . . . . . 
[DEBUG]    98	# . . . . . . . 
[DEBUG]    99	# . . . . . . . 
[DEBUG]   100	# . . . # . . # 
[DEBUG]   101	# . . # # . # # 
[DEBUG]   102	# . . # # . # # 
[DEBUG]   103	# . . # # . # # 
[DEBUG]   104	# # . # # . # # 
[DEBUG]   105	# # # # # # # # 
[DEBUG]   106	# # # # # # # # 
[DEBUG]   107	# # # # # # # # 
[DEBUG]   108	# # # # # # # # 
[DEBUG]   109	# # # # # # # # 
[DEBUG]   110	# # # # # # # # 
[DEBUG]   111	# # # # # # # # 
[DEBUG]   112	# # # # # # # # 
[DEBUG]   113	# # # # # # # # 
[DEBUG]   114	# # # # # # # # 
[DEBUG]   115	# # # # # # # # 
[DEBUG]   116	# # # # # # # # 
[DEBUG]   117	# # # # # # # # 
[DEBUG]   118	# # # # # # # # 
[DEBUG]   119	# # # # # # # # 
[DEBUG]   120	# # # # # # # # 
[DEBUG]   121	# # # # # # # # 
[DEBUG]   122	# # # # # # # # 
[DEBUG]   123	# # # # # # # # 
[DEBUG]   124	# # # # # # # # 
[DEBUG]   125	# # # # # # # # 
[DEBUG]   126	# # # # # # # # 
[DEBUG]   127	# # # # # # # # 
[DEBUG]  Smallest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]     3 121   5 107   5 128   2  88   4 192   5 161   4 179   4 181
[DEBUG]     4 122   5 107   6 129   2  88   4 192   5 161   5 180   4 181
[DEBUG]     4 122   5 107   6 129   2  88   4 192   5 161   5 180   4 181

[DEBUG]  Largest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]    34 152  37 139  40 163  34 120  36 224  40 196  36 211  34 211
[DEBUG]    34 152  37 139  40 163  34 120  36 224  40 196  36 211  34 211
[DEBUG]    34 152  37 139  40 163  34 120  36 224  40 196  36 211  34 211
[SPEW ]  REG_178 = 28
[DEBUG]  C1R0:

[DEBUG]  SWEEP
[DEBUG]  Tim	0 1 2 3 4 5 6 7 
[DEBUG]     0	# # # # # # # # 
[DEBUG]     1	# # # . # # # # 
[DEBUG]     2	# # . . . . # # 
[DEBUG]     3	. # . . . . . # 
[DEBUG]     4	. # . . . . . . 
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[DEBUG]     6	. . . . . . . . 
[DEBUG]     7	. . . . . . . . 
[DEBUG]     8	. . . . . . . . 
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[DEBUG]    11	. . . . . . . . 
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[DEBUG]    22	. . . . . . . . 
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[DEBUG]    24	. . . . . . . . 
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[DEBUG]    31	. . . . . . . . 
[DEBUG]    32	. . . . . . . . 
[DEBUG]    33	. . . . . . . . 
[DEBUG]    34	. . . . . . . . 
[DEBUG]    35	. # . . . . . . 
[DEBUG]    36	. # # # . . . . 
[DEBUG]    37	# # # # # . . . 
[DEBUG]    38	# # # # # . . . 
[DEBUG]    39	# # # # # . # . 
[DEBUG]    40	# # # # # . # # 
[DEBUG]    41	# # # # # # # # 
[DEBUG]    42	# # # # # # # # 
[DEBUG]    43	# # # # # # # # 
[DEBUG]    44	# # # # # # # # 
[DEBUG]    45	# # # # # # # # 
[DEBUG]    46	# # # # # # # # 
[DEBUG]    47	# # # # # # # # 
[DEBUG]    48	# # # # # # # # 
[DEBUG]    49	# # # # # # # # 
[DEBUG]    50	# # # # # # # # 
[DEBUG]    51	# # # # # # # # 
[DEBUG]    52	# # # # # # # # 
[DEBUG]    53	# # # # # # # # 
[DEBUG]    54	# # # # # # # # 
[DEBUG]    55	# # # # # # # # 
[DEBUG]    56	# # # # # # # # 
[DEBUG]    57	# # # # # # # # 
[DEBUG]    58	# # # # # # # # 
[DEBUG]    59	# # # # # # # # 
[DEBUG]    60	# # # # # # # # 
[DEBUG]    61	# # # # # # # # 
[DEBUG]    62	# # # # # # # # 
[DEBUG]    63	# # # # # # # # 
[DEBUG]    64	# # # # # # # # 
[DEBUG]    65	# # # # # # # # 
[DEBUG]    66	# # . . . # # # 
[DEBUG]    67	# # . . . . # # 
[DEBUG]    68	. # . . . . . . 
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[DEBUG]    72	. . . . . . . . 
[DEBUG]    73	. . . . . . . . 
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[DEBUG]    86	. . . . . . . . 
[DEBUG]    87	. . . . . . . . 
[DEBUG]    88	. . . . . . . . 
[DEBUG]    89	. . . . . . . . 
[DEBUG]    90	. . . . . . . . 
[DEBUG]    91	. . . . . . . . 
[DEBUG]    92	. . . . . . . . 
[DEBUG]    93	. . . . . . . . 
[DEBUG]    94	. . . . . . . . 
[DEBUG]    95	. . . . . . . . 
[DEBUG]    96	. . . . . . . . 
[DEBUG]    97	. . . . . . . . 
[DEBUG]    98	. . . # . . . . 
[DEBUG]    99	. . . # . . . . 
[DEBUG]   100	. # . # . . . . 
[DEBUG]   101	. # # # # . . . 
[DEBUG]   102	# # # # # . . . 
[DEBUG]   103	# # # # # . . . 
[DEBUG]   104	# # # # # . # # 
[DEBUG]   105	# # # # # # # # 
[DEBUG]   106	# # # # # # # # 
[DEBUG]   107	# # # # # # # # 
[DEBUG]   108	# # # # # # # # 
[DEBUG]   109	# # # # # # # # 
[DEBUG]   110	# # # # # # # # 
[DEBUG]   111	# # # # # # # # 
[DEBUG]   112	# # # # # # # # 
[DEBUG]   113	# # # # # # # # 
[DEBUG]   114	# # # # # # # # 
[DEBUG]   115	# # # # # # # # 
[DEBUG]   116	# # # # # # # # 
[DEBUG]   117	# # # # # # # # 
[DEBUG]   118	# # # # # # # # 
[DEBUG]   119	# # # # # # # # 
[DEBUG]   120	# # # # # # # # 
[DEBUG]   121	# # # # # # # # 
[DEBUG]   122	# # # # # # # # 
[DEBUG]   123	# # # # # # # # 
[DEBUG]   124	# # # # # # # # 
[DEBUG]   125	# # # # # # # # 
[DEBUG]   126	# # # # # # # # 
[DEBUG]   127	# # # # # # # # 
[DEBUG]  Smallest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]     3 126   4 117   2 135   1  95   1 193   2 153   3 181   3 179
[DEBUG]     3 126   5 118   2 135   1  95   2 194   2 153   3 181   3 179
[DEBUG]     3 126   6 119   2 135   1  95   2 194   2 153   3 181   3 179
[DEBUG]     3 126   6 119   2 135   1  95   2 194   2 153   3 181   3 179

[DEBUG]  Largest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]    36 159  33 146  35 168  35 129  36 228  40 191  37 215  39 215
[DEBUG]    36 159  33 146  35 168  35 129  36 228  40 191  37 215  39 215
[DEBUG]    36 159  33 146  35 168  35 129  36 228  40 191  37 215  39 215
[DEBUG]  C1R1:

[DEBUG]  SWEEP
[DEBUG]  Tim	0 1 2 3 4 5 6 7 
[DEBUG]     0	# # # # # # # # 
[DEBUG]     1	# # # # . # # # 
[DEBUG]     2	. # . . . . # # 
[DEBUG]     3	. # . . . . . . 
[DEBUG]     4	. # . . . . . . 
[DEBUG]     5	. . . . . . . . 
[DEBUG]     6	. . . . . . . . 
[DEBUG]     7	. . . . . . . . 
[DEBUG]     8	. . . . . . . . 
[DEBUG]     9	. . . . . . . . 
[DEBUG]    10	. . . . . . . . 
[DEBUG]    11	. . . . . . . . 
[DEBUG]    12	. . . . . . . . 
[DEBUG]    13	. . . . . . . . 
[DEBUG]    14	. . . . . . . . 
[DEBUG]    15	. . . . . . . . 
[DEBUG]    16	. . . . . . . . 
[DEBUG]    17	. . . . . . . . 
[DEBUG]    18	. . . . . . . . 
[DEBUG]    19	. . . . . . . . 
[DEBUG]    20	. . . . . . . . 
[DEBUG]    21	. . . . . . . . 
[DEBUG]    22	. . . . . . . . 
[DEBUG]    23	. . . . . . . . 
[DEBUG]    24	. . . . . . . . 
[DEBUG]    25	. . . . . . . . 
[DEBUG]    26	. . . . . . . . 
[DEBUG]    27	. . . . . . . . 
[DEBUG]    28	. . . . . . . . 
[DEBUG]    29	. . . . . . . . 
[DEBUG]    30	. . . . . . . . 
[DEBUG]    31	. . . . . . . . 
[DEBUG]    32	. . . . . . . . 
[DEBUG]    33	. . . . . . . . 
[DEBUG]    34	. . . . . . . . 
[DEBUG]    35	# . . . . . . . 
[DEBUG]    36	# # # # # . . . 
[DEBUG]    37	# # # # # . . . 
[DEBUG]    38	# # # # # . . . 
[DEBUG]    39	# # # # # . . . 
[DEBUG]    40	# # # # # . # . 
[DEBUG]    41	# # # # # # # # 
[DEBUG]    42	# # # # # # # # 
[DEBUG]    43	# # # # # # # # 
[DEBUG]    44	# # # # # # # # 
[DEBUG]    45	# # # # # # # # 
[DEBUG]    46	# # # # # # # # 
[DEBUG]    47	# # # # # # # # 
[DEBUG]    48	# # # # # # # # 
[DEBUG]    49	# # # # # # # # 
[DEBUG]    50	# # # # # # # # 
[DEBUG]    51	# # # # # # # # 
[DEBUG]    52	# # # # # # # # 
[DEBUG]    53	# # # # # # # # 
[DEBUG]    54	# # # # # # # # 
[DEBUG]    55	# # # # # # # # 
[DEBUG]    56	# # # # # # # # 
[DEBUG]    57	# # # # # # # # 
[DEBUG]    58	# # # # # # # # 
[DEBUG]    59	# # # # # # # # 
[DEBUG]    60	# # # # # # # # 
[DEBUG]    61	# # # # # # # # 
[DEBUG]    62	# # # # # # # # 
[DEBUG]    63	# # # # # # # # 
[DEBUG]    64	# # # # # # # # 
[DEBUG]    65	# # # # # # # # 
[DEBUG]    66	# # . . . # # # 
[DEBUG]    67	. # . . . . # # 
[DEBUG]    68	. . . . . . . . 
[DEBUG]    69	. . . . . . . . 
[DEBUG]    70	. . . . . . . . 
[DEBUG]    71	. . . . . . . . 
[DEBUG]    72	. . . . . . . . 
[DEBUG]    73	. . . . . . . . 
[DEBUG]    74	. . . . . . . . 
[DEBUG]    75	. . . . . . . . 
[DEBUG]    76	. . . . . . . . 
[DEBUG]    77	. . . . . . . . 
[DEBUG]    78	. . . . . . . . 
[DEBUG]    79	. . . . . . . . 
[DEBUG]    80	. . . . . . . . 
[DEBUG]    81	. . . . . . . . 
[DEBUG]    82	. . . . . . . . 
[DEBUG]    83	. . . . . . . . 
[DEBUG]    84	. . . . . . . . 
[DEBUG]    85	. . . . . . . . 
[DEBUG]    86	. . . . . . . . 
[DEBUG]    87	. . . . . . . . 
[DEBUG]    88	. . . . . . . . 
[DEBUG]    89	. . . . . . . . 
[DEBUG]    90	. . . . . . . . 
[DEBUG]    91	. . . . . . . . 
[DEBUG]    92	. . . . . . . . 
[DEBUG]    93	. . . . . . . . 
[DEBUG]    94	. . . . . . . . 
[DEBUG]    95	. . . . . . . . 
[DEBUG]    96	. . . . . . . . 
[DEBUG]    97	. . . . . . . . 
[DEBUG]    98	. . . . . . . . 
[DEBUG]    99	. # . . . . . . 
[DEBUG]   100	# # . # . . . . 
[DEBUG]   101	# # . # # . . . 
[DEBUG]   102	# # # # # . . . 
[DEBUG]   103	# # # # # . # # 
[DEBUG]   104	# # # # # . # # 
[DEBUG]   105	# # # # # . # # 
[DEBUG]   106	# # # # # # # # 
[DEBUG]   107	# # # # # # # # 
[DEBUG]   108	# # # # # # # # 
[DEBUG]   109	# # # # # # # # 
[DEBUG]   110	# # # # # # # # 
[DEBUG]   111	# # # # # # # # 
[DEBUG]   112	# # # # # # # # 
[DEBUG]   113	# # # # # # # # 
[DEBUG]   114	# # # # # # # # 
[DEBUG]   115	# # # # # # # # 
[DEBUG]   116	# # # # # # # # 
[DEBUG]   117	# # # # # # # # 
[DEBUG]   118	# # # # # # # # 
[DEBUG]   119	# # # # # # # # 
[DEBUG]   120	# # # # # # # # 
[DEBUG]   121	# # # # # # # # 
[DEBUG]   122	# # # # # # # # 
[DEBUG]   123	# # # # # # # # 
[DEBUG]   124	# # # # # # # # 
[DEBUG]   125	# # # # # # # # 
[DEBUG]   126	# # # # # # # # 
[DEBUG]   127	# # # # # # # # 
[DEBUG]  Smallest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]     2 120   4 112   1 127   2  94   1 189   2 150   3 174   3 176
[DEBUG]     2 120   5 113   1 127   2  94   1 189   2 150   3 174   3 176
[DEBUG]     2 120   5 113   2 128   2  94   1 189   2 150   3 174   3 176
[DEBUG]     2 120   5 113   2 128   2  94   1 189   2 150   3 174   3 176

[DEBUG]  Largest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]    34 152  33 141  35 161  35 127  35 223  40 188  39 210  38 211
[DEBUG]    34 152  33 141  35 161  35 127  35 223  40 188  39 210  38 211
[DEBUG]    34 152  33 141  35 161  35 127  35 223  40 188  39 210  38 211
[DEBUG]  C0R0:

[DEBUG]  SWEEP
[DEBUG]  Tim	0 1 2 3 4 5 6 7 
[DEBUG]     0	# # # # # # # # 
[DEBUG]     1	# # # . # # # # 
[DEBUG]     2	. . # . . . # . 
[DEBUG]     3	. . . . . . . . 
[DEBUG]     4	. . . . . . . . 
[DEBUG]     5	. . . . . . . . 
[DEBUG]     6	. . . . . . . . 
[DEBUG]     7	. . . . . . . . 
[DEBUG]     8	. . . . . . . . 
[DEBUG]     9	. . . . . . . . 
[DEBUG]    10	. . . . . . . . 
[DEBUG]    11	. . . . . . . . 
[DEBUG]    12	. . . . . . . . 
[DEBUG]    13	. . . . . . . . 
[DEBUG]    14	. . . . . . . . 
[DEBUG]    15	. . . . . . . . 
[DEBUG]    16	. . . . . . . . 
[DEBUG]    17	. . . . . . . . 
[DEBUG]    18	. . . . . . . . 
[DEBUG]    19	. . . . . . . . 
[DEBUG]    20	. . . . . . . . 
[DEBUG]    21	. . . . . . . . 
[DEBUG]    22	. . . . . . . . 
[DEBUG]    23	. . . . . . . . 
[DEBUG]    24	. . . . . . . . 
[DEBUG]    25	. . . . . . . . 
[DEBUG]    26	. . . . . . . . 
[DEBUG]    27	. . . . . . . . 
[DEBUG]    28	. . . . . . . . 
[DEBUG]    29	. . . . . . . . 
[DEBUG]    30	. . . . . . . . 
[DEBUG]    31	. . . . . . . . 
[DEBUG]    32	. . . . . . . . 
[DEBUG]    33	. . . . . . . . 
[DEBUG]    34	. . . . . . . . 
[DEBUG]    35	. . . . . . . . 
[DEBUG]    36	. . . . . . . . 
[DEBUG]    37	. . . . . . . # 
[DEBUG]    38	# . . . . . . # 
[DEBUG]    39	# . . # . . . # 
[DEBUG]    40	# . . # . . # # 
[DEBUG]    41	# . . # # . # # 
[DEBUG]    42	# # . # # # # # 
[DEBUG]    43	# # . # # # # # 
[DEBUG]    44	# # # # # # # # 
[DEBUG]    45	# # # # # # # # 
[DEBUG]    46	# # # # # # # # 
[DEBUG]    47	# # # # # # # # 
[DEBUG]    48	# # # # # # # # 
[DEBUG]    49	# # # # # # # # 
[DEBUG]    50	# # # # # # # # 
[DEBUG]    51	# # # # # # # # 
[DEBUG]    52	# # # # # # # # 
[DEBUG]    53	# # # # # # # # 
[DEBUG]    54	# # # # # # # # 
[DEBUG]    55	# # # # # # # # 
[DEBUG]    56	# # # # # # # # 
[DEBUG]    57	# # # # # # # # 
[DEBUG]    58	# # # # # # # # 
[DEBUG]    59	# # # # # # # # 
[DEBUG]    60	# # # # # # # # 
[DEBUG]    61	# # # # # # # # 
[DEBUG]    62	# # # # # # # # 
[DEBUG]    63	# # # # # # # # 
[DEBUG]    64	# # # # # # # # 
[DEBUG]    65	# # # . # # # # 
[DEBUG]    66	. # # . . # # # 
[DEBUG]    67	. . # . . . . . 
[DEBUG]    68	. . . . . . . . 
[DEBUG]    69	. . . . . . . . 
[DEBUG]    70	. . . . . . . . 
[DEBUG]    71	. . . . . . . . 
[DEBUG]    72	. . . . . . . . 
[DEBUG]    73	. . . . . . . . 
[DEBUG]    74	. . . . . . . . 
[DEBUG]    75	. . . . . . . . 
[DEBUG]    76	. . . . . . . . 
[DEBUG]    77	. . . . . . . . 
[DEBUG]    78	. . . . . . . . 
[DEBUG]    79	. . . . . . . . 
[DEBUG]    80	. . . . . . . . 
[DEBUG]    81	. . . . . . . . 
[DEBUG]    82	. . . . . . . . 
[DEBUG]    83	. . . . . . . . 
[DEBUG]    84	. . . . . . . . 
[DEBUG]    85	. . . . . . . . 
[DEBUG]    86	. . . . . . . . 
[DEBUG]    87	. . . . . . . . 
[DEBUG]    88	. . . . . . . . 
[DEBUG]    89	. . . . . . . . 
[DEBUG]    90	. . . . . . . . 
[DEBUG]    91	. . . . . . . . 
[DEBUG]    92	. . . . . . . . 
[DEBUG]    93	. . . . . . . . 
[DEBUG]    94	. . . . . . . . 
[DEBUG]    95	. . . . . . . . 
[DEBUG]    96	. . . . . . . . 
[DEBUG]    97	. . . . . . . . 
[DEBUG]    98	. . . . . . . . 
[DEBUG]    99	. . . . . . . . 
[DEBUG]   100	. . . . . . . # 
[DEBUG]   101	# . . . . . . # 
[DEBUG]   102	# . . # . . # # 
[DEBUG]   103	# . . # . . # # 
[DEBUG]   104	# . . # . . # # 
[DEBUG]   105	# # . # # . # # 
[DEBUG]   106	# # . # # . # # 
[DEBUG]   107	# # # # # # # # 
[DEBUG]   108	# # # # # # # # 
[DEBUG]   109	# # # # # # # # 
[DEBUG]   110	# # # # # # # # 
[DEBUG]   111	# # # # # # # # 
[DEBUG]   112	# # # # # # # # 
[DEBUG]   113	# # # # # # # # 
[DEBUG]   114	# # # # # # # # 
[DEBUG]   115	# # # # # # # # 
[DEBUG]   116	# # # # # # # # 
[DEBUG]   117	# # # # # # # # 
[DEBUG]   118	# # # # # # # # 
[DEBUG]   119	# # # # # # # # 
[DEBUG]   120	# # # # # # # # 
[DEBUG]   121	# # # # # # # # 
[DEBUG]   122	# # # # # # # # 
[DEBUG]   123	# # # # # # # # 
[DEBUG]   124	# # # # # # # # 
[DEBUG]   125	# # # # # # # # 
[DEBUG]   126	# # # # # # # # 
[DEBUG]   127	# # # # # # # # 
[DEBUG]  Smallest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]     2 120   2 106   3 128   1  90   2 192   2 158   2 182   2 183
[DEBUG]     2 120   2 106   3 128   1  90   2 192   2 158   3 183   2 183
[DEBUG]     2 120   2 106   3 128   1  90   2 192   2 158   3 183   2 183

[DEBUG]  Largest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]    37 155  40 144  42 167  38 127  40 230  41 197  37 217  35 216
[DEBUG]    37 155  40 144  42 167  38 127  40 230  41 197  37 217  35 216
[DEBUG]    37 155  40 144  42 167  38 127  40 230  41 197  37 217  35 216
[DEBUG]  C0R1:

[DEBUG]  SWEEP
[DEBUG]  Tim	0 1 2 3 4 5 6 7 
[DEBUG]     0	# # # # # # # # 
[DEBUG]     1	# # # . # # # # 
[DEBUG]     2	. # # . . . . . 
[DEBUG]     3	. . . . . . . . 
[DEBUG]     4	. . . . . . . . 
[DEBUG]     5	. . . . . . . . 
[DEBUG]     6	. . . . . . . . 
[DEBUG]     7	. . . . . . . . 
[DEBUG]     8	. . . . . . . . 
[DEBUG]     9	. . . . . . . . 
[DEBUG]    10	. . . . . . . . 
[DEBUG]    11	. . . . . . . . 
[DEBUG]    12	. . . . . . . . 
[DEBUG]    13	. . . . . . . . 
[DEBUG]    14	. . . . . . . . 
[DEBUG]    15	. . . . . . . . 
[DEBUG]    16	. . . . . . . . 
[DEBUG]    17	. . . . . . . . 
[DEBUG]    18	. . . . . . . . 
[DEBUG]    19	. . . . . . . . 
[DEBUG]    20	. . . . . . . . 
[DEBUG]    21	. . . . . . . . 
[DEBUG]    22	. . . . . . . . 
[DEBUG]    23	. . . . . . . . 
[DEBUG]    24	. . . . . . . . 
[DEBUG]    25	. . . . . . . . 
[DEBUG]    26	. . . . . . . . 
[DEBUG]    27	. . . . . . . . 
[DEBUG]    28	. . . . . . . . 
[DEBUG]    29	. . . . . . . . 
[DEBUG]    30	. . . . . . . . 
[DEBUG]    31	. . . . . . . . 
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[DEBUG]    33	. . . . . . . . 
[DEBUG]    34	. . . . . . . . 
[DEBUG]    35	. . . . . . . . 
[DEBUG]    36	. . . . . . . . 
[DEBUG]    37	# . . . . . . # 
[DEBUG]    38	# . . # . . . # 
[DEBUG]    39	# . . # . . . # 
[DEBUG]    40	# . . # . . # # 
[DEBUG]    41	# # . # # . # # 
[DEBUG]    42	# # . # # # # # 
[DEBUG]    43	# # # # # # # # 
[DEBUG]    44	# # # # # # # # 
[DEBUG]    45	# # # # # # # # 
[DEBUG]    46	# # # # # # # # 
[DEBUG]    47	# # # # # # # # 
[DEBUG]    48	# # # # # # # # 
[DEBUG]    49	# # # # # # # # 
[DEBUG]    50	# # # # # # # # 
[DEBUG]    51	# # # # # # # # 
[DEBUG]    52	# # # # # # # # 
[DEBUG]    53	# # # # # # # # 
[DEBUG]    54	# # # # # # # # 
[DEBUG]    55	# # # # # # # # 
[DEBUG]    56	# # # # # # # # 
[DEBUG]    57	# # # # # # # # 
[DEBUG]    58	# # # # # # # # 
[DEBUG]    59	# # # # # # # # 
[DEBUG]    60	# # # # # # # # 
[DEBUG]    61	# # # # # # # # 
[DEBUG]    62	# # # # # # # # 
[DEBUG]    63	# # # # # # # # 
[DEBUG]    64	# # # # # # # # 
[DEBUG]    65	# # # . # # # # 
[DEBUG]    66	. # # . # # # # 
[DEBUG]    67	. # # . . . . . 
[DEBUG]    68	. . . . . . . . 
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[DEBUG]    89	. . . . . . . . 
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[DEBUG]    97	. . . . . . . . 
[DEBUG]    98	. . . . . . . . 
[DEBUG]    99	. . . . . . . . 
[DEBUG]   100	# . . . . . . . 
[DEBUG]   101	# . . . . . . . 
[DEBUG]   102	# . . . . . . # 
[DEBUG]   103	# . . # # . . # 
[DEBUG]   104	# . . # # . # # 
[DEBUG]   105	# . . # # . # # 
[DEBUG]   106	# # # # # # # # 
[DEBUG]   107	# # # # # # # # 
[DEBUG]   108	# # # # # # # # 
[DEBUG]   109	# # # # # # # # 
[DEBUG]   110	# # # # # # # # 
[DEBUG]   111	# # # # # # # # 
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[DEBUG]   118	# # # # # # # # 
[DEBUG]   119	# # # # # # # # 
[DEBUG]   120	# # # # # # # # 
[DEBUG]   121	# # # # # # # # 
[DEBUG]   122	# # # # # # # # 
[DEBUG]   123	# # # # # # # # 
[DEBUG]   124	# # # # # # # # 
[DEBUG]   125	# # # # # # # # 
[DEBUG]   126	# # # # # # # # 
[DEBUG]   127	# # # # # # # # 
[DEBUG]  Smallest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]     1 119   3 105   3 126   1  87   2 190   2 158   2 177   2 179
[DEBUG]     2 120   3 105   3 126   1  87   2 190   2 158   2 177   2 179
[DEBUG]     2 120   3 105   3 126   1  87   2 190   2 158   2 177   2 179

[DEBUG]  Largest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]    35 153  40 142  41 164  36 122  39 227  41 197  38 213  35 212
[DEBUG]    35 153  40 142  41 164  36 122  39 227  41 197  38 213  35 212
[DEBUG]    35 153  40 142  41 164  36 122  39 227  41 197  38 213  35 212
[SPEW ]  REG_178 = 40
[DEBUG]  C1R0:

[DEBUG]  SWEEP
[DEBUG]  Tim	0 1 2 3 4 5 6 7 
[DEBUG]     0	# # # # # # # # 
[DEBUG]     1	# # # # # # # # 
[DEBUG]     2	# # # . . # # # 
[DEBUG]     3	# # . . . # # # 
[DEBUG]     4	. # . . . . . . 
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[DEBUG]     6	. # . . . . . . 
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[DEBUG]    33	. . . . . . . . 
[DEBUG]    34	. . # . . . . . 
[DEBUG]    35	# # # # . . . . 
[DEBUG]    36	# # # # . . # . 
[DEBUG]    37	# # # # # . # . 
[DEBUG]    38	# # # # # . # # 
[DEBUG]    39	# # # # # # # # 
[DEBUG]    40	# # # # # # # # 
[DEBUG]    41	# # # # # # # # 
[DEBUG]    42	# # # # # # # # 
[DEBUG]    43	# # # # # # # # 
[DEBUG]    44	# # # # # # # # 
[DEBUG]    45	# # # # # # # # 
[DEBUG]    46	# # # # # # # # 
[DEBUG]    47	# # # # # # # # 
[DEBUG]    48	# # # # # # # # 
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[DEBUG]    50	# # # # # # # # 
[DEBUG]    51	# # # # # # # # 
[DEBUG]    52	# # # # # # # # 
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[DEBUG]    54	# # # # # # # # 
[DEBUG]    55	# # # # # # # # 
[DEBUG]    56	# # # # # # # # 
[DEBUG]    57	# # # # # # # # 
[DEBUG]    58	# # # # # # # # 
[DEBUG]    59	# # # # # # # # 
[DEBUG]    60	# # # # # # # # 
[DEBUG]    61	# # # # # # # # 
[DEBUG]    62	# # # # # # # # 
[DEBUG]    63	# # # # # # # # 
[DEBUG]    64	# # # # # # # # 
[DEBUG]    65	# # # # # # # # 
[DEBUG]    66	# # # # # # # # 
[DEBUG]    67	# # # . . # # # 
[DEBUG]    68	# # . . . . # # 
[DEBUG]    69	. # . . . . . . 
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[DEBUG]    92	. . . . . . . . 
[DEBUG]    93	. . . # . . . . 
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[DEBUG]    98	. . . # . . . . 
[DEBUG]    99	. # # # . . . . 
[DEBUG]   100	# # # # # . . . 
[DEBUG]   101	# # # # # . # . 
[DEBUG]   102	# # # # # . # # 
[DEBUG]   103	# # # # # . # # 
[DEBUG]   104	# # # # # . # # 
[DEBUG]   105	# # # # # # # # 
[DEBUG]   106	# # # # # # # # 
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[DEBUG]   108	# # # # # # # # 
[DEBUG]   109	# # # # # # # # 
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[DEBUG]   111	# # # # # # # # 
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[DEBUG]   114	# # # # # # # # 
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[DEBUG]   118	# # # # # # # # 
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[DEBUG]   121	# # # # # # # # 
[DEBUG]   122	# # # # # # # # 
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[DEBUG]   124	# # # # # # # # 
[DEBUG]   125	# # # # # # # # 
[DEBUG]   126	# # # # # # # # 
[DEBUG]   127	# # # # # # # # 
[DEBUG]  Smallest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]     4 127   7 120   3 136   2  96   2 194   3 154   4 182   4 180
[DEBUG]     4 127   8 121   3 136   2  96   2 194   3 154   4 182   4 180
[DEBUG]     4 127   9 122   3 136   2  96   2 194   3 154   4 182   4 180
[DEBUG]     4 127   9 122   3 136   2  96   2 194   3 154   4 182   4 180
[DEBUG]     4 127   9 122   3 136   2  96   2 194   4 155   4 182   4 180
[DEBUG]     4 127   9 122   3 136   2  96   2 194   4 155   4 182   4 180

[DEBUG]  Largest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]    33 156  29 142  33 166  33 127  35 227  37 188  35 213  36 212
[DEBUG]    33 156  29 142  33 166  33 127  35 227  37 188  35 213  36 212
[DEBUG]    33 156  29 142  33 166  33 127  35 227  37 188  35 213  36 212
[DEBUG]  C1R1:

[DEBUG]  SWEEP
[DEBUG]  Tim	0 1 2 3 4 5 6 7 
[DEBUG]     0	# # # # # # # # 
[DEBUG]     1	# # # # # # # # 
[DEBUG]     2	# # # . . # # # 
[DEBUG]     3	# # . . . . . # 
[DEBUG]     4	. # . . . . . # 
[DEBUG]     5	. # . . . . . . 
[DEBUG]     6	. # . . . . . . 
[DEBUG]     7	. # . . . . . . 
[DEBUG]     8	. . . . . . . . 
[DEBUG]     9	. . . . . . . . 
[DEBUG]    10	. . . . . . . . 
[DEBUG]    11	. . . . . . . . 
[DEBUG]    12	. . . . . . . . 
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[DEBUG]    21	. . . . . . . . 
[DEBUG]    22	. . . . . . . . 
[DEBUG]    23	. . . . . . . . 
[DEBUG]    24	. . . . . . . . 
[DEBUG]    25	. . . . . . . . 
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[DEBUG]    27	. . . . . . . . 
[DEBUG]    28	. . . . . . . . 
[DEBUG]    29	. . . . . . . . 
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[DEBUG]    31	. . . . . . . . 
[DEBUG]    32	. . . . . . . . 
[DEBUG]    33	. . . . . . . . 
[DEBUG]    34	# # . . . . . . 
[DEBUG]    35	# # # # # . . . 
[DEBUG]    36	# # # # # . . . 
[DEBUG]    37	# # # # # . . . 
[DEBUG]    38	# # # # # . # # 
[DEBUG]    39	# # # # # . # # 
[DEBUG]    40	# # # # # . # # 
[DEBUG]    41	# # # # # # # # 
[DEBUG]    42	# # # # # # # # 
[DEBUG]    43	# # # # # # # # 
[DEBUG]    44	# # # # # # # # 
[DEBUG]    45	# # # # # # # # 
[DEBUG]    46	# # # # # # # # 
[DEBUG]    47	# # # # # # # # 
[DEBUG]    48	# # # # # # # # 
[DEBUG]    49	# # # # # # # # 
[DEBUG]    50	# # # # # # # # 
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[DEBUG]    52	# # # # # # # # 
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[DEBUG]    54	# # # # # # # # 
[DEBUG]    55	# # # # # # # # 
[DEBUG]    56	# # # # # # # # 
[DEBUG]    57	# # # # # # # # 
[DEBUG]    58	# # # # # # # # 
[DEBUG]    59	# # # # # # # # 
[DEBUG]    60	# # # # # # # # 
[DEBUG]    61	# # # # # # # # 
[DEBUG]    62	# # # # # # # # 
[DEBUG]    63	# # # # # # # # 
[DEBUG]    64	# # # # # # # # 
[DEBUG]    65	# # # # # # # # 
[DEBUG]    66	# # # # # # # # 
[DEBUG]    67	# # # . . # # # 
[DEBUG]    68	# # . . . . . # 
[DEBUG]    69	. # . . . . . # 
[DEBUG]    70	. # . . . . . . 
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[DEBUG]    72	. . . . . . . . 
[DEBUG]    73	. . . . . . . . 
[DEBUG]    74	. . . . . . . . 
[DEBUG]    75	. . . . . . . . 
[DEBUG]    76	. . . . . . . . 
[DEBUG]    77	. . . . . . . . 
[DEBUG]    78	. . . . . . . . 
[DEBUG]    79	. . . . . . . . 
[DEBUG]    80	. . . . . . . . 
[DEBUG]    81	. . . . . . . . 
[DEBUG]    82	. . . . . . . . 
[DEBUG]    83	. . . . . . . . 
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[DEBUG]    85	. . . . . . . . 
[DEBUG]    86	. . . . . . . . 
[DEBUG]    87	. . . . . . . . 
[DEBUG]    88	. . . . . . . . 
[DEBUG]    89	. . . . . . . . 
[DEBUG]    90	. . . . . . . . 
[DEBUG]    91	. . . . . . . . 
[DEBUG]    92	. . . . . . . . 
[DEBUG]    93	. . . . . . . . 
[DEBUG]    94	. . . . . . . . 
[DEBUG]    95	. . . . . . . . 
[DEBUG]    96	. . . . . . . . 
[DEBUG]    97	. . . . . . . . 
[DEBUG]    98	. # . # . . . . 
[DEBUG]    99	# # # # . . . . 
[DEBUG]   100	# # # # # . . . 
[DEBUG]   101	# # # # # . # # 
[DEBUG]   102	# # # # # . # # 
[DEBUG]   103	# # # # # . # # 
[DEBUG]   104	# # # # # # # # 
[DEBUG]   105	# # # # # # # # 
[DEBUG]   106	# # # # # # # # 
[DEBUG]   107	# # # # # # # # 
[DEBUG]   108	# # # # # # # # 
[DEBUG]   109	# # # # # # # # 
[DEBUG]   110	# # # # # # # # 
[DEBUG]   111	# # # # # # # # 
[DEBUG]   112	# # # # # # # # 
[DEBUG]   113	# # # # # # # # 
[DEBUG]   114	# # # # # # # # 
[DEBUG]   115	# # # # # # # # 
[DEBUG]   116	# # # # # # # # 
[DEBUG]   117	# # # # # # # # 
[DEBUG]   118	# # # # # # # # 
[DEBUG]   119	# # # # # # # # 
[DEBUG]   120	# # # # # # # # 
[DEBUG]   121	# # # # # # # # 
[DEBUG]   122	# # # # # # # # 
[DEBUG]   123	# # # # # # # # 
[DEBUG]   124	# # # # # # # # 
[DEBUG]   125	# # # # # # # # 
[DEBUG]   126	# # # # # # # # 
[DEBUG]   127	# # # # # # # # 
[DEBUG]  Smallest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]     4 122   6 114   3 129   3  95   2 190   3 151   3 174   5 178
[DEBUG]     4 122   7 115   3 129   3  95   2 190   3 151   3 174   5 178
[DEBUG]     4 122   7 115   3 129   3  95   2 190   3 151   3 174   5 178
[DEBUG]     4 122   8 116   3 129   3  95   2 190   3 151   3 174   5 178
[DEBUG]     4 122   8 116   3 129   3  95   2 190   3 151   3 174   5 178

[DEBUG]  Largest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]    33 151  30 138  33 159  34 126  34 222  39 187  37 208  36 209
[DEBUG]    33 151  30 138  33 159  34 126  34 222  39 187  37 208  36 209
[DEBUG]    33 151  30 138  33 159  34 126  34 222  39 187  37 208  36 209
[DEBUG]  C0R0:

[DEBUG]  SWEEP
[DEBUG]  Tim	0 1 2 3 4 5 6 7 
[DEBUG]     0	# # # # # # # # 
[DEBUG]     1	# # # # # # # # 
[DEBUG]     2	# # # . # # # # 
[DEBUG]     3	. # # . . . # . 
[DEBUG]     4	. . # . . . . . 
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[DEBUG]     6	. . . . . . . . 
[DEBUG]     7	. . . . . . . . 
[DEBUG]     8	. . . . . . . . 
[DEBUG]     9	. . . . . . . . 
[DEBUG]    10	. . . . . . . . 
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[DEBUG]    24	. . . . . . . . 
[DEBUG]    25	. . . . . . . . 
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[DEBUG]    27	. . . . . . . . 
[DEBUG]    28	. . . . . . . . 
[DEBUG]    29	. . . . . . . . 
[DEBUG]    30	. . . . . . . . 
[DEBUG]    31	. . . . . . . . 
[DEBUG]    32	. . . . . . . . 
[DEBUG]    33	. . . . . . . . 
[DEBUG]    34	. . . . . . . . 
[DEBUG]    35	. . . . . . . # 
[DEBUG]    36	# . . . . . . # 
[DEBUG]    37	# . . . . . # # 
[DEBUG]    38	# . . # . . # # 
[DEBUG]    39	# . . # # . # # 
[DEBUG]    40	# . . # # . # # 
[DEBUG]    41	# # . # # # # # 
[DEBUG]    42	# # # # # # # # 
[DEBUG]    43	# # # # # # # # 
[DEBUG]    44	# # # # # # # # 
[DEBUG]    45	# # # # # # # # 
[DEBUG]    46	# # # # # # # # 
[DEBUG]    47	# # # # # # # # 
[DEBUG]    48	# # # # # # # # 
[DEBUG]    49	# # # # # # # # 
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[DEBUG]    51	# # # # # # # # 
[DEBUG]    52	# # # # # # # # 
[DEBUG]    53	# # # # # # # # 
[DEBUG]    54	# # # # # # # # 
[DEBUG]    55	# # # # # # # # 
[DEBUG]    56	# # # # # # # # 
[DEBUG]    57	# # # # # # # # 
[DEBUG]    58	# # # # # # # # 
[DEBUG]    59	# # # # # # # # 
[DEBUG]    60	# # # # # # # # 
[DEBUG]    61	# # # # # # # # 
[DEBUG]    62	# # # # # # # # 
[DEBUG]    63	# # # # # # # # 
[DEBUG]    64	# # # # # # # # 
[DEBUG]    65	# # # # # # # # 
[DEBUG]    66	# # # . # # # # 
[DEBUG]    67	# # # . # # # . 
[DEBUG]    68	. # # . . . . . 
[DEBUG]    69	. . # . . . . . 
[DEBUG]    70	. . . . . . . . 
[DEBUG]    71	. . . . . . . . 
[DEBUG]    72	. . . . . . . . 
[DEBUG]    73	. . . . . . . . 
[DEBUG]    74	. . . . . . . . 
[DEBUG]    75	. . . . . . . . 
[DEBUG]    76	. . . . . . . . 
[DEBUG]    77	. . . . . . . . 
[DEBUG]    78	. . . . . . . . 
[DEBUG]    79	. . . . . . . . 
[DEBUG]    80	. . . . . . . . 
[DEBUG]    81	. . . . . . . . 
[DEBUG]    82	. . . . . . . . 
[DEBUG]    83	. . . . . . . . 
[DEBUG]    84	. . . . . . . . 
[DEBUG]    85	. . . . . . . . 
[DEBUG]    86	. . . . . . . . 
[DEBUG]    87	. . . . . . . . 
[DEBUG]    88	. . . . . . . . 
[DEBUG]    89	. . . . . . . . 
[DEBUG]    90	. . . . . . . . 
[DEBUG]    91	. . . . . . . . 
[DEBUG]    92	. . . . . . . . 
[DEBUG]    93	. . . . . . . . 
[DEBUG]    94	. . . . . . . . 
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[DEBUG]   126	# # # # # # # # 
[DEBUG]   127	# # # # # # # # 
[DEBUG]  Smallest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]     3 121   4 108   5 130   2  91   3 193   3 159   4 184   3 184
[DEBUG]     3 121   4 108   5 130   2  91   3 193   3 159   4 184   3 184

[DEBUG]  Largest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]    35 153  38 142  41 166  36 125  37 227  40 196  36 216  34 215
[DEBUG]    35 153  38 142  41 166  36 125  37 227  40 196  36 216  34 215
[DEBUG]    35 153  38 142  41 166  36 125  37 227  40 196  36 216  34 215
[DEBUG]  C0R1:

[DEBUG]  SWEEP
[DEBUG]  Tim	0 1 2 3 4 5 6 7 
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[DEBUG]   107	# # # # # # # # 
[DEBUG]   108	# # # # # # # # 
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[DEBUG]   112	# # # # # # # # 
[DEBUG]   113	# # # # # # # # 
[DEBUG]   114	# # # # # # # # 
[DEBUG]   115	# # # # # # # # 
[DEBUG]   116	# # # # # # # # 
[DEBUG]   117	# # # # # # # # 
[DEBUG]   118	# # # # # # # # 
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[DEBUG]   125	# # # # # # # # 
[DEBUG]   126	# # # # # # # # 
[DEBUG]   127	# # # # # # # # 
[DEBUG]  Smallest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]     3 121   4 106   5 128   2  88   3 191   3 159   3 178   3 180
[DEBUG]     3 121   4 106   5 128   2  88   3 191   3 159   3 178   3 180

[DEBUG]  Largest
[DEBUG]     0       1       2       3       4       5       6       7    
[DEBUG]    34 152  38 140  41 164  36 122  37 225  40 196  38 213  35 212
[DEBUG]    34 152  38 140  40 163  36 122  36 224  40 196  37 212  35 212
[DEBUG]    34 152  38 140  40 163  36 122  36 224  40 196  37 212  35 212
[DEBUG]    34 152  38 140  40 163  36 122  36 224  40 196  37 212  35 212
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   32 (  32)  136 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   32 (  32)  157 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   32 (  32)  121 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  222 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   32 (  32)  155 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   32 (  32)  145 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   32 (  32)  165 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   32 (  32)  126 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   32 (  32)  224 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   32 (  32)  183 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  210 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   32 (  32)  208 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   32 (  32)  140 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   32 (  32)  158 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   32 (  32)  124 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   32 (  32)  180 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  203 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   32 (  32)  205 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   32 (  32)  136 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   32 (  32)  157 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   32 (  32)  121 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  222 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   32 (  32)  145 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   32 (  32)  165 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   32 (  32)  126 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   32 (  32)  224 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   32 (  32)  183 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  210 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   32 (  32)  208 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   32 (  32)  140 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   32 (  32)  158 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   32 (  32)  124 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   32 (  32)  180 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  203 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   32 (  32)  205 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   32 (  32)  136 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   32 (  32)  157 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   32 (  32)  121 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  222 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   32 (  32)  165 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   32 (  32)  126 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   32 (  32)  224 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   32 (  32)  183 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  210 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   32 (  32)  208 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   32 (  32)  140 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   32 (  32)  158 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   32 (  32)  124 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   32 (  32)  180 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  203 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   32 (  32)  205 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   32 (  32)  136 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   32 (  32)  157 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   32 (  32)  121 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  222 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   32 (  32)  126 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   32 (  32)  224 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   32 (  32)  183 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  210 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   32 (  32)  208 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   32 (  32)  140 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   32 (  32)  158 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   32 (  32)  124 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   32 (  32)  180 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  203 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   32 (  32)  205 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   32 (  32)  136 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   32 (  32)  157 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   32 (  32)  121 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  222 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   32 (  32)  224 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   32 (  32)  183 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  210 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   32 (  32)  208 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   32 (  32)  140 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   32 (  32)  158 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   32 (  32)  124 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   32 (  32)  180 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  203 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   32 (  32)  205 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   32 (  32)  136 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   32 (  32)  157 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   32 (  32)  121 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  222 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   32 (  32)  183 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  210 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   32 (  32)  208 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   32 (  32)  140 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   32 (  32)  158 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   32 (  32)  124 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   32 (  32)  180 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  203 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   32 (  32)  205 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   32 (  32)  136 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   32 (  32)  157 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   32 (  32)  121 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  222 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  210 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   32 (  32)  208 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   32 (  32)  140 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   32 (  32)  158 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   32 (  32)  124 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   32 (  32)  180 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  203 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   32 (  32)  205 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   32 (  32)  136 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   32 (  32)  157 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   32 (  32)  121 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  222 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   32 (  32)  208 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   32 (  32)  140 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   32 (  32)  158 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   32 (  32)  124 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   32 (  32)  180 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  203 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   32 (  32)  205 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   32 (  32)  136 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   32 (  32)  157 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   32 (  32)  121 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  222 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   32 (  32)  140 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   32 (  32)  158 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   32 (  32)  124 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   32 (  32)  180 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  203 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   32 (  32)  205 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   32 (  32)  136 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   32 (  32)  157 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   32 (  32)  121 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  222 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   32 (  32)  140 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   32 (  32)  158 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   32 (  32)  124 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   32 (  32)  180 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  203 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   32 (  32)  205 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   32 (  32)  136 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   32 (  32)  157 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   32 (  32)  121 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  222 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   32 (  32)  158 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   32 (  32)  124 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   32 (  32)  180 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  203 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   32 (  32)  205 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   32 (  32)  136 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   32 (  32)  157 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   32 (  32)  121 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  222 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   32 (  32)  124 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   32 (  32)  180 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  203 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   32 (  32)  205 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   32 (  32)  136 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   32 (  32)  157 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   32 (  32)  121 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  222 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   32 (  32)  180 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  203 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   32 (  32)  205 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   32 (  32)  136 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   32 (  32)  157 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   32 (  32)  121 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  222 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   32 (  32)  180 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  203 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   32 (  32)  205 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   32 (  32)  136 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   32 (  32)  157 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   32 (  32)  121 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  222 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  203 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   32 (  32)  205 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   32 (  32)  136 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   32 (  32)  157 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   32 (  32)  121 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  222 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  191 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   32 (  32)  205 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   32 (  32)  150 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   32 (  32)  136 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   32 (  32)  157 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   32 (  32)  121 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  222 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  191 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   20 (  32)  193 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  137 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   32 (  32)  136 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   32 (  32)  157 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   32 (  32)  121 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  222 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  191 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   20 (  32)  193 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  137 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   20 (  32)  124 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   32 (  32)  157 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   32 (  32)  121 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  222 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  191 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   20 (  32)  193 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  137 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   20 (  32)  124 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   22 (  32)  147 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   32 (  32)  121 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  222 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  191 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   20 (  32)  193 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  137 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   20 (  32)  124 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   22 (  32)  147 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   19 (  32)  108 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   32 (  32)  222 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  191 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   20 (  32)  193 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  137 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   20 (  32)  124 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   22 (  32)  147 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   19 (  32)  108 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   20 (  32)  210 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  191 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   20 (  32)  193 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  137 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   20 (  32)  124 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   22 (  32)  147 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   19 (  32)  108 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   20 (  32)  210 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   32 (  32)  212 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  191 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   20 (  32)  193 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  137 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   20 (  32)  124 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   22 (  32)  147 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   19 (  32)  108 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   20 (  32)  210 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   20 (  32)  200 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   32 (  32)  213 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  191 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   20 (  32)  193 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  137 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   20 (  32)  124 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   22 (  32)  147 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   19 (  32)  108 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   20 (  32)  210 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   20 (  32)  200 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   18 (  32)  199 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   32 (  32)  150 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  191 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   20 (  32)  193 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  137 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   20 (  32)  124 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   22 (  32)  147 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   19 (  32)  108 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   20 (  32)  210 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   20 (  32)  200 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   18 (  32)  199 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   32 (  32)  134 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  191 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   20 (  32)  193 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  137 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   20 (  32)  124 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   22 (  32)  147 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   19 (  32)  108 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   20 (  32)  210 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   20 (  32)  200 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   18 (  32)  199 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   21 (  32)  123 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   32 (  32)  155 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  191 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   20 (  32)  193 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  137 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   20 (  32)  124 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   22 (  32)  147 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   19 (  32)  108 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   20 (  32)  210 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   20 (  32)  200 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   18 (  32)  199 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   21 (  32)  123 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   22 (  32)  145 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   32 (  32)  118 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  191 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   20 (  32)  193 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  137 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   20 (  32)  124 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   22 (  32)  147 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   19 (  32)  108 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   20 (  32)  210 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   20 (  32)  200 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   18 (  32)  199 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   21 (  32)  123 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   22 (  32)  145 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   18 (  32)  104 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   32 (  32)  220 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  191 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   20 (  32)  193 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  137 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   20 (  32)  124 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   22 (  32)  147 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   19 (  32)  108 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   20 (  32)  210 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   20 (  32)  200 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   18 (  32)  199 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   21 (  32)  123 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   22 (  32)  145 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   18 (  32)  104 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   20 (  32)  208 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   32 (  32)  188 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  191 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   20 (  32)  193 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  137 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   20 (  32)  124 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   22 (  32)  147 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   19 (  32)  108 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   20 (  32)  210 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   20 (  32)  200 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   18 (  32)  199 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   21 (  32)  123 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   22 (  32)  145 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   18 (  32)  104 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   20 (  32)  208 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   32 (  32)  207 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  191 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   20 (  32)  193 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2476:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  137 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   20 (  32)  124 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   22 (  32)  147 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   19 (  32)  108 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   20 (  32)  210 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   20 (  32)  200 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   18 (  32)  199 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   21 (  32)  123 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   22 (  32)  145 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   18 (  32)  104 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   20 (  32)  208 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  195 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   32 (  32)  209 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  115 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  138 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   97 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  198 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  156 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  173 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  156 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  191 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   20 (  32)  193 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2376:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  137 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   20 (  32)  124 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   22 (  32)  147 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   19 (  32)  108 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   20 (  32)  210 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   20 (  32)  200 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   18 (  32)  199 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   21 (  32)  123 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   22 (  32)  145 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   18 (  32)  104 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   20 (  32)  208 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  195 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   18 (  32)  195 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  120 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  116 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  142 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)  100 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  202 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  159 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  179 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  163 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  118 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  117 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  145 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  105 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  203 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  191 ( 203)  154 ( 154)  180 ( 180) 
[SPEW ]  lane 7:   20 (  32)  193 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2376:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  137 ( 150)   98 (  98)  124 ( 124) 
[SPEW ]  lane 1:   20 (  32)  124 ( 136)   97 (  97)  122 ( 122) 
[SPEW ]  lane 2:   22 (  32)  147 ( 157)  116 ( 116)  143 ( 143) 
[SPEW ]  lane 3:   19 (  32)  108 ( 121)   78 (  78)  105 ( 105) 
[SPEW ]  lane 4:   20 (  32)  210 ( 222)  178 ( 178)  205 ( 205) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   20 (  32)  200 ( 212)  158 ( 158)  185 ( 185) 
[SPEW ]  lane 7:   18 (  32)  199 ( 213)  140 ( 140)  165 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   21 (  32)  123 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   22 (  32)  145 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   18 (  32)  104 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   20 (  32)  208 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  195 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   18 (  32)  195 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  113 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  136 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   95 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  197 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  154 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  171 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  157 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  124 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  119 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  148 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  108 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  206 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  165 ( 162) 
[SPEW ]  lane 6:   20 (  32)  191 ( 203)  154 ( 154)  186 ( 180) 
[SPEW ]  lane 7:   20 (  32)  193 ( 205)  137 ( 137)  169 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2376:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  137 ( 150)   98 (  98)  130 ( 124) 
[SPEW ]  lane 1:   20 (  32)  124 ( 136)   97 (  97)  129 ( 122) 
[SPEW ]  lane 2:   22 (  32)  147 ( 157)  116 ( 116)  148 ( 143) 
[SPEW ]  lane 3:   19 (  32)  108 ( 121)   78 (  78)  110 ( 105) 
[SPEW ]  lane 4:   20 (  32)  210 ( 222)  178 ( 178)  210 ( 205) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  132 ( 132)  164 ( 156) 
[SPEW ]  lane 6:   20 (  32)  200 ( 212)  158 ( 158)  190 ( 185) 
[SPEW ]  lane 7:   18 (  32)  199 ( 213)  140 ( 140)  172 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:   21 (  32)  123 ( 134)  100 ( 100)  126 ( 126) 
[SPEW ]  lane 2:   22 (  32)  145 ( 155)  123 ( 123)  149 ( 149) 
[SPEW ]  lane 3:   18 (  32)  104 ( 118)   87 (  87)  115 ( 115) 
[SPEW ]  lane 4:   20 (  32)  208 ( 220)  185 ( 185)  211 ( 211) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  138 ( 138)  162 ( 162) 
[SPEW ]  lane 6:   20 (  32)  195 ( 207)  164 ( 164)  191 ( 191) 
[SPEW ]  lane 7:   18 (  32)  195 ( 209)  148 ( 148)  173 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  113 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  136 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   95 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  197 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  154 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  171 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  157 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  119 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  116 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  142 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  103 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  201 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  160 ( 162) 
[SPEW ]  lane 6:   20 (  32)  191 ( 203)  154 ( 154)  177 ( 180) 
[SPEW ]  lane 7:   20 (  32)  193 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 2376:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  137 ( 150)   98 (  98)  123 ( 124) 
[SPEW ]  lane 1:   20 (  32)  124 ( 136)   97 (  97)  120 ( 122) 
[SPEW ]  lane 2:   22 (  32)  147 ( 157)  116 ( 116)  141 ( 143) 
[SPEW ]  lane 3:   19 (  32)  108 ( 121)   78 (  78)  103 ( 105) 
[SPEW ]  lane 4:   20 (  32)  210 ( 222)  178 ( 178)  203 ( 205) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:   20 (  32)  200 ( 212)  158 ( 158)  182 ( 185) 
[SPEW ]  lane 7:   18 (  32)  199 ( 213)  140 ( 140)  164 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)  104 ( 104)  136 ( 129) 
[SPEW ]  lane 1:   21 (  32)  123 ( 134)  100 ( 100)  132 ( 126) 
[SPEW ]  lane 2:   22 (  32)  145 ( 155)  123 ( 123)  155 ( 149) 
[SPEW ]  lane 3:   18 (  32)  104 ( 118)   87 (  87)  119 ( 115) 
[SPEW ]  lane 4:   20 (  32)  208 ( 220)  185 ( 185)  217 ( 211) 
[SPEW ]  lane 5:   21 (  32)  177 ( 188)  138 ( 138)  170 ( 162) 
[SPEW ]  lane 6:   20 (  32)  195 ( 207)  164 ( 164)  196 ( 191) 
[SPEW ]  lane 7:   18 (  32)  195 ( 209)  148 ( 148)  180 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:   19 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:   19 (  32)  132 ( 145)   84 (  84)  113 ( 115) 
[SPEW ]  lane 2:   18 (  32)  151 ( 165)  110 ( 110)  136 ( 138) 
[SPEW ]  lane 3:   18 (  32)  112 ( 126)   68 (  68)   95 (  97) 
[SPEW ]  lane 4:   18 (  32)  210 ( 224)  170 ( 170)  197 ( 198) 
[SPEW ]  lane 5:   20 (  32)  171 ( 183)  127 ( 127)  154 ( 156) 
[SPEW ]  lane 6:   19 (  32)  197 ( 210)  147 ( 147)  171 ( 173) 
[SPEW ]  lane 7:   20 (  32)  196 ( 208)  131 ( 131)  157 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:   18 (  32)  136 ( 150)   92 (  92)  119 ( 118) 
[SPEW ]  lane 1:   19 (  32)  127 ( 140)   87 (  87)  116 ( 117) 
[SPEW ]  lane 2:   18 (  32)  144 ( 158)  116 ( 116)  142 ( 145) 
[SPEW ]  lane 3:   18 (  32)  110 ( 124)   76 (  76)  103 ( 105) 
[SPEW ]  lane 4:   18 (  32)  206 ( 220)  174 ( 174)  201 ( 203) 
[SPEW ]  lane 5:   21 (  32)  169 ( 180)  133 ( 133)  160 ( 162) 
[SPEW ]  lane 6:   20 (  32)  191 ( 203)  154 ( 154)  177 ( 180) 
[SPEW ]  lane 7:   20 (  32)  193 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    0 (   0)
[SPEW ]  Timings 3839:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:    6 (  32)  137 ( 150)   98 (  98)  123 ( 124) 
[SPEW ]  lane 1:    7 (  32)  124 ( 136)   97 (  97)  120 ( 122) 
[SPEW ]  lane 2:    9 (  32)  147 ( 157)  116 ( 116)  141 ( 143) 
[SPEW ]  lane 3:    6 (  32)  108 ( 121)   78 (  78)  103 ( 105) 
[SPEW ]  lane 4:    7 (  32)  210 ( 222)  178 ( 178)  203 ( 205) 
[SPEW ]  lane 5:    8 (  32)  177 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:    7 (  32)  200 ( 212)  158 ( 158)  182 ( 185) 
[SPEW ]  lane 7:    5 (  32)  199 ( 213)  140 ( 140)  164 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:    5 (  32)  136 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:    8 (  32)  123 ( 134)  100 ( 100)  124 ( 126) 
[SPEW ]  lane 2:    9 (  32)  145 ( 155)  123 ( 123)  148 ( 149) 
[SPEW ]  lane 3:    5 (  32)  104 ( 118)   87 (  87)  112 ( 115) 
[SPEW ]  lane 4:    7 (  32)  208 ( 220)  185 ( 185)  210 ( 211) 
[SPEW ]  lane 5:    8 (  32)  177 ( 188)  138 ( 138)  163 ( 162) 
[SPEW ]  lane 6:    7 (  32)  195 ( 207)  164 ( 164)  189 ( 191) 
[SPEW ]  lane 7:    5 (  32)  195 ( 209)  148 ( 148)  172 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:    6 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:    6 (  32)  132 ( 145)   84 (  84)  113 ( 115) 
[SPEW ]  lane 2:    5 (  32)  151 ( 165)  110 ( 110)  136 ( 138) 
[SPEW ]  lane 3:    5 (  32)  112 ( 126)   68 (  68)   95 (  97) 
[SPEW ]  lane 4:    5 (  32)  210 ( 224)  170 ( 170)  197 ( 198) 
[SPEW ]  lane 5:    7 (  32)  171 ( 183)  127 ( 127)  154 ( 156) 
[SPEW ]  lane 6:    6 (  32)  197 ( 210)  147 ( 147)  171 ( 173) 
[SPEW ]  lane 7:    7 (  32)  196 ( 208)  131 ( 131)  157 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:    5 (  32)  136 ( 150)   92 (  92)  119 ( 118) 
[SPEW ]  lane 1:    6 (  32)  127 ( 140)   87 (  87)  116 ( 117) 
[SPEW ]  lane 2:    5 (  32)  144 ( 158)  116 ( 116)  142 ( 145) 
[SPEW ]  lane 3:    5 (  32)  110 ( 124)   76 (  76)  103 ( 105) 
[SPEW ]  lane 4:    5 (  32)  206 ( 220)  174 ( 174)  201 ( 203) 
[SPEW ]  lane 5:    8 (  32)  169 ( 180)  133 ( 133)  160 ( 162) 
[SPEW ]  lane 6:    7 (  32)  191 ( 203)  154 ( 154)  177 ( 180) 
[SPEW ]  lane 7:    7 (  32)  193 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    1 (   0)
[DEBUG]  RAM Training is done

[DEBUG]  Press any key to continue...
[SPEW ]  Timings 4022:
[SPEW ]  channel 0, slot 0, rank 0
[SPEW ]  lane 0:    6 (  32)  137 ( 150)   98 (  98)  123 ( 124) 
[SPEW ]  lane 1:    7 (  32)  124 ( 136)   97 (  97)  120 ( 122) 
[SPEW ]  lane 2:    9 (  32)  147 ( 157)  116 ( 116)  141 ( 143) 
[SPEW ]  lane 3:    6 (  32)  108 ( 121)   78 (  78)  103 ( 105) 
[SPEW ]  lane 4:    7 (  32)  210 ( 222)  178 ( 178)  203 ( 205) 
[SPEW ]  lane 5:    8 (  32)  177 ( 188)  132 ( 132)  156 ( 156) 
[SPEW ]  lane 6:    7 (  32)  200 ( 212)  158 ( 158)  182 ( 185) 
[SPEW ]  lane 7:    5 (  32)  199 ( 213)  140 ( 140)  164 ( 165) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 0, slot 0, rank 1
[SPEW ]  lane 0:    5 (  32)  136 ( 150)  104 ( 104)  129 ( 129) 
[SPEW ]  lane 1:    8 (  32)  123 ( 134)  100 ( 100)  124 ( 126) 
[SPEW ]  lane 2:    9 (  32)  145 ( 155)  123 ( 123)  148 ( 149) 
[SPEW ]  lane 3:    5 (  32)  104 ( 118)   87 (  87)  112 ( 115) 
[SPEW ]  lane 4:    7 (  32)  208 ( 220)  185 ( 185)  210 ( 211) 
[SPEW ]  lane 5:    8 (  32)  177 ( 188)  138 ( 138)  163 ( 162) 
[SPEW ]  lane 6:    7 (  32)  195 ( 207)  164 ( 164)  189 ( 191) 
[SPEW ]  lane 7:    5 (  32)  195 ( 209)  148 ( 148)  172 ( 173) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 0
[SPEW ]  lane 0:    6 (  32)  142 ( 155)   88 (  88)  114 ( 114) 
[SPEW ]  lane 1:    6 (  32)  132 ( 145)   84 (  84)  113 ( 115) 
[SPEW ]  lane 2:    5 (  32)  151 ( 165)  110 ( 110)  136 ( 138) 
[SPEW ]  lane 3:    5 (  32)  112 ( 126)   68 (  68)   95 (  97) 
[SPEW ]  lane 4:    5 (  32)  210 ( 224)  170 ( 170)  197 ( 198) 
[SPEW ]  lane 5:    7 (  32)  171 ( 183)  127 ( 127)  154 ( 156) 
[SPEW ]  lane 6:    6 (  32)  197 ( 210)  147 ( 147)  171 ( 173) 
[SPEW ]  lane 7:    7 (  32)  196 ( 208)  131 ( 131)  157 ( 156) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  channel 1, slot 0, rank 1
[SPEW ]  lane 0:    5 (  32)  136 ( 150)   92 (  92)  119 ( 118) 
[SPEW ]  lane 1:    6 (  32)  127 ( 140)   87 (  87)  116 ( 117) 
[SPEW ]  lane 2:    5 (  32)  144 ( 158)  116 ( 116)  142 ( 145) 
[SPEW ]  lane 3:    5 (  32)  110 ( 124)   76 (  76)  103 ( 105) 
[SPEW ]  lane 4:    5 (  32)  206 ( 220)  174 ( 174)  201 ( 203) 
[SPEW ]  lane 5:    8 (  32)  169 ( 180)  133 ( 133)  160 ( 162) 
[SPEW ]  lane 6:    7 (  32)  191 ( 203)  154 ( 154)  177 ( 180) 
[SPEW ]  lane 7:    7 (  32)  193 ( 205)  137 ( 137)  161 ( 161) 
[SPEW ]  lane 8:   21 (  32)  256 ( 267)  126 ( 126)  126 ( 126) 
[SPEW ]  [178] =   70 (   0)
[SPEW ]  [10b] =    1 (   0)
[DEBUG]  CBMEM:
[DEBUG]  IMD: root @ 0x7f7ff000 254 entries.
[DEBUG]  IMD: root @ 0x7f7fec00 62 entries.
[DEBUG]  FMAP: area COREBOOT found @ 210200 (2031104 bytes)
[DEBUG]  External stage cache:
[DEBUG]  IMD: root @ 0x7ffff000 254 entries.
[DEBUG]  IMD: root @ 0x7fffec00 62 entries.
[SPEW ]  [6dc] = 23faff
[SPEW ]  [6e8] = 23faff

[DEBUG]  Press any key to continue...
[DEBUG]  ME: FW Partition Table      : OK
[DEBUG]  ME: Bringup Loader Failure  : NO
[DEBUG]  ME: Firmware Init Complete  : YES
[DEBUG]  ME: Manufacturing Mode      : YES
[DEBUG]  ME: Boot Options Present    : NO
[DEBUG]  ME: Update In Progress      : NO
[DEBUG]  ME: Current Working State   : Normal
[DEBUG]  ME: Current Operation State : M0 without UMA but with error
[DEBUG]  ME: Current Operation Mode  : Normal
[DEBUG]  ME: Error Code              : No Error
[DEBUG]  ME: Progress Phase          : Policy Module
[DEBUG]  ME: Power Management Event  : Moff->Mx wake after an error
[DEBUG]  ME: Progress Phase State    : Entry into Policy Module
[DEBUG]  SMM Memory Map
[DEBUG]  SMRAM       : 0x7f800000 0x800000
[DEBUG]   Subregion 0: 0x7f800000 0x700000
[DEBUG]   Subregion 1: 0x7ff00000 0x100000
[DEBUG]   Subregion 2: 0x80000000 0x0
[DEBUG]  MTRR Range: Start=7f000000 End=7f800000 (Size 800000)
[DEBUG]  MTRR Range: Start=7f800000 End=80000000 (Size 800000)
[DEBUG]  MTRR Range: Start=ffc00000 End=0 (Size 400000)
[DEBUG]  Normal boot
[INFO ]  CBFS: Found 'fallback/postcar' @0x30e00 size 0x516c in mcache @0xfefc2ff4
[DEBUG]  Loading module at 0x7f7d0000 with entry 0x7f7d0031. filesize: 0x4da8 memsize: 0x90d8
[DEBUG]  Processing 225 relocs. Offset value of 0x7d7d0000
[DEBUG]  BS: romstage times (exec / console): total (unknown) / 20660 ms


[NOTE ]  coreboot-4.15-1556-g9d458a95bd-dirty Mon Feb 14 19:27:41 UTC 2022 postcar starting (log level: 8)...
[DEBUG]  Normal boot
[DEBUG]  FMAP: area COREBOOT found @ 210200 (2031104 bytes)
[INFO ]  CBFS: Found 'fallback/ramstage' @0x14800 size 0x19867 in mcache @0x7f7dd0dc
[DEBUG]  Loading module at 0x7f78a000 with entry 0x7f78a000. filesize: 0x33458 memsize: 0x444c8
[DEBUG]  Processing 3603 relocs. Offset value of 0x7e98a000
[DEBUG]  BS: postcar times (exec / console): total (unknown) / 43 ms


[NOTE ]  coreboot-4.15-1556-g9d458a95bd-dirty Mon Feb 14 19:27:41 UTC 2022 ramstage starting (log level: 8)...
[DEBUG]  Normal boot
[DEBUG]  Disabling PEG10.
[DEBUG]  BS: BS_DEV_INIT_CHIPS run times (exec / console): 0 / 3 ms
[INFO ]  Enumerating buses...
[SPEW ]  Show all devs... Before device enumeration.
[SPEW ]  Root Device: enabled 1
[SPEW ]  CPU_CLUSTER: 0: enabled 1
[SPEW ]  DOMAIN: 0000: enabled 1
[SPEW ]  APIC: 00: enabled 1
[SPEW ]  PCI: 00:00.0: enabled 1
[SPEW ]  PCI: 00:01.0: enabled 0
[SPEW ]  PCI: 00:02.0: enabled 1
[SPEW ]  PCI: 00:16.0: enabled 1
[SPEW ]  PCI: 00:16.1: enabled 0
[SPEW ]  PCI: 00:16.2: enabled 0
[SPEW ]  PCI: 00:16.3: enabled 0
[SPEW ]  PCI: 00:19.0: enabled 1
[SPEW ]  PCI: 00:1a.0: enabled 1
[SPEW ]  PCI: 00:1b.0: enabled 1
[SPEW ]  PCI: 00:1c.0: enabled 1
[SPEW ]  PCI: 00:1c.1: enabled 1
[SPEW ]  PCI: 00:1c.2: enabled 1
[SPEW ]  PCI: 00:1c.3: enabled 1
[SPEW ]  PCI: 00:1c.4: enabled 1
[SPEW ]  PCI: 00:1c.5: enabled 1
[SPEW ]  PCI: 00:1c.6: enabled 0
[SPEW ]  PCI: 00:1c.7: enabled 0
[SPEW ]  PCI: 00:1d.0: enabled 1
[SPEW ]  PCI: 00:1e.0: enabled 0
[SPEW ]  PCI: 00:1f.0: enabled 1
[SPEW ]  PCI: 00:1f.2: enabled 1
[SPEW ]  PCI: 00:1f.3: enabled 1
[SPEW ]  PCI: 00:1f.5: enabled 0
[SPEW ]  PCI: 00:1f.6: enabled 1
[SPEW ]  PNP: 004e.3: enabled 0
[SPEW ]  PNP: 004e.4: enabled 1
[SPEW ]  PNP: 004e.5: enabled 0
[SPEW ]  Compare with tree...
[SPEW ]  Root Device: enabled 1
[SPEW ]   CPU_CLUSTER: 0: enabled 1
[SPEW ]    APIC: 00: enabled 1
[SPEW ]   DOMAIN: 0000: enabled 1
[SPEW ]    PCI: 00:00.0: enabled 1
[SPEW ]    PCI: 00:01.0: enabled 0
[SPEW ]    PCI: 00:02.0: enabled 1
[SPEW ]    PCI: 00:16.0: enabled 1
[SPEW ]    PCI: 00:16.1: enabled 0
[SPEW ]    PCI: 00:16.2: enabled 0
[SPEW ]    PCI: 00:16.3: enabled 0
[SPEW ]    PCI: 00:19.0: enabled 1
[SPEW ]    PCI: 00:1a.0: enabled 1
[SPEW ]    PCI: 00:1b.0: enabled 1
[SPEW ]    PCI: 00:1c.0: enabled 1
[SPEW ]    PCI: 00:1c.1: enabled 1
[SPEW ]    PCI: 00:1c.2: enabled 1
[SPEW ]    PCI: 00:1c.3: enabled 1
[SPEW ]    PCI: 00:1c.4: enabled 1
[SPEW ]    PCI: 00:1c.5: enabled 1
[SPEW ]    PCI: 00:1c.6: enabled 0
[SPEW ]    PCI: 00:1c.7: enabled 0
[SPEW ]    PCI: 00:1d.0: enabled 1
[SPEW ]    PCI: 00:1e.0: enabled 0
[SPEW ]    PCI: 00:1f.0: enabled 1
[SPEW ]     PNP: 004e.3: enabled 0
[SPEW ]     PNP: 004e.4: enabled 1
[SPEW ]     PNP: 004e.5: enabled 0
[SPEW ]    PCI: 00:1f.2: enabled 1
[SPEW ]    PCI: 00:1f.3: enabled 1
[SPEW ]    PCI: 00:1f.5: enabled 0
[SPEW ]    PCI: 00:1f.6: enabled 1
[DEBUG]  Root Device scanning...
[SPEW ]  scan_static_bus for Root Device
[DEBUG]  CPU_CLUSTER: 0 enabled
[DEBUG]  DOMAIN: 0000 enabled
[DEBUG]  DOMAIN: 0000 scanning...
[DEBUG]  PCI: pci_scan_bus for bus 00
[SPEW ]  PCI: 00:00.0 [8086/0000] ops
[DEBUG]  PCI: 00:00.0 [8086/0044] enabled
[SPEW ]  PCI: 00:02.0 [8086/0000] ops
[DEBUG]  PCI: 00:02.0 [8086/0046] enabled
[SPEW ]  PCI: 00:16.0 [8086/0000] ops
[DEBUG]  PCI: 00:16.0 [8086/3b64] enabled
[DEBUG]  PCI: 00:16.1: Disabling device
[DEBUG]  PCI: 00:16.2: Disabling device
[DEBUG]  PCI: 00:16.3: Disabling device
[INFO ]  PCI: Static device PCI: 00:19.0 not found, disabling it.
[SPEW ]  PCI: 00:1a.0 [8086/0000] ops
[DEBUG]  PCI: 00:1a.0 [8086/3b3c] enabled
[SPEW ]  PCI: 00:1b.0 [8086/0000] ops
[DEBUG]  PCI: 00:1b.0 [8086/3b56] enabled
[DEBUG]  PCI: 00:1c.0 subordinate bus PCI Express
[DEBUG]  PCI: 00:1c.0 [8086/3b42] enabled
[DEBUG]  PCI: 00:1c.1 subordinate bus PCI Express
[DEBUG]  PCI: 00:1c.1 [8086/3b44] enabled
[DEBUG]  PCI: 00:1c.2 subordinate bus PCI Express
[DEBUG]  PCI: 00:1c.2 [8086/3b46] enabled
[DEBUG]  PCI: 00:1c.3 subordinate bus PCI Express
[DEBUG]  PCI: 00:1c.3 [8086/3b48] enabled
[DEBUG]  PCI: 00:1c.4 subordinate bus PCI Express
[DEBUG]  PCI: 00:1c.4 [8086/3b4a] enabled
[DEBUG]  PCI: 00:1c.5 subordinate bus PCI Express
[DEBUG]  PCI: 00:1c.5 [8086/3b4c] enabled
[DEBUG]  PCI: 00:1c.6: Disabling device
[DEBUG]  PCI: 00:1c.6 [8086/3b4e] disabled No operations
[DEBUG]  PCI: 00:1c.7: Disabling device
[DEBUG]  PCI: 00:1c.7 [8086/3b50] disabled No operations
[SPEW ]  PCI: 00:1d.0 [8086/0000] ops
[DEBUG]  PCI: 00:1d.0 [8086/3b34] enabled
[DEBUG]  PCI: 00:1e.0: Disabling device
[SPEW ]  PCI: 00:1e.0 [8086/0000] bus ops
[DEBUG]  PCI: 00:1e.0 [8086/2448] disabled
[SPEW ]  PCI: 00:1f.0 [8086/0000] bus ops
[DEBUG]  PCI: 00:1f.0 [8086/3b0b] enabled
[SPEW ]  PCI: 00:1f.2 [8086/0000] ops
[DEBUG]  PCI: 00:1f.2 [8086/3b2e] enabled
[SPEW ]  PCI: 00:1f.3 [8086/0000] bus ops
[DEBUG]  PCI: 00:1f.3 [8086/3b30] enabled
[DEBUG]  PCI: 00:1f.5: Disabling device
[DEBUG]  PCI: 00:1f.5 [8086/3b2d] disabled No operations
[SPEW ]  PCI: 00:1f.6 [8086/3b32] ops
[DEBUG]  PCI: 00:1f.6 [8086/3b32] enabled
[WARN ]  PCI: Leftover static devices:
[WARN ]  PCI: 00:01.0
[WARN ]  PCI: 00:16.1
[WARN ]  PCI: 00:16.2
[WARN ]  PCI: 00:16.3
[WARN ]  PCI: 00:19.0
[WARN ]  PCI: Check your devicetree.cb.
[DEBUG]  PCI: 00:1c.0 scanning...
[SPEW ]  do_pci_scan_bridge for PCI: 00:1c.0
[DEBUG]  PCI: 00:1c.0: No LTR support
[DEBUG]  PCI: pci_scan_bus for bus 01
[DEBUG]  scan_bus: bus PCI: 00:1c.0 finished in 12 msecs
[DEBUG]  PCI: 00:1c.1 scanning...
[SPEW ]  do_pci_scan_bridge for PCI: 00:1c.1
[DEBUG]  PCI: 00:1c.1: No LTR support
[DEBUG]  PCI: pci_scan_bus for bus 02
[DEBUG]  scan_bus: bus PCI: 00:1c.1 finished in 12 msecs
[DEBUG]  PCI: 00:1c.2 scanning...
[SPEW ]  do_pci_scan_bridge for PCI: 00:1c.2
[DEBUG]  PCI: 00:1c.2: No LTR support
[DEBUG]  PCI: pci_scan_bus for bus 03
[DEBUG]  scan_bus: bus PCI: 00:1c.2 finished in 12 msecs
[DEBUG]  PCI: 00:1c.3 scanning...
[SPEW ]  do_pci_scan_bridge for PCI: 00:1c.3
[DEBUG]  PCI: 00:1c.3: No LTR support
[DEBUG]  PCI: pci_scan_bus for bus 04
[DEBUG]  PCI: 04:00.0 [14e4/4727] enabled
[INFO ]  Enabling Common Clock Configuration
[INFO ]  ASPM: Enabled L0s and L1
[INFO ]  PCIe: Max_Payload_Size adjusted to 128
[DEBUG]  PCI: 04:00.0: No LTR support
[DEBUG]  scan_bus: bus PCI: 00:1c.3 finished in 34 msecs
[DEBUG]  PCI: 00:1c.4 scanning...
[SPEW ]  do_pci_scan_bridge for PCI: 00:1c.4
[DEBUG]  PCI: 00:1c.4: No LTR support
[DEBUG]  PCI: pci_scan_bus for bus 05
[DEBUG]  scan_bus: bus PCI: 00:1c.4 finished in 12 msecs
[DEBUG]  PCI: 00:1c.5 scanning...
[SPEW ]  do_pci_scan_bridge for PCI: 00:1c.5
[DEBUG]  PCI: 00:1c.5: No LTR support
[DEBUG]  PCI: pci_scan_bus for bus 06
[DEBUG]  scan_bus: bus PCI: 00:1c.5 finished in 12 msecs
[DEBUG]  PCI: 00:1f.0 scanning...
[SPEW ]  scan_static_bus for PCI: 00:1f.0
[DEBUG]  PNP: 004e.3 disabled
[DEBUG]  PNP: 004e.4 enabled
[DEBUG]  PNP: 004e.5 disabled
[SPEW ]  scan_static_bus for PCI: 00:1f.0 done
[DEBUG]  scan_bus: bus PCI: 00:1f.0 finished in 19 msecs
[DEBUG]  PCI: 00:1f.3 scanning...
[SPEW ]  scan_generic_bus for PCI: 00:1f.3
[SPEW ]  scan_generic_bus for PCI: 00:1f.3 done
[DEBUG]  scan_bus: bus PCI: 00:1f.3 finished in 9 msecs
[DEBUG]  scan_bus: bus DOMAIN: 0000 finished in 433 msecs
[SPEW ]  scan_static_bus for Root Device done
[DEBUG]  scan_bus: bus Root Device finished in 459 msecs
[INFO ]  done
[DEBUG]  BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 718 ms
[DEBUG]  FMAP: area RW_MRC_CACHE found @ 200000 (65536 bytes)
[DEBUG]  FMAP: area RW_MRC_CACHE found @ 200000 (65536 bytes)
[DEBUG]  MRC: Checking cached data update for 'RW_MRC_CACHE'.
[INFO ]  Manufacturer: ef
[INFO ]  SF: Detected ef 4016 with sector size 0x1000, total 0x400000
[ERROR]  MRC: no data in 'RW_MRC_CACHE'
[DEBUG]  MRC: cache data 'RW_MRC_CACHE' needs update.
[DEBUG]  MRC: updated 'RW_MRC_CACHE'.
[DEBUG]  BS: BS_DEV_ENUMERATE exit times (exec / console): 1 / 42 ms
[DEBUG]  found VGA at PCI: 00:02.0
[DEBUG]  Setting up VGA for PCI: 00:02.0
[DEBUG]  Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
[DEBUG]  Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
[INFO ]  Allocating resources...
[INFO ]  Reading resources...
[SPEW ]  Root Device read_resources bus 0 link: 0
[SPEW ]  CPU_CLUSTER: 0 read_resources bus 0 link: 0
[SPEW ]  CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
[SPEW ]  DOMAIN: 0000 read_resources bus 0 link: 0
[DEBUG]  Adding PCIe enhanced config space BAR 0xe0000000-0xf0000000.
[DEBUG]  ram_before_4g_top: 0x7f800000
[DEBUG]  TOUUD: 0x1740
[SPEW ]  PCI: 00:1c.0 read_resources bus 1 link: 0
[SPEW ]  PCI: 00:1c.0 read_resources bus 1 link: 0 done
[SPEW ]  PCI: 00:1c.1 read_resources bus 2 link: 0
[SPEW ]  PCI: 00:1c.1 read_resources bus 2 link: 0 done
[SPEW ]  PCI: 00:1c.2 read_resources bus 3 link: 0
[SPEW ]  PCI: 00:1c.2 read_resources bus 3 link: 0 done
[SPEW ]  PCI: 00:1c.3 read_resources bus 4 link: 0
[SPEW ]  PCI: 00:1c.3 read_resources bus 4 link: 0 done
[SPEW ]  PCI: 00:1c.4 read_resources bus 5 link: 0
[SPEW ]  PCI: 00:1c.4 read_resources bus 5 link: 0 done
[SPEW ]  PCI: 00:1c.5 read_resources bus 6 link: 0
[SPEW ]  PCI: 00:1c.5 read_resources bus 6 link: 0 done
[SPEW ]  PCI: 00:1f.0 read_resources bus 0 link: 0
[SPEW ]  PCI: 00:1f.0 read_resources bus 0 link: 0 done
[SPEW ]  DOMAIN: 0000 read_resources bus 0 link: 0 done
[SPEW ]  Root Device read_resources bus 0 link: 0 done
[INFO ]  Done reading resources.
[SPEW ]  Show resources in subtree (Root Device)...After reading.
[DEBUG]   Root Device child on link 0 CPU_CLUSTER: 0
[DEBUG]    CPU_CLUSTER: 0 child on link 0 APIC: 00
[DEBUG]     APIC: 00
[DEBUG]    DOMAIN: 0000 child on link 0 PCI: 00:00.0
[SPEW ]    DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
[SPEW ]    DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit fffffffff flags 40040200 index 10000100
[DEBUG]     PCI: 00:00.0
[SPEW ]     PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 50
[SPEW ]     PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
[SPEW ]     PCI: 00:00.0 resource base 100000 size 7f700000 align 0 gran 0 limit 0 flags e0004200 index 4
[SPEW ]     PCI: 00:00.0 resource base 7f800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 5
[SPEW ]     PCI: 00:00.0 resource base 80000000 size 1c00000 align 0 gran 0 limit 0 flags f0000200 index 6
[SPEW ]     PCI: 00:00.0 resource base 81c00000 size 400000 align 0 gran 0 limit 0 flags f0000200 index 7
[SPEW ]     PCI: 00:00.0 resource base 82000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 8
[SPEW ]     PCI: 00:00.0 resource base 100000000 size 74000000 align 0 gran 0 limit 0 flags e0004200 index 9
[SPEW ]     PCI: 00:00.0 resource base fed00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index a
[SPEW ]     PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index b
[SPEW ]     PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index c
[DEBUG]     PCI: 00:02.0
[SPEW ]     PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
[SPEW ]     PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit ffffffffffffffff flags d0001201 index 18
[SPEW ]     PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 20
[DEBUG]     PCI: 00:16.0
[SPEW ]     PCI: 00:16.0 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10
[DEBUG]     PCI: 00:1a.0
[SPEW ]     PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
[DEBUG]     PCI: 00:1b.0
[SPEW ]     PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
[DEBUG]     PCI: 00:1c.0
[SPEW ]     PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
[SPEW ]     PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
[SPEW ]     PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
[DEBUG]     PCI: 00:1c.1
[SPEW ]     PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
[SPEW ]     PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
[SPEW ]     PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
[DEBUG]     PCI: 00:1c.2
[SPEW ]     PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
[SPEW ]     PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
[SPEW ]     PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
[DEBUG]     PCI: 00:1c.3 child on link 0 PCI: 04:00.0
[SPEW ]     PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
[SPEW ]     PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
[SPEW ]     PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
[DEBUG]      PCI: 04:00.0
[SPEW ]      PCI: 04:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
[DEBUG]     PCI: 00:1c.4
[SPEW ]     PCI: 00:1c.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
[SPEW ]     PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
[SPEW ]     PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
[DEBUG]     PCI: 00:1c.5
[SPEW ]     PCI: 00:1c.5 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
[SPEW ]     PCI: 00:1c.5 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
[SPEW ]     PCI: 00:1c.5 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
[DEBUG]     PCI: 00:1c.6
[DEBUG]     PCI: 00:1c.7
[DEBUG]     PCI: 00:1d.0
[SPEW ]     PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
[DEBUG]     PCI: 00:1e.0
[DEBUG]     PCI: 00:1f.0 child on link 0 PNP: 004e.3
[SPEW ]     PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
[SPEW ]     PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
[SPEW ]     PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
[SPEW ]     PCI: 00:1f.0 resource base fe00 size fc align 0 gran 0 limit 0 flags c0040100 index 10000200
[DEBUG]      PNP: 004e.3
[SPEW ]      PNP: 004e.3 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
[SPEW ]      PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
[SPEW ]      PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
[DEBUG]      PNP: 004e.4
[SPEW ]      PNP: 004e.4 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
[SPEW ]      PNP: 004e.4 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
[DEBUG]      PNP: 004e.5
[SPEW ]      PNP: 004e.5 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
[SPEW ]      PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
[DEBUG]     PCI: 00:1f.2
[SPEW ]     PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
[SPEW ]     PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
[SPEW ]     PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
[SPEW ]     PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
[SPEW ]     PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
[SPEW ]     PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
[DEBUG]     PCI: 00:1f.3
[SPEW ]     PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
[SPEW ]     PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
[DEBUG]     PCI: 00:1f.5
[DEBUG]     PCI: 00:1f.6
[SPEW ]     PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
[INFO ]  === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
[DEBUG]   PCI: 00:1c.3 io: size: 0 align: 12 gran: 12 limit: ffff
[DEBUG]   PCI: 00:1c.3 io: size: 0 align: 12 gran: 12 limit: ffff done
[DEBUG]   PCI: 00:1c.3 mem: size: 0 align: 20 gran: 20 limit: ffffffff
[DEBUG]    PCI: 04:00.0 10 *  [0x0 - 0x3fff] mem
[DEBUG]   PCI: 00:1c.3 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
[DEBUG]   PCI: 00:1c.3 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
[DEBUG]   PCI: 00:1c.3 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
[INFO ]  === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
[DEBUG]  DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
[DEBUG]   update_constraints: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
[DEBUG]   update_constraints: PCI: 00:1f.0 10000200 base 0000fe00 limit 0000fefb io (fixed)
[DEBUG]   update_constraints: PNP: 004e.4 60 base 000003f8 limit 000003ff io (fixed)
[DEBUG]   update_constraints: PCI: 00:1f.3 20 base 00000400 limit 0000041f io (fixed)
[INFO ]   DOMAIN: 0000: Resource ranges:
[INFO ]   * Base: 1000, Size: ee00, Tag: 100
[INFO ]   * Base: fefc, Size: 104, Tag: 100
[DEBUG]    PCI: 00:1f.2 20 *  [0x1000 - 0x101f] limit: 101f io
[DEBUG]    PCI: 00:02.0 20 *  [0x1020 - 0x1027] limit: 1027 io
[DEBUG]    PCI: 00:1f.2 10 *  [0x1028 - 0x102f] limit: 102f io
[DEBUG]    PCI: 00:1f.2 18 *  [0x1030 - 0x1037] limit: 1037 io
[DEBUG]    PCI: 00:1f.2 14 *  [0x1038 - 0x103b] limit: 103b io
[DEBUG]    PCI: 00:1f.2 1c *  [0x103c - 0x103f] limit: 103f io
[DEBUG]  DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
[DEBUG]  DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff
[DEBUG]   update_constraints: PCI: 00:00.0 50 base e0000000 limit efffffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 03 base 00000000 limit 0009ffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 04 base 00100000 limit 7f7fffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 05 base 7f800000 limit 7fffffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 06 base 80000000 limit 81bfffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 07 base 81c00000 limit 81ffffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 08 base 82000000 limit 83ffffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 09 base 100000000 limit 173ffffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 0a base fed00000 limit fedfffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 0b base 000a0000 limit 000bffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:00.0 0c base 000c0000 limit 000fffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:02.0 18 base d0000000 limit dfffffff prefmem (fixed)
[DEBUG]   update_constraints: PCI: 00:1f.0 10000100 base ff800000 limit ffffffff mem (fixed)
[DEBUG]   update_constraints: PCI: 00:1f.0 03 base fec00000 limit fec00fff mem (fixed)
[INFO ]   DOMAIN: 0000: Resource ranges:
[INFO ]   * Base: 84000000, Size: 4c000000, Tag: 200
[INFO ]   * Base: f0000000, Size: ec00000, Tag: 200
[INFO ]   * Base: fec01000, Size: ff000, Tag: 200
[INFO ]   * Base: fee00000, Size: a00000, Tag: 200
[INFO ]   * Base: 174000000, Size: e8c000000, Tag: 100200
[DEBUG]    PCI: 00:02.0 10 *  [0x84000000 - 0x843fffff] limit: 843fffff mem
[DEBUG]    PCI: 00:1c.3 20 *  [0x84400000 - 0x844fffff] limit: 844fffff mem
[DEBUG]    PCI: 00:1b.0 10 *  [0x84500000 - 0x84503fff] limit: 84503fff mem
[DEBUG]    PCI: 00:1f.6 10 *  [0x84504000 - 0x84504fff] limit: 84504fff mem
[DEBUG]    PCI: 00:1f.2 24 *  [0x84505000 - 0x845057ff] limit: 845057ff mem
[DEBUG]    PCI: 00:1a.0 10 *  [0x84506000 - 0x845063ff] limit: 845063ff mem
[DEBUG]    PCI: 00:1d.0 10 *  [0x84507000 - 0x845073ff] limit: 845073ff mem
[DEBUG]    PCI: 00:1f.3 10 *  [0x84508000 - 0x845080ff] limit: 845080ff mem
[DEBUG]    PCI: 00:16.0 10 *  [0x84509000 - 0x8450900f] limit: 8450900f mem
[DEBUG]  DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done
[DEBUG]  PCI: 00:1c.3 mem: base: 84400000 size: 100000 align: 20 gran: 20 limit: 844fffff
[INFO ]   PCI: 00:1c.3: Resource ranges:
[INFO ]   * Base: 84400000, Size: 100000, Tag: 200
[DEBUG]    PCI: 04:00.0 10 *  [0x84400000 - 0x84403fff] limit: 84403fff mem
[DEBUG]  PCI: 00:1c.3 mem: base: 84400000 size: 100000 align: 20 gran: 20 limit: 844fffff done
[INFO ]  === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
[SPEW ]  Root Device assign_resources, bus 0 link: 0
[SPEW ]  DOMAIN: 0000 assign_resources, bus 0 link: 0
[DEBUG]  PCI: 00:02.0 10 <- [0x0084000000 - 0x00843fffff] size 0x00400000 gran 0x16 mem64
[DEBUG]  PCI: 00:02.0 20 <- [0x0000001020 - 0x0000001027] size 0x00000008 gran 0x03 io
[DEBUG]  PCI: 00:16.0 10 <- [0x0084509000 - 0x008450900f] size 0x00000010 gran 0x04 mem64
[DEBUG]  PCI: 00:1a.0 10 <- [0x0084506000 - 0x00845063ff] size 0x00000400 gran 0x0a mem
[DEBUG]  PCI: 00:1b.0 10 <- [0x0084500000 - 0x0084503fff] size 0x00004000 gran 0x0e mem64
[DEBUG]  PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
[DEBUG]  PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
[DEBUG]  PCI: 00:1c.0 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 01 mem
[DEBUG]  PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
[DEBUG]  PCI: 00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
[DEBUG]  PCI: 00:1c.1 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 02 mem
[DEBUG]  PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io
[DEBUG]  PCI: 00:1c.2 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 03 prefmem
[DEBUG]  PCI: 00:1c.2 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 03 mem
[DEBUG]  PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io
[DEBUG]  PCI: 00:1c.3 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 04 prefmem
[DEBUG]  PCI: 00:1c.3 20 <- [0x0084400000 - 0x00844fffff] size 0x00100000 gran 0x14 bus 04 mem
[SPEW ]  PCI: 00:1c.3 assign_resources, bus 4 link: 0
[DEBUG]  PCI: 04:00.0 10 <- [0x0084400000 - 0x0084403fff] size 0x00004000 gran 0x0e mem64
[SPEW ]  PCI: 00:1c.3 assign_resources, bus 4 link: 0 done
[DEBUG]  PCI: 00:1c.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io
[DEBUG]  PCI: 00:1c.4 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 05 prefmem
[DEBUG]  PCI: 00:1c.4 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 05 mem
[DEBUG]  PCI: 00:1c.5 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 06 io
[DEBUG]  PCI: 00:1c.5 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 06 prefmem
[DEBUG]  PCI: 00:1c.5 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 06 mem
[DEBUG]  PCI: 00:1d.0 10 <- [0x0084507000 - 0x00845073ff] size 0x00000400 gran 0x0a mem
[SPEW ]  PCI: 00:1f.0 assign_resources, bus 0 link: 0
[DEBUG]  PNP: 004e.4 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
[DEBUG]  PNP: 004e.4 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
[SPEW ]  PCI: 00:1f.0 assign_resources, bus 0 link: 0 done
[DEBUG]  PCI: 00:1f.2 10 <- [0x0000001028 - 0x000000102f] size 0x00000008 gran 0x03 io
[DEBUG]  PCI: 00:1f.2 14 <- [0x0000001038 - 0x000000103b] size 0x00000004 gran 0x02 io
[DEBUG]  PCI: 00:1f.2 18 <- [0x0000001030 - 0x0000001037] size 0x00000008 gran 0x03 io
[DEBUG]  PCI: 00:1f.2 1c <- [0x000000103c - 0x000000103f] size 0x00000004 gran 0x02 io
[DEBUG]  PCI: 00:1f.2 20 <- [0x0000001000 - 0x000000101f] size 0x00000020 gran 0x05 io
[DEBUG]  PCI: 00:1f.2 24 <- [0x0084505000 - 0x00845057ff] size 0x00000800 gran 0x0b mem
[DEBUG]  PCI: 00:1f.3 10 <- [0x0084508000 - 0x00845080ff] size 0x00000100 gran 0x08 mem64
[DEBUG]  PCI: 00:1f.6 10 <- [0x0084504000 - 0x0084504fff] size 0x00001000 gran 0x0c mem64
[SPEW ]  DOMAIN: 0000 assign_resources, bus 0 link: 0 done
[SPEW ]  Root Device assign_resources, bus 0 link: 0 done
[INFO ]  Done setting resources.
[SPEW ]  Show resources in subtree (Root Device)...After assigning values.
[DEBUG]   Root Device child on link 0 CPU_CLUSTER: 0
[DEBUG]    CPU_CLUSTER: 0 child on link 0 APIC: 00
[DEBUG]     APIC: 00
[DEBUG]    DOMAIN: 0000 child on link 0 PCI: 00:00.0
[SPEW ]    DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
[SPEW ]    DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit fffffffff flags 40040200 index 10000100
[DEBUG]     PCI: 00:00.0
[SPEW ]     PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 50
[SPEW ]     PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
[SPEW ]     PCI: 00:00.0 resource base 100000 size 7f700000 align 0 gran 0 limit 0 flags e0004200 index 4
[SPEW ]     PCI: 00:00.0 resource base 7f800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 5
[SPEW ]     PCI: 00:00.0 resource base 80000000 size 1c00000 align 0 gran 0 limit 0 flags f0000200 index 6
[SPEW ]     PCI: 00:00.0 resource base 81c00000 size 400000 align 0 gran 0 limit 0 flags f0000200 index 7
[SPEW ]     PCI: 00:00.0 resource base 82000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 8
[SPEW ]     PCI: 00:00.0 resource base 100000000 size 74000000 align 0 gran 0 limit 0 flags e0004200 index 9
[SPEW ]     PCI: 00:00.0 resource base fed00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index a
[SPEW ]     PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index b
[SPEW ]     PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index c
[DEBUG]     PCI: 00:02.0
[SPEW ]     PCI: 00:02.0 resource base 84000000 size 400000 align 22 gran 22 limit 843fffff flags 60000201 index 10
[SPEW ]     PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit ffffffffffffffff flags d0001201 index 18
[SPEW ]     PCI: 00:02.0 resource base 1020 size 8 align 3 gran 3 limit 1027 flags 60000100 index 20
[DEBUG]     PCI: 00:16.0
[SPEW ]     PCI: 00:16.0 resource base 84509000 size 10 align 12 gran 4 limit 8450900f flags 60000201 index 10
[DEBUG]     PCI: 00:1a.0
[SPEW ]     PCI: 00:1a.0 resource base 84506000 size 400 align 12 gran 10 limit 845063ff flags 60000200 index 10
[DEBUG]     PCI: 00:1b.0
[SPEW ]     PCI: 00:1b.0 resource base 84500000 size 4000 align 14 gran 14 limit 84503fff flags 60000201 index 10
[DEBUG]     PCI: 00:1c.0
[SPEW ]     PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
[SPEW ]     PCI: 00:1c.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
[SPEW ]     PCI: 00:1c.0 resource base ffffffff size 0 align 20 gran 20 limit ffffffff flags 20080202 index 20
[DEBUG]     PCI: 00:1c.1
[SPEW ]     PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
[SPEW ]     PCI: 00:1c.1 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
[SPEW ]     PCI: 00:1c.1 resource base ffffffff size 0 align 20 gran 20 limit ffffffff flags 20080202 index 20
[DEBUG]     PCI: 00:1c.2
[SPEW ]     PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
[SPEW ]     PCI: 00:1c.2 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
[SPEW ]     PCI: 00:1c.2 resource base ffffffff size 0 align 20 gran 20 limit ffffffff flags 20080202 index 20
[DEBUG]     PCI: 00:1c.3 child on link 0 PCI: 04:00.0
[SPEW ]     PCI: 00:1c.3 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
[SPEW ]     PCI: 00:1c.3 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
[SPEW ]     PCI: 00:1c.3 resource base 84400000 size 100000 align 20 gran 20 limit 844fffff flags 60080202 index 20
[DEBUG]      PCI: 04:00.0
[SPEW ]      PCI: 04:00.0 resource base 84400000 size 4000 align 14 gran 14 limit 84403fff flags 60000201 index 10
[DEBUG]     PCI: 00:1c.4
[SPEW ]     PCI: 00:1c.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
[SPEW ]     PCI: 00:1c.4 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
[SPEW ]     PCI: 00:1c.4 resource base ffffffff size 0 align 20 gran 20 limit ffffffff flags 20080202 index 20
[DEBUG]     PCI: 00:1c.5
[SPEW ]     PCI: 00:1c.5 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
[SPEW ]     PCI: 00:1c.5 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
[SPEW ]     PCI: 00:1c.5 resource base ffffffff size 0 align 20 gran 20 limit ffffffff flags 20080202 index 20
[DEBUG]     PCI: 00:1c.6
[DEBUG]     PCI: 00:1c.7
[DEBUG]     PCI: 00:1d.0
[SPEW ]     PCI: 00:1d.0 resource base 84507000 size 400 align 12 gran 10 limit 845073ff flags 60000200 index 10
[DEBUG]     PCI: 00:1e.0
[DEBUG]     PCI: 00:1f.0 child on link 0 PNP: 004e.3
[SPEW ]     PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
[SPEW ]     PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
[SPEW ]     PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
[SPEW ]     PCI: 00:1f.0 resource base fe00 size fc align 0 gran 0 limit 0 flags c0040100 index 10000200
[DEBUG]      PNP: 004e.3
[SPEW ]      PNP: 004e.3 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
[SPEW ]      PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
[SPEW ]      PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
[DEBUG]      PNP: 004e.4
[SPEW ]      PNP: 004e.4 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
[SPEW ]      PNP: 004e.4 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
[DEBUG]      PNP: 004e.5
[SPEW ]      PNP: 004e.5 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
[SPEW ]      PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
[DEBUG]     PCI: 00:1f.2
[SPEW ]     PCI: 00:1f.2 resource base 1028 size 8 align 3 gran 3 limit 102f flags 60000100 index 10
[SPEW ]     PCI: 00:1f.2 resource base 1038 size 4 align 2 gran 2 limit 103b flags 60000100 index 14
[SPEW ]     PCI: 00:1f.2 resource base 1030 size 8 align 3 gran 3 limit 1037 flags 60000100 index 18
[SPEW ]     PCI: 00:1f.2 resource base 103c size 4 align 2 gran 2 limit 103f flags 60000100 index 1c
[SPEW ]     PCI: 00:1f.2 resource base 1000 size 20 align 5 gran 5 limit 101f flags 60000100 index 20
[SPEW ]     PCI: 00:1f.2 resource base 84505000 size 800 align 12 gran 11 limit 845057ff flags 60000200 index 24
[DEBUG]     PCI: 00:1f.3
[SPEW ]     PCI: 00:1f.3 resource base 84508000 size 100 align 12 gran 8 limit 845080ff flags 60000201 index 10
[SPEW ]     PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
[DEBUG]     PCI: 00:1f.5
[DEBUG]     PCI: 00:1f.6
[SPEW ]     PCI: 00:1f.6 resource base 84504000 size 1000 align 12 gran 12 limit 84504fff flags 60000201 index 10
[INFO ]  Done allocating resources.
[DEBUG]  BS: BS_DEV_RESOURCES run times (exec / console): 1 / 2313 ms
[INFO ]  Enabling resources...
[DEBUG]  PCI: 00:00.0 subsystem <- 103c/146d
[DEBUG]  PCI: 00:00.0 cmd <- 06
[DEBUG]  PCI: 00:02.0 subsystem <- 103c/146d
[DEBUG]  PCI: 00:02.0 cmd <- 03
[DEBUG]  PCI: 00:16.0 subsystem <- 103c/146d
[DEBUG]  PCI: 00:16.0 cmd <- 06
[DEBUG]  PCI: 00:1a.0 subsystem <- 103c/146d
[DEBUG]  PCI: 00:1a.0 cmd <- 102
[DEBUG]  PCI: 00:1b.0 subsystem <- 103c/146d
[DEBUG]  PCI: 00:1b.0 cmd <- 102
[DEBUG]  PCI: 00:1c.0 bridge ctrl <- 0013
[DEBUG]  PCI: 00:1c.0 cmd <- 100
[DEBUG]  PCI: 00:1c.1 bridge ctrl <- 0013
[DEBUG]  PCI: 00:1c.1 cmd <- 100
[DEBUG]  PCI: 00:1c.2 bridge ctrl <- 0013
[DEBUG]  PCI: 00:1c.2 cmd <- 100
[DEBUG]  PCI: 00:1c.3 bridge ctrl <- 0013
[DEBUG]  PCI: 00:1c.3 cmd <- 106
[DEBUG]  PCI: 00:1c.4 bridge ctrl <- 0013
[DEBUG]  PCI: 00:1c.4 cmd <- 100
[DEBUG]  PCI: 00:1c.5 bridge ctrl <- 0013
[DEBUG]  PCI: 00:1c.5 cmd <- 100
[DEBUG]  PCI: 00:1d.0 subsystem <- 103c/146d
[DEBUG]  PCI: 00:1d.0 cmd <- 102
[DEBUG]  PCI: 00:1f.0 subsystem <- 103c/146d
[DEBUG]  PCI: 00:1f.0 cmd <- 107
[DEBUG]  PCI: 00:1f.2 subsystem <- 103c/146d
[DEBUG]  PCI: 00:1f.2 cmd <- 03
[DEBUG]  PCI: 00:1f.3 subsystem <- 103c/146d
[DEBUG]  PCI: 00:1f.3 cmd <- 103
[DEBUG]  PCI: 00:1f.6 subsystem <- 103c/146d
[DEBUG]  PCI: 00:1f.6 cmd <- 02
[DEBUG]  PCI: 04:00.0 cmd <- 02
[INFO ]  done.
[DEBUG]  BS: BS_DEV_ENABLE run times (exec / console): 0 / 140 ms
[INFO ]  Initializing devices...
[DEBUG]  Root Device init
[DEBUG]  Root Device init finished in 0 msecs
[DEBUG]  CPU_CLUSTER: 0 init
[DEBUG]  MTRR: Physical address space:
[DEBUG]  0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
[DEBUG]  0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
[DEBUG]  0x00000000000c0000 - 0x000000007f800000 size 0x7f740000 type 6
[DEBUG]  0x000000007f800000 - 0x00000000d0000000 size 0x50800000 type 0
[DEBUG]  0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
[DEBUG]  0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
[DEBUG]  0x0000000100000000 - 0x0000000174000000 size 0x74000000 type 6
[DEBUG]  MTRR: Fixed MSR 0x250 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x258 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x259 0x0000000000000000
[DEBUG]  MTRR: Fixed MSR 0x268 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x269 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26a 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26b 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26c 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26d 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26e 0x0606060606060606
[DEBUG]  MTRR: Fixed MSR 0x26f 0x0606060606060606
[SPEW ]  call enable_fixed_mtrr()
[DEBUG]  CPU physical address size: 36 bits
[DEBUG]  MTRR: default type WB/UC MTRR counts: 5/4.
[DEBUG]  MTRR: UC selected as default type.
[DEBUG]  MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6
[DEBUG]  MTRR: 1 base 0x000000007f800000 mask 0x0000000fff800000 type 0
[DEBUG]  MTRR: 2 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
[DEBUG]  MTRR: 3 base 0x0000000100000000 mask 0x0000000f80000000 type 6

[DEBUG]  MTRR check
[DEBUG]  Fixed MTRRs   : Enabled
[DEBUG]  Variable MTRRs: Enabled

[DEBUG]  CPU has 2 cores, 4 threads enabled.
[DEBUG]  Setting up SMI for CPU
[INFO ]  Will perform SMM setup.
[DEBUG]  FMAP: area COREBOOT found @ 210200 (2031104 bytes)
[INFO ]  CBFS: Found 'cpu_microcode_blob.bin' @0x113c0 size 0x3400 in mcache @0x7f7dd0ac
[DEBUG]  microcode: sig=0x20655 pf=0x10 revision=0x7
[INFO ]  CPU: Intel(R) Core(TM) i5 CPU       M 450  @ 2.40GHz.
[INFO ]  LAPIC 0x0 in XAPIC mode.
[DEBUG]  Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
[DEBUG]  Processing 18 relocs. Offset value of 0x00030000
[DEBUG]  Attempting to start 3 APs
[DEBUG]  Waiting for 10ms after sending INIT.
[DEBUG]  Waiting for SIPI to complete...
[INFO ]  LAPIC 0x1 in XAPIC mode.
[INFO ]  LAPIC 0x5 in XAPIC mode.
[INFO ]  AP: slot 3 apic_id 1, MCU rev: 0x00000007
[DEBUG]  done.
[INFO ]  AP: slot 1 apic_id 5, MCU rev: 0x00000007
[DEBUG]  Waiting for SIPI to complete...
[DEBUG]  done.
[INFO ]  LAPIC 0x4 in XAPIC mode.
[INFO ]  AP: slot 2 apic_id 4, MCU rev: 0x00000007
[SPEW ]  smm_setup_relocation_handler: enter
[SPEW ]  smm_setup_relocation_handler: exit
[DEBUG]  Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e0 memsize: 0x1e0
[DEBUG]  Processing 11 relocs. Offset value of 0x00038000
[DEBUG]  smm_module_setup_stub: stack_top = 0x7f801000
[DEBUG]  smm_module_setup_stub: per cpu stack_size = 0x400
[DEBUG]  smm_module_setup_stub: runtime.start32_offset = 0x4c
[DEBUG]  smm_module_setup_stub: runtime.smm_size = 0x10000
[DEBUG]  SMM Module: stub loaded at 38000. Will call 0x7f7a4a78
[DEBUG]  Installing permanent SMM handler to 0x7f800000
[DEBUG]  smm_load_module: total_smm_space_needed 8108, available -> 700000
[DEBUG]  Loading module at 0x7fef9000 with entry 0x7fefa115. filesize: 0x28f0 memsize: 0x6908
[DEBUG]  Processing 195 relocs. Offset value of 0x7fef9000
[DEBUG]  smm_load_module: smram_start: 0x7f800000
[DEBUG]  smm_load_module: smram_end: 7ff00000
[DEBUG]  smm_load_module: handler start 0x7fefa115
[DEBUG]  smm_load_module: handler_size 6a10
[DEBUG]  smm_load_module: fxsave_area 0x7feff800
[DEBUG]  smm_load_module: fxsave_size 800
[DEBUG]  smm_load_module: CONFIG_MSEG_SIZE 0x0
[DEBUG]  smm_load_module: CONFIG_BIOS_RESOURCE_LIST_SIZE 0x0
[DEBUG]  smm_load_module: handler_mod_params.smbase = 0x7f800000
[DEBUG]  smm_load_module: per_cpu_save_state_size = 0x400
[DEBUG]  smm_load_module: num_cpus = 0x4
[DEBUG]  smm_load_module: total_save_state_size = 0x1000
[DEBUG]  smm_load_module: cpu0 entry: 7fee9000
[DEBUG]  smm_create_map: cpus allowed in one segment 30
[DEBUG]  smm_create_map: min # of segments needed 1
[DEBUG]  CPU 0x0
[DEBUG]      smbase 7fee9000  entry 7fef1000
[DEBUG]             ss_start 7fef8c00  code_end 7fef11e0
[DEBUG]  CPU 0x1
[DEBUG]      smbase 7fee8c00  entry 7fef0c00
[DEBUG]             ss_start 7fef8800  code_end 7fef0de0
[DEBUG]  CPU 0x2
[DEBUG]      smbase 7fee8800  entry 7fef0800
[DEBUG]             ss_start 7fef8400  code_end 7fef09e0
[DEBUG]  CPU 0x3
[DEBUG]      smbase 7fee8400  entry 7fef0400
[DEBUG]             ss_start 7fef8000  code_end 7fef05e0
[DEBUG]  Loading module at 0x7fef1000 with entry 0x7fef1000. filesize: 0x1e0 memsize: 0x1e0
[DEBUG]  Processing 11 relocs. Offset value of 0x7fef1000
[INFO ]  smm_place_entry_code: smbase 7fee8400, stack_top 7f801000
[DEBUG]  SMM Module: placing smm entry code at 7fef0c00,  cpu # 0x1
[DEBUG]  smm_place_entry_code: copying from 7fef1000 to 7fef0c00 0x1e0 bytes
[DEBUG]  SMM Module: placing smm entry code at 7fef0800,  cpu # 0x2
[DEBUG]  smm_place_entry_code: copying from 7fef1000 to 7fef0800 0x1e0 bytes
[DEBUG]  SMM Module: placing smm entry code at 7fef0400,  cpu # 0x3
[DEBUG]  smm_place_entry_code: copying from 7fef1000 to 7fef0400 0x1e0 bytes
[DEBUG]  smm_module_setup_stub: stack_top = 0x7f801000
[DEBUG]  smm_module_setup_stub: per cpu stack_size = 0x400
[DEBUG]  smm_module_setup_stub: runtime.start32_offset = 0x4c
[DEBUG]  smm_module_setup_stub: runtime.smm_size = 0x700000
[DEBUG]  SMM Module: stub loaded at 7fef1000. Will call 0x7fefa115
[DEBUG]  Initializing southbridge SMI... ... pmbase = 0x0500

[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7fee9000, cpu = 0
[DEBUG]  In relocation handler: cpu 0
[DEBUG]  New SMBASE=0x7fee9000
[SPEW ]  SMM revision: 0x00030101
[DEBUG]  Writing SMRR. base = 0x7f800006, mask=0xff800800
[DEBUG]  Relocation complete.
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7fee8400, cpu = 3
[INFO ]  microcode: Update skipped, already up-to-date
[DEBUG]  In relocation handler: cpu 3
[DEBUG]  New SMBASE=0x7fee8400
[SPEW ]  SMM revision: 0x00030101
[DEBUG]  Writing SMRR. base = 0x7f800006, mask=0xff800800
[DEBUG]  Relocation complete.
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7fee8c00, cpu = 1
[DEBUG]  In relocation handler: cpu 1
[DEBUG]  New SMBASE=0x7fee8c00
[SPEW ]  SMM revision: 0x00030101
[DEBUG]  Writing SMRR. base = 0x7f800006, mask=0xff800800
[DEBUG]  Relocation complete.
[INFO ]  smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7fee8800, cpu = 2
[INFO ]  microcode: Update skipped, already up-to-date
[DEBUG]  In relocation handler: cpu 2
[DEBUG]  New SMBASE=0x7fee8800
[SPEW ]  SMM revision: 0x00030101
[DEBUG]  Writing SMRR. base = 0x7f800006, mask=0xff800800
[DEBUG]  Relocation complete.
[INFO ]  microcode: Update skipped, already up-to-date
[INFO ]  Initializing CPU #0
[DEBUG]  CPU: vendor Intel device 20655
[DEBUG]  CPU: family 06, model 25, stepping 05
[INFO ]  CPU: Intel(R) Core(TM) i5 CPU       M 450  @ 2.40GHz.
[INFO ]  CPU:lapic=0, boot_cpu=1
[DEBUG]  VMX status: enabled
[DEBUG]  IA32_FEATURE_CONTROL status: locked
[DEBUG]  model_x065x: frequency set to 2394
[INFO ]  Turbo is available and visible
[INFO ]  CPU #0 initialized
[INFO ]  Initializing CPU #3
[INFO ]  Initializing CPU #2
[DEBUG]  CPU: vendor Intel device 20655
[DEBUG]  CPU: family 06, model 25, stepping 05
[DEBUG]  CPU: vendor Intel device 20655
[DEBUG]  CPU: family 06, model 25, stepping 05
[INFO ]  CPU: Intel(R) Core(TM) i5 CPU       M 450  @ 2.40GHz.
[INFO ]  CPU: Intel(R) Core(TM) i5 CPU       M 450  @ 2.40GHz.
[INFO ]  CPU:lapic=1, boot_cpu=0
[INFO ]  CPU:lapic=4, boot_cpu=0
[DEBUG]  VMX status: enabled
[DEBUG]  VMX status: enabled
[DEBUG]  IA32_FEATURE_CONTROL status: locked
[DEBUG]  IA32_FEATURE_CONTROL status: locked
[DEBUG]  model_x065x: frequency set to 2394
[INFO ]  CPU #3 initialized
[DEBUG]  model_x065x: frequency set to 2394
[INFO ]  Initializing CPU #1
[INFO ]  CPU #2 initialized
[DEBUG]  CPU: vendor Intel device 20655
[DEBUG]  CPU: family 06, model 25, stepping 05
[INFO ]  CPU: Intel(R) Core(TM) i5 CPU       M 450  @ 2.40GHz.
[INFO ]  CPU:lapic=5, boot_cpu=0
[DEBUG]  VMX status: enabled
[DEBUG]  IA32_FEATURE_CONTROL status: locked
[DEBUG]  model_x065x: frequency set to 2394
[INFO ]  CPU #1 initialized
[INFO ]  bsp_do_flight_plan done after 817 msecs.
[DEBUG]  Initializing southbridge SMI... ... pmbase = 0x0500

[DEBUG]  SMI_STS: 
[SPEW ]  PM1_STS: 
[SPEW ]  PM1_EN: 0
[DEBUG]  GPE0_STS: GPIO15 GPIO10 GPIO0 
[DEBUG]  ALT_GP_SMI_STS: GPI15 GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI6 GPI4 GPI2 GPI1 GPI0 
[DEBUG]  TCO_STS: 
[DEBUG]  Locking SMM.
[DEBUG]  CPU_CLUSTER: 0 init finished in 1125 msecs
[DEBUG]  PCI: 00:00.0 init
[DEBUG]  PCI: 00:00.0 init finished in 0 msecs
[DEBUG]  PCI: 00:02.0 init
[INFO ]  CBFS: Found 'vbt.bin' @0x30800 size 0x5ad in mcache @0x7f7dd1c4
[INFO ]  Found a VBT of 6144 bytes after decompression
[INFO ]  GMA: Found VBT in CBFS
[INFO ]  GMA: Found valid VBT in CBFS
[SPEW ]  Initializing VGA without OPROM.
[4.664581] CONFIG =>
[4.666479]   (Primary   =>
[4.668896]      (Port => LVDS    ,
[4.672004]       Framebuffer =>
[4.674851]         (Width     => 1366,
[4.678304]          Height    => 768,
[4.681670]          Start_X   => 0,
[4.684863]          Start_Y   => 0,
[4.688057]          Stride    => 1376,
[4.691510]          V_Stride  => 768,
[4.694876]          Tiling    => Linear ,
[4.698587]          Rotation  => No_Rotation,
[4.702645]          Offset => 0x00000000,
[4.706356]          BPC    => 8),
[4.709377]       Mode =>
[4.711620]         (Dotclock           => 69300000,
[4.716195]          H_Visible          => 1366,
[4.720425]          H_Sync_Begin       => 1398,
[4.724654]          H_Sync_End         => 1430,
[4.728884]          H_Total            => 1486,
[4.733114]          V_Visible          => 768,
[4.737258]          V_Sync_Begin       => 770,
[4.741401]          V_Sync_End         => 774,
[4.745544]          V_Total            => 782,
[4.749688]          H_Sync_Active_High => False,
[4.754003]          V_Sync_Active_High => False,
[4.758319]          BPC                => 5)),
[4.762462]    Secondary =>
[4.764879]      (Port => Disabled,
[4.767985]       Framebuffer =>
[4.770834]         (Width     => 1,
[4.774027]          Height    => 1,
[4.777222]          Start_X   => 0,
[4.780415]          Start_Y   => 0,
[4.783608]          Stride    => 1,
[4.786803]          V_Stride  => 1,
[4.789996]          Tiling    => Linear ,
[4.793709]          Rotation  => No_Rotation,
[4.797766]          Offset => 0x00000000,
[4.801477]          BPC    => 8),
[4.804499]       Mode =>
[4.806742]         (Dotclock           => 1000000,
[4.811231]          H_Visible          => 1,
[4.815201]          H_Sync_Begin       => 1,
[4.819172]          H_Sync_End         => 1,
[4.823142]          H_Total            => 1,
[4.827113]          V_Visible          => 1,
[4.831084]          V_Sync_Begin       => 1,
[4.835054]          V_Sync_End         => 1,
[4.839025]          V_Total            => 1,
[4.842996]          H_Sync_Active_High => False,
[4.847312]          V_Sync_Active_High => False,
[4.851627]          BPC                => 5)),
[4.855770]    Tertiary  =>
[4.858186]      (Port => Disabled,
[4.861294]       Framebuffer =>
[4.864142]         (Width     => 1,
[4.867336]          Height    => 1,
[4.870529]          Start_X   => 0,
[4.873723]          Start_Y   => 0,
[4.876916]          Stride    => 1,
[4.880110]          V_Stride  => 1,
[4.883303]          Tiling    => Linear ,
[4.887014]          Rotation  => No_Rotation,
[4.891072]          Offset => 0x00000000,
[4.894783]          BPC    => 8),
[4.897803]       Mode =>
[4.900048]         (Dotclock           => 1000000,
[4.904536]          H_Visible          => 1,
[4.908506]          H_Sync_Begin       => 1,
[4.912477]          H_Sync_End         => 1,
[4.916448]          H_Total            => 1,
[4.920419]          V_Visible          => 1,
[4.924389]          V_Sync_Begin       => 1,
[4.928360]          V_Sync_End         => 1,
[4.932330]          V_Total            => 1,
[4.936301]          H_Sync_Active_High => False,
[4.940616]          V_Sync_Active_High => False,
[4.944933]          BPC                => 5)));
framebuffer_info: bytes_per_line: 5504, bits_per_pixel: 32
[INFO ]                     x_res x y_res: 1366 x 768, size: 4227072 at 0xd0000000
[DEBUG]  GT Power Management Init (post VBIOS)
[DEBUG]  PCI: 00:02.0 init finished in 546 msecs
[DEBUG]  PCI: 00:16.0 init
[DEBUG]  ME: FW Partition Table      : OK
[DEBUG]  ME: Bringup Loader Failure  : NO
[DEBUG]  ME: Firmware Init Complete  : YES
[DEBUG]  ME: Manufacturing Mode      : YES
[DEBUG]  ME: Boot Options Present    : NO
[DEBUG]  ME: Update In Progress      : NO
[DEBUG]  ME: Current Working State   : Normal
[DEBUG]  ME: Current Operation State : M0 without UMA but with error
[DEBUG]  ME: Current Operation Mode  : Normal
[DEBUG]  ME: Error Code              : No Error
[DEBUG]  ME: Progress Phase          : Policy Module
[DEBUG]  ME: Power Management Event  : Moff->Mx wake after an error
[DEBUG]  ME: Progress Phase State    : Entry into Policy Module
[NOTE ]  ME: BIOS path: Normal
[DEBUG]  ME: Extend SHA-256: 7c2166aa0f3c77f5b6f722166200effd9981c5dd607449de8d16e31847fe2559
[DEBUG]  PCI: 00:16.0 init finished in 78 msecs
[DEBUG]  PCI: 00:1a.0 init
[DEBUG]  EHCI: Setting up controller.. done.
[DEBUG]  PCI: 00:1a.0 init finished in 4 msecs
[DEBUG]  PCI: 00:1b.0 init
[DEBUG]  Azalia: base = 0x84500000
[DEBUG]  Azalia: V1CTL disabled.
[DEBUG]  Azalia: codec_mask = 0b
[DEBUG]  azalia_audio: Initializing codec #3
[DEBUG]  azalia_audio: codec viddid: 80862804
[DEBUG]  azalia_audio: verb_size: 16
[DEBUG]  azalia_audio: verb loaded.
[DEBUG]  azalia_audio: Initializing codec #1
[DEBUG]  azalia_audio: codec viddid: 11c11040
[DEBUG]  azalia_audio: No verb!
[DEBUG]  azalia_audio: Initializing codec #0
[DEBUG]  azalia_audio: codec viddid: 111d7603
[DEBUG]  azalia_audio: verb_size: 52
[DEBUG]  azalia_audio: verb loaded.
[DEBUG]  PCI: 00:1b.0 init finished in 62 msecs
[DEBUG]  PCI: 00:1d.0 init
[DEBUG]  EHCI: Setting up controller.. done.
[DEBUG]  PCI: 00:1d.0 init finished in 4 msecs
[DEBUG]  PCI: 00:1f.0 init
[DEBUG]  pch: lpc_init
[DEBUG]  IOAPIC: Initializing IOAPIC at 0xfec00000
[DEBUG]  IOAPIC: ID = 0x01
[SPEW ]  IOAPIC: Dumping registers
[SPEW ]    reg 0x0000: 0x01000000
[SPEW ]    reg 0x0001: 0x00170020
[SPEW ]    reg 0x0002: 0x00170020
[DEBUG]  IOAPIC: 24 interrupts
[DEBUG]  IOAPIC: Clearing IOAPIC at 0xfec00000
[SPEW ]  IOAPIC: vector 0x00 value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x01 value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x02 value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x03 value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x04 value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x05 value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x06 value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x07 value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x08 value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x09 value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x0a value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x0b value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x0c value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x0d value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x0e value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x0f value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x10 value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x11 value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x12 value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x13 value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x14 value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x15 value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x16 value 0x00000000 0x00010000
[SPEW ]  IOAPIC: vector 0x17 value 0x00000000 0x00010000
[DEBUG]  IOAPIC: Bootstrap Processor Local APIC = 0x00
[SPEW ]  IOAPIC: vector 0x00 value 0x00000000 0x00000700
[INFO ]  Set power off after power failure.
[INFO ]  NMI sources disabled.
[DEBUG]  Mobile 5 PM init
[DEBUG]  rtc_failed = 0x0
[DEBUG]  RTC Init
[DEBUG]  apm_control: Disabling ACPI.


[NOTE ]  coreboot-4.15-1556-g9d458a95bd-dirty Mon Feb 14 19:27:41 UTC 2022 smm starting (log level: 8)...

[SPEW ]  SMI# #2
[DEBUG]  SMI#: Disabling ACPI.
[DEBUG]  APMC done.
[DEBUG]  PCI: 00:1f.0 init finished in 222 msecs
[DEBUG]  PCI: 00:1f.2 init
[DEBUG]  SATA: Initializing...
[DEBUG]  SATA: Controller in AHCI mode.
[DEBUG]  ABAR: 0x84505000
[DEBUG]  PCI: 00:1f.2 init finished in 10 msecs
[DEBUG]  PCI: 00:1f.3 init
[DEBUG]  PCI: 00:1f.3 init finished in 0 msecs
[DEBUG]  PCI: 00:1f.6 init
[DEBUG]  Thermal init start.
[DEBUG]  Thermal init done.
[DEBUG]  PCI: 00:1f.6 init finished in 6 msecs
[DEBUG]  PCI: 04:00.0 init
[DEBUG]  PCI: 04:00.0 init finished in 0 msecs
[DEBUG]  PNP: 004e.4 init
[DEBUG]  PNP: 004e.4 init finished in 0 msecs
[INFO ]  Devices initialized
[SPEW ]  Show all devs... After init.
[SPEW ]  Root Device: enabled 1
[SPEW ]  CPU_CLUSTER: 0: enabled 1
[SPEW ]  DOMAIN: 0000: enabled 1
[SPEW ]  APIC: 00: enabled 1
[SPEW ]  PCI: 00:00.0: enabled 1
[SPEW ]  PCI: 00:01.0: enabled 0
[SPEW ]  PCI: 00:02.0: enabled 1
[SPEW ]  PCI: 00:16.0: enabled 1
[SPEW ]  PCI: 00:16.1: enabled 0
[SPEW ]  PCI: 00:16.2: enabled 0
[SPEW ]  PCI: 00:16.3: enabled 0
[SPEW ]  PCI: 00:19.0: enabled 0
[SPEW ]  PCI: 00:1a.0: enabled 1
[SPEW ]  PCI: 00:1b.0: enabled 1
[SPEW ]  PCI: 00:1c.0: enabled 1
[SPEW ]  PCI: 00:1c.1: enabled 1
[SPEW ]  PCI: 00:1c.2: enabled 1
[SPEW ]  PCI: 00:1c.3: enabled 1
[SPEW ]  PCI: 00:1c.4: enabled 1
[SPEW ]  PCI: 00:1c.5: enabled 1
[SPEW ]  PCI: 00:1c.6: enabled 0
[SPEW ]  PCI: 00:1c.7: enabled 0
[SPEW ]  PCI: 00:1d.0: enabled 1
[SPEW ]  PCI: 00:1e.0: enabled 0
[SPEW ]  PCI: 00:1f.0: enabled 1
[SPEW ]  PCI: 00:1f.2: enabled 1
[SPEW ]  PCI: 00:1f.3: enabled 1
[SPEW ]  PCI: 00:1f.5: enabled 0
[SPEW ]  PCI: 00:1f.6: enabled 1
[SPEW ]  PNP: 004e.3: enabled 0
[SPEW ]  PNP: 004e.4: enabled 1
[SPEW ]  PNP: 004e.5: enabled 0
[SPEW ]  PCI: 04:00.0: enabled 1
[SPEW ]  APIC: 05: enabled 1
[SPEW ]  APIC: 04: enabled 1
[SPEW ]  APIC: 01: enabled 1
[DEBUG]  BS: BS_DEV_INIT run times (exec / console): 989 / 1325 ms
[INFO ]  Finalize devices...
[DEBUG]  PCI: 00:1f.0 final
[DEBUG]  apm_control: Finalizing SMM.


[NOTE ]  coreboot-4.15-1556-g9d458a95bd-dirty Mon Feb 14 19:27:41 UTC 2022 smm starting (log level: 8)...

[SPEW ]  SMI# #0
[DEBUG]  SMI#: Finalizing SMM.
[DEBUG]  APMC done.
[INFO ]  Devices finalized
[DEBUG]  BS: BS_POST_DEVICE run times (exec / console): 17 / 16 ms
[INFO ]  CBFS: Found 'fallback/dsdt.aml' @0x2e700 size 0x20a9 in mcache @0x7f7dd198
[WARN ]  CBFS: 'fallback/slic' not found.
[INFO ]  ACPI: Writing ACPI tables at 7f74b000.
[DEBUG]  ACPI:    * FACS
[DEBUG]  ACPI:    * DSDT
[DEBUG]  ACPI:    * FADT
[DEBUG]  ACPI: added table 1/32, length now 40
[DEBUG]  ACPI:     * SSDT
[DEBUG]  Found 1 CPU(s) with 4 core(s) each.
[DEBUG]  PSS: 2401MHz power 25000 control 0x14 status 0x14
[DEBUG]  PSS: 2400MHz power 25000 control 0x12 status 0x12
[DEBUG]  PSS: 2266MHz power 23316 control 0x11 status 0x11
[DEBUG]  PSS: 2133MHz power 21689 control 0x10 status 0x10
[DEBUG]  PSS: 2000MHz power 20116 control 0xf status 0xf
[DEBUG]  PSS: 1866MHz power 18531 control 0xe status 0xe
[DEBUG]  PSS: 1733MHz power 17021 control 0xd status 0xd
[DEBUG]  PSS: 1600MHz power 15517 control 0xc status 0xc
[DEBUG]  PSS: 1466MHz power 14068 control 0xb status 0xb
[DEBUG]  PSS: 1333MHz power 12640 control 0xa status 0xa
[DEBUG]  PSS: 1200MHz power 11250 control 0x9 status 0x9
[DEBUG]  PSS: 2401MHz power 25000 control 0x14 status 0x14
[DEBUG]  PSS: 2400MHz power 25000 control 0x12 status 0x12
[DEBUG]  PSS: 2266MHz power 23316 control 0x11 status 0x11
[DEBUG]  PSS: 2133MHz power 21689 control 0x10 status 0x10
[DEBUG]  PSS: 2000MHz power 20116 control 0xf status 0xf
[DEBUG]  PSS: 1866MHz power 18531 control 0xe status 0xe
[DEBUG]  PSS: 1733MHz power 17021 control 0xd status 0xd
[DEBUG]  PSS: 1600MHz power 15517 control 0xc status 0xc
[DEBUG]  PSS: 1466MHz power 14068 control 0xb status 0xb
[DEBUG]  PSS: 1333MHz power 12640 control 0xa status 0xa
[DEBUG]  PSS: 1200MHz power 11250 control 0x9 status 0x9
[DEBUG]  PSS: 2401MHz power 25000 control 0x14 status 0x14
[DEBUG]  PSS: 2400MHz power 25000 control 0x12 status 0x12
[DEBUG]  PSS: 2266MHz power 23316 control 0x11 status 0x11
[DEBUG]  PSS: 2133MHz power 21689 control 0x10 status 0x10
[DEBUG]  PSS: 2000MHz power 20116 control 0xf status 0xf
[DEBUG]  PSS: 1866MHz power 18531 control 0xe status 0xe
[DEBUG]  PSS: 1733MHz power 17021 control 0xd status 0xd
[DEBUG]  PSS: 1600MHz power 15517 control 0xc status 0xc
[DEBUG]  PSS: 1466MHz power 14068 control 0xb status 0xb
[DEBUG]  PSS: 1333MHz power 12640 control 0xa status 0xa
[DEBUG]  PSS: 1200MHz power 11250 control 0x9 status 0x9
[DEBUG]  PSS: 2401MHz power 25000 control 0x14 status 0x14
[DEBUG]  PSS: 2400MHz power 25000 control 0x12 status 0x12
[DEBUG]  PSS: 2266MHz power 23316 control 0x11 status 0x11
[DEBUG]  PSS: 2133MHz power 21689 control 0x10 status 0x10
[DEBUG]  PSS: 2000MHz power 20116 control 0xf status 0xf
[DEBUG]  PSS: 1866MHz power 18531 control 0xe status 0xe
[DEBUG]  PSS: 1733MHz power 17021 control 0xd status 0xd
[DEBUG]  PSS: 1600MHz power 15517 control 0xc status 0xc
[DEBUG]  PSS: 1466MHz power 14068 control 0xb status 0xb
[DEBUG]  PSS: 1333MHz power 12640 control 0xa status 0xa
[DEBUG]  PSS: 1200MHz power 11250 control 0x9 status 0x9
[DEBUG]  Generating ACPI PIRQ entries
[SPEW ]  ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0
[SPEW ]  ACPI_PIRQ_GEN: PCI: 00:16.0: pin=0 pirq=0
[SPEW ]  ACPI_PIRQ_GEN: PCI: 00:1a.0: pin=0 pirq=3
[SPEW ]  ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=3
[SPEW ]  ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0
[SPEW ]  ACPI_PIRQ_GEN: PCI: 00:1c.1: pin=1 pirq=1
[SPEW ]  ACPI_PIRQ_GEN: PCI: 00:1c.2: pin=2 pirq=2
[SPEW ]  ACPI_PIRQ_GEN: PCI: 00:1c.3: pin=3 pirq=3
[SPEW ]  ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=2
[SPEW ]  ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=0 pirq=0
[SPEW ]  ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=1 pirq=0
[SPEW ]  ACPI_PIRQ_GEN: PCI: 00:1f.6: pin=3 pirq=1
[DEBUG]  ACPI: added table 2/32, length now 44
[DEBUG]  ACPI:    * MCFG
[DEBUG]  ACPI: added table 3/32, length now 48
[DEBUG]  ACPI:    * MADT
[DEBUG]  ACPI: added table 4/32, length now 52
[DEBUG]  current = 7f74e7e0
[DEBUG]  ACPI:    * HPET
[DEBUG]  ACPI: added table 5/32, length now 56
[INFO ]  ACPI: done.
[DEBUG]  ACPI tables: 14368 bytes.
[DEBUG]  smbios_write_tables: 7f74a000
[DEBUG]  SMBIOS firmware version is set to coreboot_version: '4.15-1556-g9d458a95bd-dirty'
[DEBUG]  SMBIOS tables: 582 bytes.
[DEBUG]  Writing table forward entry at 0x00000500
[DEBUG]  Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 9067
[DEBUG]  Writing coreboot table at 0x7f76f000
[DEBUG]   0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
[DEBUG]   1. 0000000000001000-000000000009ffff: RAM
[DEBUG]   2. 00000000000a0000-00000000000fffff: RESERVED
[DEBUG]   3. 0000000000100000-000000007f749fff: RAM
[DEBUG]   4. 000000007f74a000-000000007f789fff: CONFIGURATION TABLES
[DEBUG]   5. 000000007f78a000-000000007f7cefff: RAMSTAGE
[DEBUG]   6. 000000007f7cf000-000000007f7fffff: CONFIGURATION TABLES
[DEBUG]   7. 000000007f800000-0000000083ffffff: RESERVED
[DEBUG]   8. 00000000d0000000-00000000efffffff: RESERVED
[DEBUG]   9. 00000000fed00000-00000000fedfffff: RESERVED
[DEBUG]  10. 0000000100000000-0000000173ffffff: RAM
[DEBUG]  Wrote coreboot table at: 0x7f76f000, 0x3a8 bytes, checksum eec0
[DEBUG]  coreboot table: 960 bytes.
[DEBUG]  IMD ROOT    0. 0x7f7ff000 0x00001000
[DEBUG]  IMD SMALL   1. 0x7f7fe000 0x00001000
[DEBUG]  CONSOLE     2. 0x7f7de000 0x00020000
[DEBUG]  RO MCACHE   3. 0x7f7dd000 0x00000328
[DEBUG]  TIME STAMP  4. 0x7f7dc000 0x00000910
[DEBUG]  MRC DATA    5. 0x7f7db000 0x000005c8
[DEBUG]  ROMSTG STCK 6. 0x7f7da000 0x00001000
[DEBUG]  AFTER CAR   7. 0x7f7cf000 0x0000b000
[DEBUG]  RAMSTAGE    8. 0x7f789000 0x00046000
[DEBUG]  SMM BACKUP  9. 0x7f779000 0x00010000
[DEBUG]  IGD OPREGION10. 0x7f777000 0x00002000
[DEBUG]  COREBOOT   11. 0x7f76f000 0x00008000
[DEBUG]  ACPI       12. 0x7f74b000 0x00024000
[DEBUG]  SMBIOS     13. 0x7f74a000 0x00001000
[DEBUG]  IMD small region:
[DEBUG]    IMD ROOT    0. 0x7f7fec00 0x00000400
[DEBUG]    FMAP        1. 0x7f7feb20 0x000000e0
[DEBUG]    ROMSTAGE    2. 0x7f7feb00 0x00000004
[DEBUG]  BS: BS_WRITE_TABLES run times (exec / console): 5 / 589 ms
[INFO ]  CBFS: Found 'fallback/payload' @0x35fc0 size 0xb4464 in mcache @0x7f7dd238
[DEBUG]  Checking segment from ROM address 0xffe461ec
[DEBUG]  Checking segment from ROM address 0xffe46208
[DEBUG]  Loading segment from ROM address 0xffe461ec
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x00800000 memsize 0x410000 srcaddr 0xffe46224 filesize 0xb442c
[DEBUG]  Loading Segment: addr: 0x00800000 memsz: 0x0000000000410000 filesz: 0x00000000000b442c
[DEBUG]  using LZMA
[SPEW ]  [ 0x00800000, 00c10000, 0x00c10000) <- ffe46224
[DEBUG]  Loading segment from ROM address 0xffe46208
[DEBUG]    Entry Point 0x008008f0
[SPEW ]  Loaded segments
[DEBUG]  BS: BS_PAYLOAD_LOAD run times (exec / console): 375 / 66 ms
[DEBUG]  ICH-NM10-PCH: watchdog disabled
[DEBUG]  Jumping to boot code at 0x008008f0(0x7f76f000)
[SPEW ]  CPU0: stack: 0x7f7c2000 - 0x7f7c3000, lowest used address 0x7f7c287c, stack used: 1924 bytes


[NOTE ]  coreboot-4.15-1556-g9d458a95bd-dirty Mon Feb 14 19:27:41 UTC 2022 smm starting (log level: 8)...

[SPEW ]  SMI# #2
[SPEW ]  PM1_STS: TMROF 
[SPEW ]  PM1_EN: 120


[NOTE ]  coreboot-4.15-1556-g9d458a95bd-dirty Mon Feb 14 19:27:41 UTC 2022 smm starting (log level: 8)...

[SPEW ]  SMI# #2
3h

[NOTE ]  coreboot-4.15-1556-g9d458a95bd-dirty Mon Feb 14 19:27:41 UTC 2022 smm starting (log level: 8)...

[SPEW ]  SMI# #0
[DEBUG]  SMI#: Unknown APMC 0xcd.
[SPEW ]  PM1_STS: TMROF 
[SPEW ]  PM1_EN: 120