Nick: flx E-mail: none Board: rw14 Contents: coreboot-4.13-3465-g567d4dbacd-dirty Mon May 10 16:20:34 UTC 2021 bootblock starting (log level: 7)... CPU: Intel(R) Xeon(R) E-2176M CPU @ 2.70GHz CPU: ID 906ea, Coffeelake U0 (6+2), ucode: 000000dd CPU: AES supported, TXT supported, VT supported MCH: device id 3ec4 (rev 07) is Coffeelake-H PCH: device id a30e (rev 10) is Cannonlake-H CM246 IGD: device id 3e94 (rev 00) is Coffeelake-H Xeon GT2 PMC: Using default GPE route. FMAP: Found "FLASH" version 1.1 at 0x1850000. FMAP: base = 0xfe000000 size = 0x2000000 #areas = 5 FMAP: area COREBOOT found @ 1850200 (8060416 bytes) CBFS: mcache @0xfef21400 built for 15 files, used 0x378 of 0x2000 bytes CBFS: Found 'fallback/romstage' @0x80 size 0xcff0 in mcache @0xfef2142c BS: bootblock times (exec / console): total (unknown) / 65 ms coreboot-4.13-3465-g567d4dbacd-dirty Mon May 10 16:20:34 UTC 2021 romstage starting (log level: 7)... pm1_sts: 8100 pm1_en: 0100 pm1_cnt: 00001c00 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000 TCO_STS: 0000 0000 GEN_PMCON: e0801408 00000000 GBLRST_CAUSE: 00000000 00000000 prev_sleep_state 5 FMAP: area COREBOOT found @ 1850200 (8060416 bytes) CBFS: Found 'fspm.bin' @0x96dc0 size 0x88000 in mcache @0xfef21624 POST: 0x34 FMAP: area RW_MRC_CACHE found @ 1800000 (65536 bytes) POST: 0x36 POST: 0x92 POST: 0x98 CBMEM: IMD: root @ 0x89fff000 254 entries. IMD: root @ 0x89ffec00 62 entries. External stage cache: IMD: root @ 0x8abff000 254 entries. IMD: root @ 0x8abfec00 62 entries. FMAP: area RW_MRC_CACHE found @ 1800000 (65536 bytes) MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 MRC: 'RW_MRC_CACHE' does not need update. 4 DIMMs found SMM Memory Map SMRAM : 0x8a000000 0x1000000 Subregion 0: 0x8a000000 0xa00000 Subregion 1: 0x8aa00000 0x200000 Subregion 2: 0x8ac00000 0x400000 top_of_ram = 0x8a000000 MTRR Range: Start=89000000 End=8a000000 (Size 1000000) MTRR Range: Start=8a000000 End=8b000000 (Size 1000000) MTRR Range: Start=ff000000 End=0 (Size 1000000) Normal boot CBFS: Found 'fallback/postcar' @0x14ba00 size 0x4d78 in mcache @0xfef216a4 Loading module at 0x89ce2000 with entry 0x89ce2031. filesize: 0x4a50 memsize: 0x8d58 Processing 186 relocs. Offset value of 0x87ce2000 BS: romstage times (exec / console): total (unknown) / 143 ms coreboot-4.13-3465-g567d4dbacd-dirty Mon May 10 16:20:34 UTC 2021 postcar starting (log level: 7)... Normal boot FMAP: area COREBOOT found @ 1850200 (8060416 bytes) CBFS: Found 'fallback/ramstage' @0x725c0 size 0x20d3e in mcache @0x89d0d10c Loading module at 0x89c79000 with entry 0x89c79000. filesize: 0x49300 memsize: 0x67910 Processing 4669 relocs. Offset value of 0x88e79000 BS: postcar times (exec / console): total (unknown) / 34 ms coreboot-4.13-3465-g567d4dbacd-dirty Mon May 10 16:20:34 UTC 2021 ramstage starting (log level: 7)... POST: 0x39 POST: 0x80 Normal boot ACPI _SWS is PM1 Index 8 GPE Index -1 BS: BS_PRE_DEVICE entry times (exec / console): 0 / 3 ms POST: 0x70 BS: BS_PRE_DEVICE run times (exec / console): 0 / 1 ms FMAP: area COREBOOT found @ 1850200 (8060416 bytes) CBFS: Found 'cpu_microcode_blob.bin' @0xd100 size 0x65400 in mcache @0x89d0d0ac microcode: sig=0x906ea pf=0x20 revision=0xdd Skip microcode update CBFS: Found 'fsps.bin' @0x11fdc0 size 0x2bbd3 in mcache @0x89d0d264 Detected 6 core, 12 thread CPU. Setting up SMI for CPU IED base = 0x8ac00000 IED size = 0x00400000 Will perform SMM setup. CPU: Intel(R) Xeon(R) E-2176M CPU @ 2.70GHz. Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 11 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 3 apic_id 1, MCU rev: 0x000000dd done. AP: slot 1 apic_id 3, MCU rev: 0x000000dd AP: slot 2 apic_id 2, MCU rev: 0x000000dd AP: slot 6 apic_id 7, MCU rev: 0x000000dd AP: slot 10 apic_id 8, MCU rev: 0x000000dd AP: slot 11 apic_id 9, MCU rev: 0x000000dd AP: slot 9 apic_id 5, MCU rev: 0x000000dd AP: slot 8 apic_id 4, MCU rev: 0x000000dd AP: slot 4 apic_id 6, MCU rev: 0x000000dd Waiting for 2nd SIPI to complete...done. AP: slot 7 apic_id a, MCU rev: 0x000000dd AP: slot 5 apic_id b, MCU rev: 0x000000dd smm_stub_place_stacks: cpus: c : stack space: needed -> 3000 smm_stub_place_stacks: exit, stack_top 0x8a003000 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b0 memsize: 0x1b0 Processing 11 relocs. Offset value of 0x00038000 smm_module_setup_stub: stack_end = 0x8a000000 smm_module_setup_stub: stack_top = 0x8a003000 smm_module_setup_stub: stack_size = 0x400 smm_module_setup_stub: runtime.start32_offset = 0x4c smm_module_setup_stub: runtime.smm_size = 0x10000 SMM Module: stub loaded at 0x00038000. Will call 0x89c9da4b Installing permanent SMM handler to 0x8a000000 smm_load_module: total_smm_space_needed dd40, available -> a00000 Loading module at 0x8a9f9000 with entry 0x8a9f9934. filesize: 0x2490 memsize: 0x6540 Processing 149 relocs. Offset value of 0x8a9f9000 smm_load_module: smram_start: 0x0x8a000000 smm_load_module: smram_end: 0x8aa00000 smm_load_module: stack_top: 0x8a006000 smm_load_module: handler start 0x8a9f9934 smm_load_module: handler_size 7280 smm_load_module: fxsave_area 0x8a9fe800 smm_load_module: fxsave_size 1800 smm_load_module: CONFIG_MSEG_SIZE 0x0 smm_load_module: CONFIG_BIOS_RESOURCE_LIST_SIZE 0x0 smm_load_module: handler_mod_params.smbase = 0x8a000000 smm_load_module: per_cpu_save_state_size = 0x400 smm_load_module: num_cpus = 0xc smm_load_module: total_save_state_size = 0x3000 smm_load_module: cpu0 entry: 0x8a9e9000 smm_create_map: cpus allowed in one segment 30 smm_create_map: min # of segments needed 1 CPU 0x0 smbase 8a9e9000 entry 8a9f1000 ss_start 8a9f8c00 code_end 8a9f11b0 CPU 0x1 smbase 8a9e8c00 entry 8a9f0c00 ss_start 8a9f8800 code_end 8a9f0db0 CPU 0x2 smbase 8a9e8800 entry 8a9f0800 ss_start 8a9f8400 code_end 8a9f09b0 CPU 0x3 smbase 8a9e8400 entry 8a9f0400 ss_start 8a9f8000 code_end 8a9f05b0 CPU 0x4 smbase 8a9e8000 entry 8a9f0000 ss_start 8a9f7c00 code_end 8a9f01b0 CPU 0x5 smbase 8a9e7c00 entry 8a9efc00 ss_start 8a9f7800 code_end 8a9efdb0 CPU 0x6 smbase 8a9e7800 entry 8a9ef800 ss_start 8a9f7400 code_end 8a9ef9b0 CPU 0x7 smbase 8a9e7400 entry 8a9ef400 ss_start 8a9f7000 code_end 8a9ef5b0 CPU 0x8 smbase 8a9e7000 entry 8a9ef000 ss_start 8a9f6c00 code_end 8a9ef1b0 CPU 0x9 smbase 8a9e6c00 entry 8a9eec00 ss_start 8a9f6800 code_end 8a9eedb0 CPU 0xa smbase 8a9e6800 entry 8a9ee800 ss_start 8a9f6400 code_end 8a9ee9b0 CPU 0xb smbase 8a9e6400 entry 8a9ee400 ss_start 8a9f6000 code_end 8a9ee5b0 smm_stub_place_stacks: cpus: c : stack space: needed -> 6000 smm_stub_place_stacks: exit, stack_top 0x8a006000 Loading module at 0x8a9f1000 with entry 0x8a9f1000. filesize: 0x1b0 memsize: 0x1b0 Processing 11 relocs. Offset value of 0x8a9f1000 smm_place_entry_code: smbase 8a9e6400, stack_top 8a006000 SMM Module: placing smm entry code at 8a9f0c00, cpu # 0x1 smm_place_entry_code: copying from 8a9f1000 to 8a9f0c00 0x1b0 bytes SMM Module: placing smm entry code at 8a9f0800, cpu # 0x2 smm_place_entry_code: copying from 8a9f1000 to 8a9f0800 0x1b0 bytes SMM Module: placing smm entry code at 8a9f0400, cpu # 0x3 smm_place_entry_code: copying from 8a9f1000 to 8a9f0400 0x1b0 bytes SMM Module: placing smm entry code at 8a9f0000, cpu # 0x4 smm_place_entry_code: copying from 8a9f1000 to 8a9f0000 0x1b0 bytes SMM Module: placing smm entry code at 8a9efc00, cpu # 0x5 smm_place_entry_code: copying from 8a9f1000 to 8a9efc00 0x1b0 bytes SMM Module: placing smm entry code at 8a9ef800, cpu # 0x6 smm_place_entry_code: copying from 8a9f1000 to 8a9ef800 0x1b0 bytes SMM Module: placing smm entry code at 8a9ef400, cpu # 0x7 smm_place_entry_code: copying from 8a9f1000 to 8a9ef400 0x1b0 bytes SMM Module: placing smm entry code at 8a9ef000, cpu # 0x8 smm_place_entry_code: copying from 8a9f1000 to 8a9ef000 0x1b0 bytes SMM Module: placing smm entry code at 8a9eec00, cpu # 0x9 smm_place_entry_code: copying from 8a9f1000 to 8a9eec00 0x1b0 bytes SMM Module: placing smm entry code at 8a9ee800, cpu # 0xa smm_place_entry_code: copying from 8a9f1000 to 8a9ee800 0x1b0 bytes SMM Module: placing smm entry code at 8a9ee400, cpu # 0xb smm_place_entry_code: copying from 8a9f1000 to 8a9ee400 0x1b0 bytes smm_module_setup_stub: stack_end = 0x8a000000 smm_module_setup_stub: stack_top = 0x8a006000 smm_module_setup_stub: stack_size = 0x800 smm_module_setup_stub: runtime.start32_offset = 0x4c smm_module_setup_stub: runtime.smm_size = 0xa00000 SMM Module: stub loaded at 0x8a9f1000. Will call 0x8a9f9934 Clearing SMI status registers SMI_STS: GPI PM1 WAK PWRBTN TMROF smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9e9000, cpu = 0 In relocation handler: CPU 0 New SMBASE=0x8a9e9000 IEDBASE=0x8ac00000 Writing SMRR. base = 0x8a000006, mask=0xff000800 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9e8400, cpu = 3 In relocation handler: CPU 3 New SMBASE=0x8a9e8400 IEDBASE=0x8ac00000 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9e8c00, cpu = 1 In relocation handler: CPU 1 New SMBASE=0x8a9e8c00 IEDBASE=0x8ac00000 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9e8800, cpu = 2 In relocation handler: CPU 2 New SMBASE=0x8a9e8800 IEDBASE=0x8ac00000 Writing SMRR. base = 0x8a000006, mask=0xff000800 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9e7000, cpu = 8 In relocation handler: CPU 8 New SMBASE=0x8a9e7000 IEDBASE=0x8ac00000 Writing SMRR. base = 0x8a000006, mask=0xff000800 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9e6c00, cpu = 9 In relocation handler: CPU 9 New SMBASE=0x8a9e6c00 IEDBASE=0x8ac00000 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9e7800, cpu = 6 In relocation handler: CPU 6 New SMBASE=0x8a9e7800 IEDBASE=0x8ac00000 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9e8000, cpu = 4 In relocation handler: CPU 4 New SMBASE=0x8a9e8000 IEDBASE=0x8ac00000 Writing SMRR. base = 0x8a000006, mask=0xff000800 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9e6400, cpu = 11 In relocation handler: CPU 11 New SMBASE=0x8a9e6400 IEDBASE=0x8ac00000 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9e6800, cpu = 10 In relocation handler: CPU 10 New SMBASE=0x8a9e6800 IEDBASE=0x8ac00000 Writing SMRR. base = 0x8a000006, mask=0xff000800 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9e7400, cpu = 7 In relocation handler: CPU 7 New SMBASE=0x8a9e7400 IEDBASE=0x8ac00000 Writing SMRR. base = 0x8a000006, mask=0xff000800 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x8a9e7c00, cpu = 5 In relocation handler: CPU 5 New SMBASE=0x8a9e7c00 IEDBASE=0x8ac00000 Relocation complete. Initializing CPU #0 CPU: vendor Intel device 906ea CPU: family 06, model 9e, stepping 0a Clearing out pending MCEs Setting up local APIC... apic_id: 0x0 done. Turbo is available but hidden Turbo is available and visible VMX status: enabled IA32_FEATURE_CONTROL status: locked Skip microcode update CPU #0 initialized Initializing CPU #3 Initializing CPU #2 Initializing CPU #1 CPU: vendor Intel device 906ea CPU: family 06, model 9e, stepping 0a CPU: vendor Intel device 906ea CPU: family 06, model 9e, stepping 0a Clearing out pending MCEs Clearing out pending MCEs Setting up local APIC... Initializing CPU #7 Initializing CPU #5 CPU: vendor Intel device 906ea CPU: family 06, model 9e, stepping 0a CPU: vendor Intel device 906ea CPU: family 06, model 9e, stepping 0a Clearing out pending MCEs Clearing out pending MCEs Setting up local APIC... Initializing CPU #11 Initializing CPU #10 CPU: vendor Intel device 906ea CPU: family 06, model 9e, stepping 0a CPU: vendor Intel device 906ea CPU: family 06, model 9e, stepping 0a Clearing out pending MCEs Clearing out pending MCEs Setting up local APIC... Initializing CPU #6 Initializing CPU #4 CPU: vendor Intel device 906ea CPU: family 06, model 9e, stepping 0a Initializing CPU #8 Initializing CPU #9 CPU: vendor Intel device 906ea CPU: family 06, model 9e, stepping 0a CPU: vendor Intel device 906ea CPU: family 06, model 9e, stepping 0a Clearing out pending MCEs Clearing out pending MCEs Setting up local APIC... CPU: vendor Intel device 906ea CPU: family 06, model 9e, stepping 0a Clearing out pending MCEs Clearing out pending MCEs Setting up local APIC... CPU: vendor Intel device 906ea CPU: family 06, model 9e, stepping 0a Setting up local APIC... Setting up local APIC... Setting up local APIC... apic_id: 0x9 done. Setting up local APIC... Clearing out pending MCEs apic_id: 0x2 done. apic_id: 0x3 done. VMX status: enabled VMX status: enabled IA32_FEATURE_CONTROL status: locked IA32_FEATURE_CONTROL status: locked Skip microcode update CPU #2 initialized Skip microcode update CPU #1 initialized VMX status: enabled apic_id: 0x8 done. IA32_FEATURE_CONTROL status: locked VMX status: enabled Skip microcode update CPU #11 initialized IA32_FEATURE_CONTROL status: locked apic_id: 0x7 done. Setting up local APIC... Skip microcode update CPU #10 initialized Setting up local APIC... apic_id: 0x4 done. apic_id: 0x5 done. VMX status: enabled VMX status: enabled IA32_FEATURE_CONTROL status: locked IA32_FEATURE_CONTROL status: locked Skip microcode update CPU #8 initialized Skip microcode update CPU #9 initialized apic_id: 0x6 done. VMX status: enabled VMX status: enabled apic_id: 0xb done. apic_id: 0xa done. VMX status: enabled VMX status: enabled IA32_FEATURE_CONTROL status: locked apic_id: 0x1 done. Skip microcode update CPU #5 initialized IA32_FEATURE_CONTROL status: locked IA32_FEATURE_CONTROL status: locked IA32_FEATURE_CONTROL status: locked Skip microcode update CPU #4 initialized Skip microcode update CPU #6 initialized VMX status: enabled Skip microcode update CPU #7 initialized IA32_FEATURE_CONTROL status: locked Skip microcode update CPU #3 initialized bsp_do_flight_plan done after 911 msecs. CPU: frequency set to 4400 MHz Enabling SMIs. Locking SMM. BS: BS_DEV_INIT_CHIPS entry times (exec / console): 516 / 535 ms POST: 0x71 WEAK: src/soc/intel/cannonlake/fsp_params.c/mainboard_silicon_init_params called ERROR: Unknown MCH (0x3ec4) in load_table ERROR: Unknown MCH (0x3ec4) in load_table ERROR: Unknown MCH (0x3ec4) in load_table ERROR: Unknown MCH (0x3ec4) in load_table POST: 0x93 FSPS returned 0 POST: 0x99 Display FSP Version Info HOB Reference Code - CPU = 7.0.74.20 uCode Version = 0.0.0.de TXT ACM version = ff.ff.ff.ffff Reference Code - ME = 7.0.74.20 MEBx version = 0.0.0.0 ME Firmware Version = Corporate SKU Reference Code - CNL PCH = 7.0.74.20 PCH-CRID Status = Disabled PCH-CRID Original Value = ff.ff.ff.ffff PCH-CRID New Value = ff.ff.ff.ffff OPROM - RST - RAID = ff.ff.ff.ffff CNL PCH H A0 Hsio Version = 2.0.0.0 CNL PCH H Ax Hsio Version = 9.0.0.0 CNL PCH H Bx Hsio Version = d.0.0.0 CNL PCH LP B0 Hsio Version = 7.0.0.0 CNL PCH LP Bx Hsio Version = 6.0.0.0 CNL PCH LP Dx Hsio Version = 8.0.0.0 Reference Code - SA - System Agent = 7.0.74.20 Reference Code - MRC = 0.7.1.77 SA - PCIe Version = 7.0.74.20 SA-CRID Status = Disabled SA-CRID Original Value = 0.0.0.7 SA-CRID New Value = 0.0.0.7 OPROM - VBIOS = ff.ff.ff.ffff Found PCIe Root Port #3 at PCI: 00:1c.0. Found PCIe Root Port #6 at PCI: 00:1c.5. Found PCIe Root Port #7 at PCI: 00:1c.6. Found PCIe Root Port #8 at PCI: 00:1c.7. Found PCIe Root Port #9 at PCI: 00:1d.0. Found PCIe Root Port #21 at PCI: 00:1b.0. Remapping PCIe Root Port #3 from PCI: 00:1c.2 to new function number 0. pcie_rp_update_dev: Couldn't find PCIe Root Port #5 (originally PCI: 00:1c.4) which was enabled in devicetree, removing. Remapping PCIe Root Port #21 from PCI: 00:1b.4 to new function number 0. BS: BS_DEV_INIT_CHIPS run times (exec / console): 1340 / 160 ms RTC Init Set power on after power failure. PMC: Using default GPE route. Disabling Deep S3 Disabling Deep S3 Disabling Deep S4 Disabling Deep S4 Disabling Deep S5 Disabling Deep S5 BS: BS_DEV_INIT_CHIPS exit times (exec / console): 1 / 18 ms POST: 0x72 Enumerating buses... Root Device scanning... CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 PCI: 00:00.0 [8086/3ec4] enabled PCI: 00:02.0 [8086/3e94] enabled PCI: 00:04.0 [8086/1903] enabled PCI: 00:08.0 [8086/1911] disabled PCI: 00:12.0 [8086/a379] enabled PCI: 00:14.0 [8086/a36d] enabled PCI: 00:14.2 [8086/a36f] enabled PCI: 00:16.0 [8086/a360] enabled PCI: 00:17.0 [8086/a353] enabled PCI: 00:1b.0 [8086/a32c] disabled PCI: 00:1c.0 [8086/a33a] enabled PCI: 00:1c.5 [8086/a33d] enabled PCI: 00:1c.6 [8086/a33e] enabled PCI: 00:1c.7 [8086/a33f] enabled PCI: 00:1d.0 [8086/a330] enabled PCI: 00:1f.0 [8086/a30e] enabled PCI: 00:1f.1 [0000/0000] hidden PCI: 00:1f.2 [0000/0000] hidden PCI: 00:1f.3 [8086/a348] enabled PCI: 00:1f.4 [8086/a323] enabled PCI: 00:1f.5 [8086/a324] enabled PCI: 00:1f.6 [8086/15bb] enabled POST: 0x25 PCI: Leftover static devices: PCI: 00:05.0 PCI: 00:12.5 PCI: 00:12.6 PCI: 00:13.0 PCI: 00:14.1 PCI: 00:14.3 PCI: 00:14.5 PCI: 00:15.0 PCI: 00:15.1 PCI: 00:15.2 PCI: 00:15.3 PCI: 00:16.1 PCI: 00:16.2 PCI: 00:16.3 PCI: 00:16.4 PCI: 00:16.5 PCI: 00:19.0 PCI: 00:19.1 PCI: 00:19.2 PCI: 00:1a.0 PCI: 00:1e.0 PCI: 00:1e.1 PCI: 00:1e.2 PCI: 00:1e.3 PCI: 00:1f.7 PCI: Check your devicetree.cb. PCI: 00:02.0 scanning... scan_bus: bus PCI: 00:02.0 finished in 0 msecs PCI: 00:14.0 scanning... scan_bus: bus PCI: 00:14.0 finished in 0 msecs PCI: 00:1c.0 scanning... PCI: 00:1c.0: No LTR support PCI: pci_scan_bus for bus 01 POST: 0x24 PCI: 01:00.0 [8086/2526] enabled POST: 0x25 POST: 0x55 Enabling Common Clock Configuration L1 Sub-State supported from root port 28 L1 Sub-State Support = 0xf CommonModeRestoreTime = 0x28 Power On Value = 0x16, Power On Scale = 0x0 ASPM: Enabled L1 PCIe: Max_Payload_Size adjusted to 128 scan_bus: bus PCI: 00:1c.0 finished in 36 msecs PCI: 00:1c.5 scanning... PCI: 00:1c.5: No LTR support PCI: pci_scan_bus for bus 02 POST: 0x24 POST: 0x25 POST: 0x55 scan_bus: bus PCI: 00:1c.5 finished in 9 msecs PCI: 00:1c.6 scanning... PCI: 00:1c.6: No LTR support PCI: pci_scan_bus for bus 03 POST: 0x24 PCI: 03:00.0 [8086/1533] enabled POST: 0x25 POST: 0x55 Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint ASPM: Enabled L1 PCIe: Max_Payload_Size adjusted to 128 PCI: 03:00.0: No LTR support scan_bus: bus PCI: 00:1c.6 finished in 28 msecs PCI: 00:1c.7 scanning... PCI: 00:1c.7: No LTR support PCI: pci_scan_bus for bus 04 POST: 0x24 POST: 0x25 POST: 0x55 scan_bus: bus PCI: 00:1c.7 finished in 9 msecs PCI: 00:1d.0 scanning... PCI: 00:1d.0: No LTR support PCI: pci_scan_bus for bus 05 POST: 0x24 POST: 0x25 POST: 0x55 scan_bus: bus PCI: 00:1d.0 finished in 9 msecs PCI: 00:1f.0 scanning... PNP: 0c31.0 enabled PNP: 002e.1 enabled PNP: 002e.2 enabled PNP: 002e.3 disabled PNP: 002e.4 enabled PNP: 002e.5 disabled PNP: 002e.6 disabled PNP: 002e.7 enabled PNP: 002e.8 enabled PNP: 002e.9 enabled PNP: 002e.a disabled PNP: 002e.b disabled PNP: 002e.c disabled scan_bus: bus PCI: 00:1f.0 finished in 29 msecs PCI: 00:1f.1 scanning... scan_bus: bus PCI: 00:1f.1 finished in 0 msecs PCI: 00:1f.2 scanning... scan_bus: bus PCI: 00:1f.2 finished in 0 msecs PCI: 00:1f.3 scanning... scan_bus: bus PCI: 00:1f.3 finished in 0 msecs PCI: 00:1f.4 scanning... scan_bus: bus PCI: 00:1f.4 finished in 0 msecs PCI: 00:1f.5 scanning... scan_bus: bus PCI: 00:1f.5 finished in 0 msecs POST: 0x55 scan_bus: bus DOMAIN: 0000 finished in 334 msecs scan_bus: bus Root Device finished in 347 msecs done BS: BS_DEV_ENUMERATE run times (exec / console): 5 / 354 ms MRC: Could not find region 'UNIFIED_MRC_CACHE' FMAP: area RW_MRC_CACHE found @ 1800000 (65536 bytes) MRC: NOT enabling PRR for 'RW_MRC_CACHE'. BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 14 ms POST: 0x73 found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Done reading resources. ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0x3fff] mem PCI: 00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:1c.6 io: size: 0 align: 12 gran: 12 limit: ffff PCI: 03:00.0 18 * [0x0 - 0x1f] io PCI: 00:1c.6 io: size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:1c.6 mem: size: 0 align: 20 gran: 20 limit: ffffffff PCI: 03:00.0 10 * [0x0 - 0xfffff] mem PCI: 03:00.0 1c * [0x100000 - 0x103fff] mem PCI: 00:1c.6 mem: size: 200000 align: 20 gran: 20 limit: ffffffff done PCI: 00:1c.6 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:1c.6 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed) update_constraints: PCI: 00:1f.0 20 base 00001800 limit 000018ff io (fixed) update_constraints: PNP: 002e.1 60 base 000003f8 limit 000003ff io (fixed) update_constraints: PNP: 002e.2 60 base 000002f8 limit 000002ff io (fixed) update_constraints: PNP: 002e.4 60 base 00000a40 limit 00000a47 io (fixed) update_constraints: PNP: 002e.4 62 base 00000a30 limit 00000a33 io (fixed) update_constraints: PNP: 002e.7 60 base 00000a10 limit 00000a13 io (fixed) update_constraints: PNP: 002e.7 62 base 00000a00 limit 00000a00 io (fixed) update_constraints: PNP: 002e.8 60 base 000003e8 limit 000003ef io (fixed) update_constraints: PNP: 002e.9 60 base 000002e8 limit 000002ef io (fixed) update_constraints: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed) DOMAIN: 0000: Resource ranges: * Base: 1000, Size: 800, Tag: 100 * Base: 1900, Size: d6a0, Tag: 100 * Base: efc0, Size: 1040, Tag: 100 PCI: 00:1c.6 1c * [0x2000 - 0x2fff] limit: 2fff io PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io PCI: 00:17.0 20 * [0x1040 - 0x105f] limit: 105f io PCI: 00:17.0 18 * [0x1060 - 0x1067] limit: 1067 io PCI: 00:17.0 1c * [0x1068 - 0x106b] limit: 106b io DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff update_constraints: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed) update_constraints: PCI: 00:00.0 01 base fed10000 limit fed17fff mem (fixed) update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed) update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed) update_constraints: PCI: 00:00.0 04 base fc000000 limit fc000fff mem (fixed) update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed) update_constraints: PCI: 00:00.0 06 base fe000000 limit fe00ffff mem (fixed) update_constraints: PCI: 00:00.0 07 base fed90000 limit fed90fff mem (fixed) update_constraints: PCI: 00:00.0 08 base fed91000 limit fed91fff mem (fixed) update_constraints: PCI: 00:00.0 09 base 00000000 limit 0009ffff mem (fixed) update_constraints: PCI: 00:00.0 0a base 000c0000 limit 89ffffff mem (fixed) update_constraints: PCI: 00:00.0 0b base 8a000000 limit 8f7fffff mem (fixed) update_constraints: PCI: 00:00.0 0c base 100000000 limit 106c7fffff mem (fixed) update_constraints: PCI: 00:00.0 0d base 000a0000 limit 000bffff mem (fixed) update_constraints: PCI: 00:00.0 0e base 000c0000 limit 000fffff mem (fixed) update_constraints: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed) DOMAIN: 0000: Resource ranges: * Base: 8f800000, Size: 50800000, Tag: 200 * Base: f0000000, Size: c000000, Tag: 200 * Base: fc001000, Size: 1fff000, Tag: 200 * Base: fe010000, Size: d00000, Tag: 200 * Base: fed18000, Size: 28000, Tag: 200 * Base: fed45000, Size: 3b000, Tag: 200 * Base: fed84000, Size: c000, Tag: 200 * Base: fed92000, Size: e000, Tag: 200 * Base: feda2000, Size: 125e000, Tag: 200 * Base: 106c800000, Size: 6f93800000, Tag: 100200 PCI: 00:02.0 18 * [0x90000000 - 0x9fffffff] limit: 9fffffff prefmem PCI: 00:02.0 10 * [0xa0000000 - 0xa0ffffff] limit: a0ffffff mem PCI: 00:1c.6 20 * [0x8f800000 - 0x8f9fffff] limit: 8f9fffff mem PCI: 00:1c.0 20 * [0x8fa00000 - 0x8fafffff] limit: 8fafffff mem PCI: 00:1f.3 20 * [0x8fb00000 - 0x8fbfffff] limit: 8fbfffff mem PCI: 00:1f.6 10 * [0x8fc00000 - 0x8fc1ffff] limit: 8fc1ffff mem PCI: 00:14.0 10 * [0x8fc20000 - 0x8fc2ffff] limit: 8fc2ffff mem PCI: 00:04.0 10 * [0x8fc30000 - 0x8fc37fff] limit: 8fc37fff mem PCI: 00:1f.3 10 * [0x8fc38000 - 0x8fc3bfff] limit: 8fc3bfff mem PCI: 00:14.2 10 * [0x8fc3c000 - 0x8fc3dfff] limit: 8fc3dfff mem PCI: 00:17.0 10 * [0x8fc3e000 - 0x8fc3ffff] limit: 8fc3ffff mem PCI: 00:12.0 10 * [0x8fc40000 - 0x8fc40fff] limit: 8fc40fff mem PCI: 00:14.2 18 * [0x8fc41000 - 0x8fc41fff] limit: 8fc41fff mem PCI: 00:16.0 10 * [0x8fc42000 - 0x8fc42fff] limit: 8fc42fff mem PCI: 00:1f.5 10 * [0x8fc43000 - 0x8fc43fff] limit: 8fc43fff mem PCI: 00:17.0 24 * [0x8fc44000 - 0x8fc447ff] limit: 8fc447ff mem PCI: 00:17.0 14 * [0x8fc45000 - 0x8fc450ff] limit: 8fc450ff mem PCI: 00:1f.4 10 * [0x8fc46000 - 0x8fc460ff] limit: 8fc460ff mem DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done PCI: 00:1c.0 mem: base: 8fa00000 size: 100000 align: 20 gran: 20 limit: 8fafffff PCI: 00:1c.0: Resource ranges: * Base: 8fa00000, Size: 100000, Tag: 200 PCI: 01:00.0 10 * [0x8fa00000 - 0x8fa03fff] limit: 8fa03fff mem PCI: 00:1c.0 mem: base: 8fa00000 size: 100000 align: 20 gran: 20 limit: 8fafffff done PCI: 00:1c.6 io: base: 2000 size: 1000 align: 12 gran: 12 limit: 2fff PCI: 00:1c.6: Resource ranges: * Base: 2000, Size: 1000, Tag: 100 PCI: 03:00.0 18 * [0x2000 - 0x201f] limit: 201f io PCI: 00:1c.6 io: base: 2000 size: 1000 align: 12 gran: 12 limit: 2fff done PCI: 00:1c.6 mem: base: 8f800000 size: 200000 align: 20 gran: 20 limit: 8f9fffff PCI: 00:1c.6: Resource ranges: * Base: 8f800000, Size: 200000, Tag: 200 PCI: 03:00.0 10 * [0x8f800000 - 0x8f8fffff] limit: 8f8fffff mem PCI: 03:00.0 1c * [0x8f900000 - 0x8f903fff] limit: 8f903fff mem PCI: 00:1c.6 mem: base: 8f800000 size: 200000 align: 20 gran: 20 limit: 8f9fffff done === Resource allocator: DOMAIN: 0000 - resource allocation complete === PCI: 00:02.0 10 <- [0x00a0000000 - 0x00a0ffffff] size 0x01000000 gran 0x18 mem64 PCI: 00:02.0 18 <- [0x0090000000 - 0x009fffffff] size 0x10000000 gran 0x1c prefmem64 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io PCI: 00:04.0 10 <- [0x008fc30000 - 0x008fc37fff] size 0x00008000 gran 0x0f mem64 PCI: 00:12.0 10 <- [0x008fc40000 - 0x008fc40fff] size 0x00001000 gran 0x0c mem64 PCI: 00:14.0 10 <- [0x008fc20000 - 0x008fc2ffff] size 0x00010000 gran 0x10 mem64 PCI: 00:14.2 10 <- [0x008fc3c000 - 0x008fc3dfff] size 0x00002000 gran 0x0d mem64 PCI: 00:14.2 18 <- [0x008fc41000 - 0x008fc41fff] size 0x00001000 gran 0x0c mem64 PCI: 00:16.0 10 <- [0x008fc42000 - 0x008fc42fff] size 0x00001000 gran 0x0c mem64 PCI: 00:17.0 10 <- [0x008fc3e000 - 0x008fc3ffff] size 0x00002000 gran 0x0d mem PCI: 00:17.0 14 <- [0x008fc45000 - 0x008fc450ff] size 0x00000100 gran 0x08 mem PCI: 00:17.0 18 <- [0x0000001060 - 0x0000001067] size 0x00000008 gran 0x03 io PCI: 00:17.0 1c <- [0x0000001068 - 0x000000106b] size 0x00000004 gran 0x02 io PCI: 00:17.0 20 <- [0x0000001040 - 0x000000105f] size 0x00000020 gran 0x05 io PCI: 00:17.0 24 <- [0x008fc44000 - 0x008fc447ff] size 0x00000800 gran 0x0b mem PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:1c.0 20 <- [0x008fa00000 - 0x008fafffff] size 0x00100000 gran 0x14 bus 01 mem PCI: 01:00.0 10 <- [0x008fa00000 - 0x008fa03fff] size 0x00004000 gran 0x0e mem64 PCI: 00:1c.5 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:1c.5 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:1c.5 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 02 mem PCI: 00:1c.6 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 03 io PCI: 00:1c.6 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:1c.6 20 <- [0x008f800000 - 0x008f9fffff] size 0x00200000 gran 0x14 bus 03 mem PCI: 03:00.0 10 <- [0x008f800000 - 0x008f8fffff] size 0x00100000 gran 0x14 mem PCI: 03:00.0 18 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io PCI: 03:00.0 1c <- [0x008f900000 - 0x008f903fff] size 0x00004000 gran 0x0e mem PCI: 00:1c.7 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io PCI: 00:1c.7 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 04 prefmem PCI: 00:1c.7 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 04 mem PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 05 prefmem PCI: 00:1d.0 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 05 mem PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq WARNING: PNP: 002e.1 f0 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.1 f1 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.1 f2 irq size: 0x0000000001 not assigned in devicetree PNP: 002e.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq WARNING: PNP: 002e.2 f0 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.2 f1 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.2 f2 irq size: 0x0000000001 not assigned in devicetree PNP: 002e.4 60 <- [0x0000000a40 - 0x0000000a47] size 0x00000008 gran 0x03 io PNP: 002e.4 62 <- [0x0000000a30 - 0x0000000a33] size 0x00000004 gran 0x02 io PNP: 002e.4 70 <- [0x0000000009 - 0x0000000009] size 0x00000001 gran 0x00 irq WARNING: PNP: 002e.4 f0 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.4 f1 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.4 f2 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.4 f3 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.4 f4 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.4 f5 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.4 f6 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.4 fa irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.4 fb irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.4 fc irq size: 0x0000000001 not assigned in devicetree PNP: 002e.7 60 <- [0x0000000a10 - 0x0000000a13] size 0x00000004 gran 0x02 io PNP: 002e.7 62 <- [0x0000000a00 - 0x0000000a00] size 0x00000001 gran 0x00 io PNP: 002e.7 70 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 irq WARNING: PNP: 002e.7 f0 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.7 f1 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.7 f2 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.7 f3 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.7 f4 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.7 f5 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.7 f6 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.7 f7 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.7 f8 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.7 f9 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.7 fa irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.7 fb irq size: 0x0000000001 not assigned in devicetree PNP: 002e.8 60 <- [0x00000003e8 - 0x00000003ef] size 0x00000008 gran 0x03 io PNP: 002e.8 70 <- [0x000000000a - 0x000000000a] size 0x00000001 gran 0x00 irq WARNING: PNP: 002e.8 f0 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.8 f1 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.8 f2 irq size: 0x0000000001 not assigned in devicetree PNP: 002e.9 60 <- [0x00000002e8 - 0x00000002ef] size 0x00000008 gran 0x03 io PNP: 002e.9 70 <- [0x0000000005 - 0x0000000005] size 0x00000001 gran 0x00 irq WARNING: PNP: 002e.9 f0 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.9 f1 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.9 f2 irq size: 0x0000000001 not assigned in devicetree LPC: Cannot open IO window: 3f8 size 8 No more IO windows LPC: Cannot open IO window: 2f8 size 8 No more IO windows LPC: Cannot open IO window: 0 size 8 No more IO windows LPC: Cannot open IO window: 0 size 4 No more IO windows LPC: Cannot open IO window: a40 size 8 No more IO windows LPC: Cannot open IO window: a30 size 4 No more IO windows LPC: Cannot open IO window: 0 size 1 No more IO windows LPC: Cannot open IO window: 0 size 1 No more IO windows LPC: Cannot open IO window: a10 size 4 No more IO windows LPC: Cannot open IO window: a00 size 1 No more IO windows LPC: Cannot open IO window: 3e8 size 8 No more IO windows LPC: Cannot open IO window: 2e8 size 8 No more IO windows LPC: Cannot open IO window: 0 size 8 No more IO windows LPC: Cannot open IO window: 0 size 8 No more IO windows LPC: Cannot open IO window: 0 size 8 No more IO windows PCI: 00:1f.3 10 <- [0x008fc38000 - 0x008fc3bfff] size 0x00004000 gran 0x0e mem64 PCI: 00:1f.3 20 <- [0x008fb00000 - 0x008fbfffff] size 0x00100000 gran 0x14 mem64 PCI: 00:1f.4 10 <- [0x008fc46000 - 0x008fc460ff] size 0x00000100 gran 0x08 mem64 PCI: 00:1f.5 10 <- [0x008fc43000 - 0x008fc43fff] size 0x00001000 gran 0x0c mem PCI: 00:1f.6 10 <- [0x008fc00000 - 0x008fc1ffff] size 0x00020000 gran 0x11 mem Done setting resources. Done allocating resources. BS: BS_DEV_RESOURCES run times (exec / console): 6 / 1428 ms POST: 0x94 POST: 0x94 BS: BS_DEV_ENABLE entry times (exec / console): 1 / 2 ms POST: 0x74 Enabling resources... PCI: 00:00.0 subsystem <- 8086/3ec4 PCI: 00:00.0 cmd <- 06 PCI: 00:02.0 subsystem <- 8086/3e94 PCI: 00:02.0 cmd <- 03 PCI: 00:04.0 subsystem <- 8086/1903 PCI: 00:04.0 cmd <- 02 PCI: 00:12.0 subsystem <- 8086/a379 PCI: 00:12.0 cmd <- 02 PCI: 00:14.0 subsystem <- 8086/a36d PCI: 00:14.0 cmd <- 02 PCI: 00:14.2 subsystem <- 8086/a36f PCI: 00:14.2 cmd <- 02 PCI: 00:16.0 subsystem <- 8086/a360 PCI: 00:16.0 cmd <- 02 PCI: 00:17.0 subsystem <- 8086/a353 PCI: 00:17.0 cmd <- 03 PCI: 00:1c.0 bridge ctrl <- 0013 PCI: 00:1c.0 subsystem <- 8086/a33a PCI: 00:1c.0 cmd <- 06 PCI: 00:1c.5 bridge ctrl <- 0013 PCI: 00:1c.5 subsystem <- 8086/a33d PCI: 00:1c.5 cmd <- 00 PCI: 00:1c.6 bridge ctrl <- 0013 PCI: 00:1c.6 subsystem <- 8086/a33e PCI: 00:1c.6 cmd <- 07 PCI: 00:1c.7 bridge ctrl <- 0013 PCI: 00:1c.7 subsystem <- 8086/a33f PCI: 00:1c.7 cmd <- 00 PCI: 00:1d.0 bridge ctrl <- 0013 PCI: 00:1d.0 subsystem <- 8086/a330 PCI: 00:1d.0 cmd <- 00 PCI: 00:1f.0 subsystem <- 8086/a30e PCI: 00:1f.0 cmd <- 07 PCI: 00:1f.3 subsystem <- 8086/a348 PCI: 00:1f.3 cmd <- 02 PCI: 00:1f.4 subsystem <- 8086/a323 PCI: 00:1f.4 cmd <- 03 PCI: 00:1f.5 subsystem <- 8086/a324 PCI: 00:1f.5 cmd <- 406 PCI: 00:1f.6 subsystem <- 8086/15bb PCI: 00:1f.6 cmd <- 02 PCI: 01:00.0 cmd <- 02 PCI: 03:00.0 cmd <- 03 done. BS: BS_DEV_ENABLE run times (exec / console): 2 / 131 ms POST: 0x00 ME: Version: 12.0.47.1524 BS: BS_DEV_ENABLE exit times (exec / console): 12 / 4 ms Found TPM SLB9665 TT 2.0 by Infineon tlcl_send_startup: Startup return code is 0 TPM: setup succeeded BS: BS_DEV_INIT entry times (exec / console): 16 / 10 ms POST: 0x75 Initializing devices... POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:00.0 init CPU TDP = 45 Watts CPU PL1 = 45 Watts CPU PL2 = 56 Watts PCI: 00:00.0 init finished in 6 msecs POST: 0x75 PCI: 00:02.0 init CBFS: Found 'vbt.bin' @0x96040 size 0x4a1 in mcache @0x89d0d1f4 Found a VBT of 6144 bytes after decompression GMA: Found VBT in CBFS GMA: Found valid VBT in CBFS [4.692528] HW.GFX.GMA.Initialize [4.695710] HW.GFX.GMA.Panel.Setup_PP_Sequencer [4.700300] HW.GFX.GMA.Panel.Setup_PP_Sequencer [4.704894] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7208:PCH_PP_ON_DELAYS [4.712778] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c720c:PCH_PP_OFF_DELAYS [4.720724] HW.GFX.GMA.Registers.Read: 0x00000012 <- 0x000c7204:PCH_PP_CONTROL [4.728353] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_ON_DELAYS [4.735087] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7208:PCH_PP_ON_DELAYS [4.742910] HW.GFX.GMA.Registers.Write: 0x08340001 -> 0x000c7208:PCH_PP_ON_DELAYS [4.750790] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_OFF_DELAYS [4.757586] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c720c:PCH_PP_OFF_DELAYS [4.765503] HW.GFX.GMA.Registers.Write: 0x138801f4 -> 0x000c720c:PCH_PP_OFF_DELAYS [4.773483] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_CONTROL [4.779961] HW.GFX.GMA.Registers.Read: 0x00000012 <- 0x000c7204:PCH_PP_CONTROL [4.787621] HW.GFX.GMA.Registers.Write: 0x00000072 -> 0x000c7204:PCH_PP_CONTROL [4.795311] HW.GFX.GMA.Registers.Set_Mask: 0x00000002 .S PCH_PP_CONTROL [4.802208] HW.GFX.GMA.Registers.Read: 0x00000072 <- 0x000c7204:PCH_PP_CONTROL [4.809829] HW.GFX.GMA.Registers.Write: 0x00000072 -> 0x000c7204:PCH_PP_CONTROL [4.817517] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A [4.823234] HW.GFX.GMA.Registers.Read: 0x00000091 <- 0x00064000:DDI_BUF_CTL_A [4.830796] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL [4.837148] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c4030:SHOTPLUG_CTL [4.844584] HW.GFX.GMA.Registers.Write: 0x13000000 -> 0x000c4030:SHOTPLUG_CTL [4.852083] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP [4.857636] HW.GFX.GMA.Registers.Read: 0x00000107 <- 0x000c2014:SFUSE_STRAP [4.864981] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL [4.871320] HW.GFX.GMA.Registers.Read: 0x10000000 <- 0x000c4030:SHOTPLUG_CTL [4.878758] HW.GFX.GMA.Registers.Write: 0x10000013 -> 0x000c4030:SHOTPLUG_CTL [4.886260] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP [4.891813] HW.GFX.GMA.Registers.Read: 0x00000107 <- 0x000c2014:SFUSE_STRAP [4.899157] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL [4.905506] HW.GFX.GMA.Registers.Read: 0x10000010 <- 0x000c4030:SHOTPLUG_CTL [4.912944] HW.GFX.GMA.Registers.Write: 0x10001310 -> 0x000c4030:SHOTPLUG_CTL [4.920442] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP [4.925965] HW.GFX.GMA.Registers.Read: 0x00000107 <- 0x000c2014:SFUSE_STRAP [4.933335] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL [4.939680] HW.GFX.GMA.Registers.Read: 0x10001010 <- 0x000c4030:SHOTPLUG_CTL [4.947110] HW.GFX.GMA.Registers.Write: 0x10131010 -> 0x000c4030:SHOTPLUG_CTL [4.954608] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e00:DDI_BUF_TRANS_A_S0T1 [4.962810] HW.GFX.GMA.Registers.Write: 0x000000a0 -> 0x00064e04:DDI_BUF_TRANS_A_S0T2 [4.971046] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e08:DDI_BUF_TRANS_A_S1T1 [4.979280] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064e0c:DDI_BUF_TRANS_A_S1T2 [4.987518] HW.GFX.GMA.Registers.Write: 0x00007011 -> 0x00064e10:DDI_BUF_TRANS_A_S2T1 [4.995751] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e14:DDI_BUF_TRANS_A_S2T2 [5.003984] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064e18:DDI_BUF_TRANS_A_S3T1 [5.012222] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e1c:DDI_BUF_TRANS_A_S3T2 [5.020457] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e20:DDI_BUF_TRANS_A_S4T1 [5.028689] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064e24:DDI_BUF_TRANS_A_S4T2 [5.036922] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e28:DDI_BUF_TRANS_A_S5T1 [5.045158] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e2c:DDI_BUF_TRANS_A_S5T2 [5.053391] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e30:DDI_BUF_TRANS_A_S6T1 [5.061628] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e34:DDI_BUF_TRANS_A_S6T2 [5.069852] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e38:DDI_BUF_TRANS_A_S7T1 [5.078086] HW.GFX.GMA.Registers.Write: 0x00000097 -> 0x00064e3c:DDI_BUF_TRANS_A_S7T2 [5.086324] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e40:DDI_BUF_TRANS_A_S8T1 [5.094557] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e44:DDI_BUF_TRANS_A_S8T2 [5.102790] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064e48:DDI_BUF_TRANS_A_S9T1 [5.111024] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e4c:DDI_BUF_TRANS_A_S9T2 [5.119259] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e60:DDI_BUF_TRANS_B_S0T1 [5.127496] HW.GFX.GMA.Registers.Write: 0x000000a0 -> 0x00064e64:DDI_BUF_TRANS_B_S0T2 [5.135727] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e68:DDI_BUF_TRANS_B_S1T1 [5.143966] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064e6c:DDI_BUF_TRANS_B_S1T2 [5.152198] HW.GFX.GMA.Registers.Write: 0x00007011 -> 0x00064e70:DDI_BUF_TRANS_B_S2T1 [5.160423] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e74:DDI_BUF_TRANS_B_S2T2 [5.168661] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064e78:DDI_BUF_TRANS_B_S3T1 [5.177982] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e7c:DDI_BUF_TRANS_B_S3T2 [5.186215] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e80:DDI_BUF_TRANS_B_S4T1 [5.194441] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064e84:DDI_BUF_TRANS_B_S4T2 [5.202669] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e88:DDI_BUF_TRANS_B_S5T1 [5.210901] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e8c:DDI_BUF_TRANS_B_S5T2 [5.219138] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e90:DDI_BUF_TRANS_B_S6T1 [5.227369] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e94:DDI_BUF_TRANS_B_S6T2 [5.235604] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e98:DDI_BUF_TRANS_B_S7T1 [5.243838] HW.GFX.GMA.Registers.Write: 0x00000097 -> 0x00064e9c:DDI_BUF_TRANS_B_S7T2 [5.252074] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064ea0:DDI_BUF_TRANS_B_S8T1 [5.260310] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064ea4:DDI_BUF_TRANS_B_S8T2 [5.268543] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064ea8:DDI_BUF_TRANS_B_S9T1 [5.276778] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064eac:DDI_BUF_TRANS_B_S9T2 [5.285011] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064ec0:DDI_BUF_TRANS_C_S0T1 [5.293246] HW.GFX.GMA.Registers.Write: 0x000000a0 -> 0x00064ec4:DDI_BUF_TRANS_C_S0T2 [5.301482] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064ec8:DDI_BUF_TRANS_C_S1T1 [5.309716] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064ecc:DDI_BUF_TRANS_C_S1T2 [5.317949] HW.GFX.GMA.Registers.Write: 0x00007011 -> 0x00064ed0:DDI_BUF_TRANS_C_S2T1 [5.326174] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064ed4:DDI_BUF_TRANS_C_S2T2 [5.334412] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064ed8:DDI_BUF_TRANS_C_S3T1 [5.342645] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064edc:DDI_BUF_TRANS_C_S3T2 [5.350879] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064ee0:DDI_BUF_TRANS_C_S4T1 [5.359105] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064ee4:DDI_BUF_TRANS_C_S4T2 [5.367339] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064ee8:DDI_BUF_TRANS_C_S5T1 [5.375573] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064eec:DDI_BUF_TRANS_C_S5T2 [5.383811] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064ef0:DDI_BUF_TRANS_C_S6T1 [5.392044] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064ef4:DDI_BUF_TRANS_C_S6T2 [5.400281] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064ef8:DDI_BUF_TRANS_C_S7T1 [5.408516] HW.GFX.GMA.Registers.Write: 0x00000097 -> 0x00064efc:DDI_BUF_TRANS_C_S7T2 [5.416749] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064f00:DDI_BUF_TRANS_C_S8T1 [5.424983] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f04:DDI_BUF_TRANS_C_S8T2 [5.433218] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064f08:DDI_BUF_TRANS_C_S9T1 [5.441454] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064f0c:DDI_BUF_TRANS_C_S9T2 [5.449689] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064f20:DDI_BUF_TRANS_D_S0T1 [5.457920] HW.GFX.GMA.Registers.Write: 0x000000a0 -> 0x00064f24:DDI_BUF_TRANS_D_S0T2 [5.466158] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064f28:DDI_BUF_TRANS_D_S1T1 [5.474389] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064f2c:DDI_BUF_TRANS_D_S1T2 [5.482626] HW.GFX.GMA.Registers.Write: 0x00007011 -> 0x00064f30:DDI_BUF_TRANS_D_S2T1 [5.490857] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064f34:DDI_BUF_TRANS_D_S2T2 [5.499094] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064f38:DDI_BUF_TRANS_D_S3T1 [5.507318] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f3c:DDI_BUF_TRANS_D_S3T2 [5.515555] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064f40:DDI_BUF_TRANS_D_S4T1 [5.523778] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064f44:DDI_BUF_TRANS_D_S4T2 [5.532013] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064f48:DDI_BUF_TRANS_D_S5T1 [5.540248] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064f4c:DDI_BUF_TRANS_D_S5T2 [5.548484] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064f50:DDI_BUF_TRANS_D_S6T1 [5.556718] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f54:DDI_BUF_TRANS_D_S6T2 [5.564956] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064f58:DDI_BUF_TRANS_D_S7T1 [5.573181] HW.GFX.GMA.Registers.Write: 0x00000097 -> 0x00064f5c:DDI_BUF_TRANS_D_S7T2 [5.581412] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064f60:DDI_BUF_TRANS_D_S8T1 [5.589648] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f64:DDI_BUF_TRANS_D_S8T2 [5.597883] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064f68:DDI_BUF_TRANS_D_S9T1 [5.606117] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064f6c:DDI_BUF_TRANS_D_S9T2 [5.614351] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064f80:DDI_BUF_TRANS_E_S0T1 [5.622588] HW.GFX.GMA.Registers.Write: 0x000000a0 -> 0x00064f84:DDI_BUF_TRANS_E_S0T2 [5.630821] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064f88:DDI_BUF_TRANS_E_S1T1 [5.639056] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064f8c:DDI_BUF_TRANS_E_S1T2 [5.647292] HW.GFX.GMA.Registers.Write: 0x00007011 -> 0x00064f90:DDI_BUF_TRANS_E_S2T1 [5.655526] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064f94:DDI_BUF_TRANS_E_S2T2 [5.663762] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064f98:DDI_BUF_TRANS_E_S3T1 [5.671994] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f9c:DDI_BUF_TRANS_E_S3T2 [5.680230] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064fa0:DDI_BUF_TRANS_E_S4T1 [5.688462] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064fa4:DDI_BUF_TRANS_E_S4T2 [5.696688] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064fa8:DDI_BUF_TRANS_E_S5T1 [5.704924] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064fac:DDI_BUF_TRANS_E_S5T2 [5.713158] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064fb0:DDI_BUF_TRANS_E_S6T1 [5.721395] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064fb4:DDI_BUF_TRANS_E_S6T2 [5.729618] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064fb8:DDI_BUF_TRANS_E_S7T1 [5.737853] HW.GFX.GMA.Registers.Write: 0x00000097 -> 0x00064fbc:DDI_BUF_TRANS_E_S7T2 [5.746087] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064fc0:DDI_BUF_TRANS_E_S8T1 [5.754316] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064fc4:DDI_BUF_TRANS_E_S8T2 [5.762551] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064fc8:DDI_BUF_TRANS_E_S9T1 [5.770782] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064fcc:DDI_BUF_TRANS_E_S9T2 [5.779018] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DISPIO_CR_TX_BMU_CR0 [5.786102] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006c00c:DISPIO_CR_TX_BMU_CR0 [5.794339] HW.GFX.GMA.Registers.Write: 0x00124900 -> 0x0006c00c:DISPIO_CR_TX_BMU_CR0 [5.802679] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S CPU_VGACNTRL [5.809297] HW.GFX.GMA.Registers.Read: 0x80002900 <- 0x00041000:CPU_VGACNTRL [5.816766] HW.GFX.GMA.Registers.Write: 0x80002900 -> 0x00041000:CPU_VGACNTRL [5.824232] HW.GFX.GMA.Registers.Set_Mask: 0x000f8000 .S DPLL_CTRL2 [5.830743] HW.GFX.GMA.Registers.Read: 0x00a00000 <- 0x0006c05c:DPLL_CTRL2 [5.838021] HW.GFX.GMA.Registers.Write: 0x00af8000 -> 0x0006c05c:DPLL_CTRL2 [5.845297] HW.GFX.GMA.Registers.Set_Mask: 0x00000010 .S NDE_RSTWRN_OPT [5.852191] HW.GFX.GMA.Registers.Read: 0x00000030 <- 0x00046408:NDE_RSTWRN_OPT [5.859850] HW.GFX.GMA.Registers.Write: 0x00000030 -> 0x00046408:NDE_RSTWRN_OPT [5.867511] HW.GFX.GMA.Registers.Wait: 0x08000000 <- 0x08000000 & 0x00042000:FUSE_STATUS [5.876120] HW.GFX.GMA.Power_And_Clocks.PD_On [5.880523] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS [5.888469] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x00045404:PWR_WELL_CTL_DRIVER [5.896608] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [5.904559] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [5.912599] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [5.920165] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [5.927729] HW.GFX.GMA.Registers.Set_Mask: 0x20000000 .S PWR_WELL_CTL_DRIVER [5.935099] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x00045404:PWR_WELL_CTL_DRIVER [5.943239] HW.GFX.GMA.Registers.Write: 0x70000001 -> 0x00045404:PWR_WELL_CTL_DRIVER [5.951377] HW.GFX.GMA.Registers.Wait: 0x10000000 <- 0x10000000 & 0x00045404:PWR_WELL_CTL_DRIVER [5.960753] HW.GFX.GMA.Registers.Wait: 0x04000000 <- 0x04000000 & 0x00042000:FUSE_STATUS [5.969373] HW.GFX.GMA.Power_And_Clocks.PD_On [5.973775] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS [5.981721] HW.GFX.GMA.Registers.Read: 0x70000001 <- 0x00045404:PWR_WELL_CTL_DRIVER [5.989859] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [5.997807] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [6.005848] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [6.013413] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [6.020978] HW.GFX.GMA.Registers.Set_Mask: 0x00000002 .S PWR_WELL_CTL_DRIVER [6.028350] HW.GFX.GMA.Registers.Read: 0x70000001 <- 0x00045404:PWR_WELL_CTL_DRIVER [6.036490] HW.GFX.GMA.Registers.Write: 0x70000003 -> 0x00045404:PWR_WELL_CTL_DRIVER [6.044627] HW.GFX.GMA.Registers.Wait: 0x00000001 <- 0x00000001 & 0x00045404:PWR_WELL_CTL_DRIVER [6.054015] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S LCPLL1_CTL [6.060523] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x00046010:LCPLL1_CTL [6.067798] HW.GFX.GMA.Registers.Write: 0xc0000000 -> 0x00046010:LCPLL1_CTL [6.075075] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00046010:LCPLL1_CTL [6.083602] HW.GFX.GMA.Registers.Read: 0x0c000544 <- 0x00046000:CDCLK_CTL [6.090778] HW.GFX.GMA.Registers.Read: 0x20400042 <- 0x00051000:DFSM [6.097485] HW.GFX.GMA.PCode.Mailbox_Write_Read [6.102074] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX [6.110600] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA [6.118355] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 [6.126300] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX [6.133576] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX [6.142094] HW.GFX.GMA.Registers.Read: 0x00000001 <- 0x00138128:GT_MAILBOX_DATA [6.149848] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0013812c:GT_MAILBOX_DATA_1 [6.157795] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00138128:GT_MAILBOX_DATA [6.165547] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 [6.173496] HW.GFX.GMA.Registers.Write: 0x080002a1 -> 0x00046000:CDCLK_CTL [6.180680] HW.GFX.GMA.PCode.Mailbox_Write_Read [6.185272] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00138128:GT_MAILBOX_DATA [6.193031] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 [6.200976] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX [6.208250] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S DBUF_CTL [6.214570] HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x00045008:DBUF_CTL [6.221655] HW.GFX.GMA.Registers.Write: 0x8000000a -> 0x00045008:DBUF_CTL [6.228744] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045008:DBUF_CTL [6.237067] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP [6.242618] HW.GFX.GMA.Registers.Read: 0x00000107 <- 0x000c2014:SFUSE_STRAP [6.249991] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_RAWCLK_FREQ [6.256629] HW.GFX.GMA.Registers.Read: 0x10120000 <- 0x000c6204:PCH_RAWCLK_FREQ [6.264351] HW.GFX.GMA.Registers.Write: 0x00180000 -> 0x000c6204:PCH_RAWCLK_FREQ [6.272140] HW.GFX.GMA.Panel.On [6.275173] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL [6.281042] HW.GFX.GMA.Registers.Read: 0x00000072 <- 0x000c7204:PCH_PP_CONTROL [6.289821] HW.GFX.GMA.Registers.Set_Mask: 0x00000001 .S PCH_PP_CONTROL [6.296715] HW.GFX.GMA.Registers.Read: 0x00000072 <- 0x000c7204:PCH_PP_CONTROL [6.304376] HW.GFX.GMA.Registers.Write: 0x00000073 -> 0x000c7204:PCH_PP_CONTROL [6.312068] HW.GFX.GMA.Panel.Wait_On [6.522039] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS [6.530777] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PCH_PP_CONTROL [6.537863] HW.GFX.GMA.Registers.Read: 0x00000073 <- 0x000c7204:PCH_PP_CONTROL [6.545509] HW.GFX.GMA.Registers.Write: 0x00000073 -> 0x000c7204:PCH_PP_CONTROL [6.553182] HW.GFX.GMA.Display_Probing.Read_EDID [6.557862] HW.GFX.GMA.Power_And_Clocks.PD_On [6.562266] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS [6.570213] HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [6.578355] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [6.586293] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [6.594336] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [6.601890] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [6.609454] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER [6.618841] HW.GFX.GMA.Registers.Set_Mask: 0x00000008 .S PWR_WELL_CTL_DRIVER [6.626213] HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [6.634352] HW.GFX.GMA.Registers.Write: 0x7000000b -> 0x00045404:PWR_WELL_CTL_DRIVER [6.642489] HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER [6.651877] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [6.657619] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064010:DDI_AUX_CTL_A [6.665173] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1 [6.673025] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [6.679438] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064010:DDI_AUX_CTL_A [6.687001] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A [6.694567] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [6.703379] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [6.710942] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1 [6.718791] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [6.724535] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [6.732102] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1 [6.739951] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064018:DDI_AUX_DATA_A_2 [6.747803] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [6.754217] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [6.761785] HW.GFX.GMA.Registers.Write: 0xd650023f -> 0x00064010:DDI_AUX_CTL_A [6.769348] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [6.778148] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [6.785711] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1 [6.793563] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [6.799308] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [6.806874] HW.GFX.GMA.Registers.Write: 0x00005000 -> 0x00064014:DDI_AUX_DATA_A_1 [6.814723] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [6.821140] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [6.828700] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A [6.836267] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [6.845077] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [6.852638] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1 [6.860492] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [6.866234] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [6.873800] HW.GFX.GMA.Registers.Write: 0x50005000 -> 0x00064014:DDI_AUX_DATA_A_1 [6.881649] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [6.888068] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [6.895629] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A [6.903192] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [6.912007] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [6.919567] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1 [6.927417] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [6.933162] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [6.940726] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1 [6.948580] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [6.954992] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [6.962557] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A [6.970123] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [6.978935] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [6.986493] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x00064014:DDI_AUX_DATA_A_1 [6.994853] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [7.000520] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [7.008084] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1 [7.015937] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [7.022351] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [7.029916] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A [7.037481] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [7.046293] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [7.053853] HW.GFX.GMA.Registers.Read: 0x0000ffff <- 0x00064014:DDI_AUX_DATA_A_1 [7.061708] HW.GFX.GMA.Registers.Read: 0xffffffff <- 0x00064018:DDI_AUX_DATA_A_2 [7.069557] HW.GFX.GMA.Registers.Read: 0x0006afed <- 0x0006401c:DDI_AUX_DATA_A_3 [7.077407] HW.GFX.GMA.Registers.Read: 0x35000000 <- 0x00064020:DDI_AUX_DATA_A_4 [7.085258] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064024:DDI_AUX_DATA_A_5 [7.093112] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [7.098855] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [7.106422] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1 [7.114271] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [7.120688] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [7.128250] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A [7.135818] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [7.144628] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [7.152189] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x00064014:DDI_AUX_DATA_A_1 [7.160544] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [7.166205] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [7.173771] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1 [7.181621] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [7.188025] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [7.195592] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A [7.203154] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [7.211966] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [7.219526] HW.GFX.GMA.Registers.Read: 0x00001701 <- 0x00064014:DDI_AUX_DATA_A_1 [7.227379] HW.GFX.GMA.Registers.Read: 0x04952213 <- 0x00064018:DDI_AUX_DATA_A_2 [7.235231] HW.GFX.GMA.Registers.Read: 0x7802d115 <- 0x0006401c:DDI_AUX_DATA_A_3 [7.243081] HW.GFX.GMA.Registers.Read: 0x9e59539b <- 0x00064020:DDI_AUX_DATA_A_4 [7.250934] HW.GFX.GMA.Registers.Read: 0x27000000 <- 0x00064024:DDI_AUX_DATA_A_5 [7.258787] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [7.264530] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [7.272093] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1 [7.279946] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [7.286360] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [7.293925] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A [7.301489] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [7.310303] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [7.317864] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x00064014:DDI_AUX_DATA_A_1 [7.326219] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [7.331882] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [7.339445] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1 [7.347297] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [7.353709] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [7.362380] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A [7.369945] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [7.378756] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [7.386309] HW.GFX.GMA.Registers.Read: 0x001e5054 <- 0x00064014:DDI_AUX_DATA_A_1 [7.394152] HW.GFX.GMA.Registers.Read: 0x00000001 <- 0x00064018:DDI_AUX_DATA_A_2 [7.401994] HW.GFX.GMA.Registers.Read: 0x01010101 <- 0x0006401c:DDI_AUX_DATA_A_3 [7.409849] HW.GFX.GMA.Registers.Read: 0x01010101 <- 0x00064020:DDI_AUX_DATA_A_4 [7.417700] HW.GFX.GMA.Registers.Read: 0x01000000 <- 0x00064024:DDI_AUX_DATA_A_5 [7.425549] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [7.431296] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [7.438860] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1 [7.446713] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [7.453126] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [7.460691] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A [7.468253] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [7.477065] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [7.484625] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x00064014:DDI_AUX_DATA_A_1 [7.492983] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [7.498643] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [7.506209] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1 [7.514051] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [7.520467] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [7.528032] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A [7.535595] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [7.544407] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [7.551966] HW.GFX.GMA.Registers.Read: 0x00010101 <- 0x00064014:DDI_AUX_DATA_A_1 [7.559810] HW.GFX.GMA.Registers.Read: 0x01010178 <- 0x00064018:DDI_AUX_DATA_A_2 [7.567661] HW.GFX.GMA.Registers.Read: 0x3780b470 <- 0x0006401c:DDI_AUX_DATA_A_3 [7.575512] HW.GFX.GMA.Registers.Read: 0x382e406c <- 0x00064020:DDI_AUX_DATA_A_4 [7.583365] HW.GFX.GMA.Registers.Read: 0x30000000 <- 0x00064024:DDI_AUX_DATA_A_5 [7.591216] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [7.596962] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [7.604527] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1 [7.612381] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [7.618788] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [7.626352] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A [7.633915] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [7.642727] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [7.650289] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x00064014:DDI_AUX_DATA_A_1 [7.658644] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [7.664310] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [7.671874] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1 [7.679728] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [7.686144] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [7.693708] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A [7.701272] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [7.710082] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [7.717646] HW.GFX.GMA.Registers.Read: 0x00aa0058 <- 0x00064014:DDI_AUX_DATA_A_1 [7.725494] HW.GFX.GMA.Registers.Read: 0xc1100000 <- 0x00064018:DDI_AUX_DATA_A_2 [7.733347] HW.GFX.GMA.Registers.Read: 0x18fb2480 <- 0x0006401c:DDI_AUX_DATA_A_3 [7.741197] HW.GFX.GMA.Registers.Read: 0xb470382e <- 0x00064020:DDI_AUX_DATA_A_4 [7.749041] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00064024:DDI_AUX_DATA_A_5 [7.756896] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [7.762638] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [7.770204] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1 [7.778056] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [7.784467] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [7.792034] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A [7.799596] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [7.808410] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [7.815973] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x00064014:DDI_AUX_DATA_A_1 [7.824325] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [7.829988] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [7.837551] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1 [7.845406] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [7.851817] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [7.859383] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A [7.866949] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [7.875760] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [7.883323] HW.GFX.GMA.Registers.Read: 0x006c30aa <- 0x00064014:DDI_AUX_DATA_A_1 [7.891171] HW.GFX.GMA.Registers.Read: 0x0058c110 <- 0x00064018:DDI_AUX_DATA_A_2 [7.899023] HW.GFX.GMA.Registers.Read: 0x00001800 <- 0x0006401c:DDI_AUX_DATA_A_3 [7.906869] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064020:DDI_AUX_DATA_A_4 [7.914710] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064024:DDI_AUX_DATA_A_5 [7.922563] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [7.928306] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [7.935861] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1 [7.943713] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [7.950128] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [7.957694] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A [7.965256] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [7.974071] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [7.981623] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x00064014:DDI_AUX_DATA_A_1 [7.989971] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [7.995637] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [8.003202] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1 [8.011052] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [8.017470] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [8.025033] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A [8.032599] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [8.041390] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [8.048951] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1 [8.056806] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064018:DDI_AUX_DATA_A_2 [8.064648] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006401c:DDI_AUX_DATA_A_3 [8.072500] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064020:DDI_AUX_DATA_A_4 [8.080353] HW.GFX.GMA.Registers.Read: 0x02000000 <- 0x00064024:DDI_AUX_DATA_A_5 [8.088196] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [8.093941] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [8.101503] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1 [8.109357] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [8.115772] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [8.123326] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A [8.130892] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [8.139700] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [8.147265] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x00064014:DDI_AUX_DATA_A_1 [8.155620] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [8.161288] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [8.168853] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1 [8.176705] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [8.183121] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [8.190684] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A [8.198247] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [8.207058] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [8.214620] HW.GFX.GMA.Registers.Read: 0x00000c33 <- 0x00064014:DDI_AUX_DATA_A_1 [8.222471] HW.GFX.GMA.Registers.Read: 0xff0e3c96 <- 0x00064018:DDI_AUX_DATA_A_2 [8.230322] HW.GFX.GMA.Registers.Read: 0x1b0d1c96 <- 0x0006401c:DDI_AUX_DATA_A_3 [8.238174] HW.GFX.GMA.Registers.Read: 0x20202000 <- 0x00064020:DDI_AUX_DATA_A_4 [8.246029] HW.GFX.GMA.Registers.Read: 0x41000000 <- 0x00064024:DDI_AUX_DATA_A_5 [8.253880] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [8.259624] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [8.267180] HW.GFX.GMA.Registers.Write: 0x10005000 -> 0x00064014:DDI_AUX_DATA_A_1 [8.275030] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [8.281449] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A [8.289011] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A [8.296567] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [8.305377] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [8.312939] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1 [8.320790] EDID+0x0000: 00 ff ff ff ff ff ff 00 06 af ed 35 00 00 00 00 [8.328067] EDID+0x0010: 00 17 01 04 95 22 13 78 02 d1 15 9e 59 53 9b 27 [8.335345] EDID+0x0020: 1e 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 [8.342621] EDID+0x0030: 01 01 01 01 01 01 78 37 80 b4 70 38 2e 40 6c 30 [8.349901] EDID+0x0040: aa 00 58 c1 10 00 00 18 fb 24 80 b4 70 38 2e 40 [8.357175] EDID+0x0050: 6c 30 aa 00 58 c1 10 00 00 18 00 00 00 00 00 00 [8.364456] EDID+0x0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 [8.371733] EDID+0x0070: 00 0c 33 ff 0e 3c 96 1b 0d 1c 96 20 20 20 00 41 [8.379012] HW.GFX.GMA.Power_And_Clocks.PD_Off [8.383508] HW.GFX.GMA.Registers.Read: 0xf0000007 <- 0x00045400:PWR_WELL_CTL_BIOS [8.391456] HW.GFX.GMA.Registers.Read: 0x7000000f <- 0x00045404:PWR_WELL_CTL_DRIVER [8.399584] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [8.407533] HW.GFX.GMA.Registers.Read: 0x50000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG [8.415575] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [8.423139] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [8.430705] HW.GFX.GMA.Power_And_Clocks.PD_Off [8.435204] HW.GFX.GMA.Registers.Read: 0xf0000007 <- 0x00045400:PWR_WELL_CTL_BIOS [8.443155] HW.GFX.GMA.Registers.Read: 0x7000000f <- 0x00045404:PWR_WELL_CTL_DRIVER [8.451294] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [8.459238] HW.GFX.GMA.Registers.Read: 0x50000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG [8.468441] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [8.476004] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [8.483567] HW.GFX.GMA.Power_And_Clocks.PD_Off [8.488070] HW.GFX.GMA.Registers.Read: 0xf0000007 <- 0x00045400:PWR_WELL_CTL_BIOS [8.496006] HW.GFX.GMA.Registers.Read: 0x7000000f <- 0x00045404:PWR_WELL_CTL_DRIVER [8.504148] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [8.512093] HW.GFX.GMA.Registers.Read: 0x50000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG [8.520137] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [8.527698] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [8.535263] HW.GFX.GMA.Power_And_Clocks.PD_Off [8.539765] HW.GFX.GMA.Registers.Read: 0xf0000007 <- 0x00045400:PWR_WELL_CTL_BIOS [8.547706] HW.GFX.GMA.Registers.Read: 0x7000000f <- 0x00045404:PWR_WELL_CTL_DRIVER [8.555845] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [8.563790] HW.GFX.GMA.Registers.Read: 0x50000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG [8.571836] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [8.579399] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [8.586963] HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER [8.596348] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PWR_WELL_CTL_DRIVER [8.603908] HW.GFX.GMA.Registers.Read: 0x7000000f <- 0x00045404:PWR_WELL_CTL_DRIVER [8.612050] HW.GFX.GMA.Registers.Write: 0x70000007 -> 0x00045404:PWR_WELL_CTL_DRIVER [8.620186] HW.GFX.GMA.Power_And_Clocks.PD_Off [8.624686] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS [8.632626] HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [8.640765] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [8.648704] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [8.656745] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [8.664311] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [8.671874] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404:PWR_WELL_CTL_DRIVER [8.681253] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PWR_WELL_CTL_BIOS [8.688620] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS [8.696562] HW.GFX.GMA.Registers.Write: 0x70000003 -> 0x00045400:PWR_WELL_CTL_BIOS [8.704701] CONFIG => [8.706805] (Primary => [8.709487] (Port => eDP , [8.712932] Framebuffer => [8.716092] (Width => 1920, [8.719923] Height => 1080, [8.723754] Start_X => 0, [8.727296] Start_Y => 0, [8.730837] Stride => 1920, [8.734661] V_Stride => 1080, [8.738489] Tiling => Linear , [8.742607] Rotation => No_Rotation, [8.747105] Offset => 0x00000000, [8.751221] BPC => 8), [8.754573] Mode => [8.757063] (Dotclock => 142000000, [8.762234] H_Visible => 1920, [8.766925] H_Sync_Begin => 2028, [8.771617] H_Sync_End => 2076, [8.776311] H_Total => 2100, [8.781003] V_Visible => 1080, [8.785694] V_Sync_Begin => 1090, [8.790383] V_Sync_End => 1100, [8.795074] V_Total => 1126, [8.799767] H_Sync_Active_High => False, [8.804555] V_Sync_Active_High => False, [8.809341] BPC => 6)), [8.813938] Secondary => [8.816618] (Port => Disabled, [8.820065] Framebuffer => [8.823217] (Width => 1, [8.826756] Height => 1, [8.830292] Start_X => 0, [8.833833] Start_Y => 0, [8.837377] Stride => 1, [8.840920] V_Stride => 1, [8.844464] Tiling => Linear , [8.848570] Rotation => No_Rotation, [8.853071] Offset => 0x00000000, [8.857190] BPC => 8), [8.860537] Mode => [8.863028] (Dotclock => 1000000, [8.868005] H_Visible => 1, [8.872412] H_Sync_Begin => 1, [8.876804] H_Sync_End => 1, [8.881213] H_Total => 1, [8.885616] V_Visible => 1, [8.890020] V_Sync_Begin => 1, [8.894415] V_Sync_End => 1, [8.898820] V_Total => 1, [8.903222] H_Sync_Active_High => False, [8.908010] V_Sync_Active_High => False, [8.912801] BPC => 5)), [8.917392] Tertiary => [8.920076] (Port => Disabled, [8.923520] Framebuffer => [8.926681] (Width => 1, [8.930225] Height => 1, [8.933766] Start_X => 0, [8.937309] Start_Y => 0, [8.940851] Stride => 1, [8.944396] V_Stride => 1, [8.947938] Tiling => Linear , [8.952052] Rotation => No_Rotation, [8.956555] Offset => 0x00000000, [8.960673] BPC => 8), [8.964022] Mode => [8.966508] (Dotclock => 1000000, [8.971490] H_Visible => 1, [8.975893] H_Sync_Begin => 1, [8.980297] H_Sync_End => 1, [8.984701] H_Total => 1, [8.989107] V_Visible => 1, [8.993509] V_Sync_Begin => 1, [8.997904] V_Sync_End => 1, [9.002309] V_Total => 1, [9.006715] H_Sync_Active_High => False, [9.011500] V_Sync_Active_High => False, [9.016288] BPC => 5))); [9.608651] HW.GFX.GMA.Power_And_Clocks.PD_On [9.612967] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS [9.620914] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [9.629051] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR [9.636999] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [9.645042] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [9.652608] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [9.660174] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER [9.669558] HW.GFX.GMA.Registers.Set_Mask: 0x00000008 .S PWR_WELL_CTL_DRIVER [9.676929] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [9.685064] HW.GFX.GMA.Registers.Write: 0x3000000b -> 0x00045404:PWR_WELL_CTL_DRIVER [9.693197] HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER [9.702770] Trying to enable port eDP [9.706886] HW.GFX.GMA.Connector_Info.Preferred_Link_Setting [9.712719] HW.GFX.GMA.Panel.On [9.715785] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL [9.721634] HW.GFX.GMA.Registers.Read: 0x00000073 <- 0x000c7204:PCH_PP_CONTROL [9.729277] HW.GFX.GMA.Registers.Set_Mask: 0x00000001 .S PCH_PP_CONTROL [9.736169] HW.GFX.GMA.Registers.Read: 0x00000073 <- 0x000c7204:PCH_PP_CONTROL [9.743830] HW.GFX.GMA.Registers.Write: 0x00000073 -> 0x000c7204:PCH_PP_CONTROL [9.751503] HW.GFX.GMA.Panel.Wait_On [9.755032] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS [9.763855] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PCH_PP_CONTROL [9.770937] HW.GFX.GMA.Registers.Read: 0x00000073 <- 0x000c7204:PCH_PP_CONTROL [9.778587] HW.GFX.GMA.Registers.Write: 0x00000073 -> 0x000c7204:PCH_PP_CONTROL [9.786261] HW.GFX.GMA.DP_Info.Read_Caps [9.790173] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [9.795917] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [9.803483] HW.GFX.GMA.Registers.Write: 0x9000000e -> 0x00064014:DDI_AUX_DATA_A_1 [9.811332] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [9.817740] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [9.825303] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A [9.832867] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [9.841679] HW.GFX.GMA.Registers.Read: 0x4500023f <- 0x00064010:DDI_AUX_CTL_A [9.849239] HW.GFX.GMA.Registers.Read: 0x00120a82 <- 0x00064014:DDI_AUX_DATA_A_1 [9.857094] HW.GFX.GMA.Registers.Read: 0x41000001 <- 0x00064018:DDI_AUX_DATA_A_2 [9.864944] HW.GFX.GMA.Registers.Read: 0x40020000 <- 0x0006401c:DDI_AUX_DATA_A_3 [9.872795] HW.GFX.GMA.Registers.Read: 0x00000b00 <- 0x00064020:DDI_AUX_DATA_A_4 [9.880838] DPCD: [9.882564] Rev : 0x12 [9.886107] Max_Link_Rate : 0x0a [9.889647] Max_Lane_Count : 0x02 [9.893189] TPS3_Supported : 0x00 [9.896735] Enhanced_Framing: 0x80 [9.900276] No_Aux_Handshake: 0x40 [9.903819] Aux_RD_Interval : 0x00 [9.907554] HW.GFX.GMA.DP_Info.Read_eDP_Rates [9.911956] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [9.917701] HW.GFX.GMA.Registers.Read: 0x4500023f <- 0x00064010:DDI_AUX_CTL_A [9.925268] HW.GFX.GMA.Registers.Write: 0x90070002 -> 0x00064014:DDI_AUX_DATA_A_1 [9.933119] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [9.939533] HW.GFX.GMA.Registers.Read: 0x4500023f <- 0x00064010:DDI_AUX_CTL_A [9.947099] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A [9.954660] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [9.963473] HW.GFX.GMA.Registers.Read: 0x4440023f <- 0x00064010:DDI_AUX_CTL_A [9.971035] HW.GFX.GMA.Registers.Read: 0x0001fbff <- 0x00064014:DDI_AUX_DATA_A_1 [9.978887] Trying DP settings: Symbol Rate = 270000000; Lane Count = 2 [9.985973] HW.GFX.GMA.PLLs.Alloc [9.989229] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006c058:DPLL_CTRL1 [9.996504] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DPLL_CTRL1 [10.002630] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006c058:DPLL_CTRL1 [10.010006] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x0006c058:DPLL_CTRL1 [10.017369] HW.GFX.GMA.Registers.Read: 0x000000c0 <- 0x0006c058:DPLL_CTRL1 [10.024742] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x00046014:LCPLL2_CTL [10.032116] HW.GFX.GMA.Registers.Wait: 0x00000100 <- 0x00000100 & 0x0006c060:DPLL_STATUS [10.040844] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL [10.047241] HW.GFX.GMA.Registers.Read: 0x12101010 <- 0x000c4030:SHOTPLUG_CTL [10.054806] HW.GFX.GMA.Registers.Write: 0x13101010 -> 0x000c4030:SHOTPLUG_CTL [10.062386] HW.GFX.GMA.Connectors.Pre_On [10.066395] HW.GFX.GMA.Connectors.DDI.Pre_On [10.070800] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DPLL_CTRL2 [10.077023] HW.GFX.GMA.Registers.Read: 0x00af8000 <- 0x0006c05c:DPLL_CTRL2 [10.084394] HW.GFX.GMA.Registers.Write: 0x00af0003 -> 0x0006c05c:DPLL_CTRL2 [10.091767] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Train_DP [10.097894] HW.GFX.GMA.Registers.Write: 0x80040080 -> 0x00064040:DP_TP_CTL_A [10.105353] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A [10.111194] HW.GFX.GMA.Registers.Read: 0x00000091 <- 0x00064000:DDI_BUF_CTL_A [10.118857] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A [10.125365] HW.GFX.GMA.Registers.Read: 0x00000091 <- 0x00064000:DDI_BUF_CTL_A [10.133026] HW.GFX.GMA.Registers.Write: 0x80000093 -> 0x00064000:DDI_BUF_CTL_A [10.140686] HW.GFX.GMA.Registers.Read: 0x80000093 <- 0x00064000:DDI_BUF_CTL_A [10.148949] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Init [10.155090] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [10.160930] HW.GFX.GMA.Registers.Read: 0x4440023f <- 0x00064010:DDI_AUX_CTL_A [10.168592] HW.GFX.GMA.Registers.Write: 0x80010001 -> 0x00064014:DDI_AUX_DATA_A_1 [10.176537] HW.GFX.GMA.Registers.Write: 0x0a820000 -> 0x00064018:DDI_AUX_DATA_A_2 [10.184488] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [10.190988] HW.GFX.GMA.Registers.Read: 0x4440023f <- 0x00064010:DDI_AUX_CTL_A [10.198648] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A [10.206311] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [10.215213] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [10.222872] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1 [10.230820] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [10.236661] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [10.244321] HW.GFX.GMA.Registers.Write: 0x80010701 -> 0x00064014:DDI_AUX_DATA_A_1 [10.252268] HW.GFX.GMA.Registers.Write: 0x00010000 -> 0x00064018:DDI_AUX_DATA_A_2 [10.260217] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [10.266726] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [10.274385] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A [10.282046] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [10.290955] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [10.298613] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1 [10.306551] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Training_Pattern [10.314299] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [10.320136] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [10.327798] HW.GFX.GMA.Registers.Write: 0x80010202 -> 0x00064014:DDI_AUX_DATA_A_1 [10.335747] HW.GFX.GMA.Registers.Write: 0x21000000 -> 0x00064018:DDI_AUX_DATA_A_2 [10.343691] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [10.350202] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [10.357862] HW.GFX.GMA.Registers.Write: 0xd670023f -> 0x00064010:DDI_AUX_CTL_A [10.365521] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [10.374430] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [10.382086] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1 [10.390137] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training [10.397333] HW.GFX.GMA.DP_Info.Read_Link_Status [10.402023] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [10.407861] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [10.415525] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1 [10.423471] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [10.429982] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [10.437642] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A [10.445302] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [10.454198] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A [10.461857] HW.GFX.GMA.Registers.Read: 0x00110080 <- 0x00064014:DDI_AUX_DATA_A_1 [10.469804] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064018:DDI_AUX_DATA_A_2 [10.477942] Link Status: [10.480433] Lane0: [10.482529] CR_Done : 1 [10.485976] Channel_EQ_Done: 0 [10.489425] Symbol_Locked : 0 [10.492869] Lane1: [10.494977] CR_Done : 1 [10.498423] Channel_EQ_Done: 0 [10.501870] Symbol_Locked : 0 [10.505318] Interlane_Align_Done: 0 [10.509052] Adjust0: [10.511351] Voltage_Swing: 0 [10.514603] Pre_Emph : 0 [10.517857] Adjust1: [10.520155] Voltage_Swing: 0 [10.523411] Pre_Emph : 0 [10.526859] HW.GFX.GMA.Registers.Write: 0x80040180 -> 0x00064040:DP_TP_CTL_A [10.534329] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Training_Pattern [10.542084] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [10.547923] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A [10.555585] HW.GFX.GMA.Registers.Write: 0x80010202 -> 0x00064014:DDI_AUX_DATA_A_1 [10.563530] HW.GFX.GMA.Registers.Write: 0x22000000 -> 0x00064018:DDI_AUX_DATA_A_2 [10.571478] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [10.577988] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A [10.585652] HW.GFX.GMA.Registers.Write: 0xd670023f -> 0x00064010:DDI_AUX_CTL_A [10.593309] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [10.602217] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [10.609876] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1 [10.618226] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training [10.625417] HW.GFX.GMA.DP_Info.Read_Link_Status [10.630110] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [10.635953] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [10.643609] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1 [10.651550] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [10.658060] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [10.665720] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A [10.673381] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [10.683428] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A [10.691079] HW.GFX.GMA.Registers.Read: 0x00110081 <- 0x00064014:DDI_AUX_DATA_A_1 [10.699026] HW.GFX.GMA.Registers.Read: 0x00440000 <- 0x00064018:DDI_AUX_DATA_A_2 [10.707162] Link Status: [10.709652] Lane0: [10.711758] CR_Done : 1 [10.715204] Channel_EQ_Done: 0 [10.718652] Symbol_Locked : 0 [10.722099] Lane1: [10.724205] CR_Done : 1 [10.727652] Channel_EQ_Done: 0 [10.731097] Symbol_Locked : 0 [10.734543] Interlane_Align_Done: 1 [10.738279] Adjust0: [10.740578] Voltage_Swing: 0 [10.743830] Pre_Emph : 1 [10.747086] Adjust1: [10.749385] Voltage_Swing: 0 [10.752639] Pre_Emph : 1 [10.756086] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A [10.761926] HW.GFX.GMA.Registers.Read: 0x80000013 <- 0x00064000:DDI_BUF_CTL_A [10.769585] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A [10.776096] HW.GFX.GMA.Registers.Read: 0x80000013 <- 0x00064000:DDI_BUF_CTL_A [10.783758] HW.GFX.GMA.Registers.Write: 0x81000013 -> 0x00064000:DDI_BUF_CTL_A [10.791408] HW.GFX.GMA.Registers.Read: 0x81000013 <- 0x00064000:DDI_BUF_CTL_A [10.799067] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels [10.806536] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [10.812379] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A [10.820029] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1 [10.827978] HW.GFX.GMA.Registers.Write: 0x08080000 -> 0x00064018:DDI_AUX_DATA_A_2 [10.835926] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [10.842435] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A [10.850094] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A [10.857757] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [10.866660] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [10.874318] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1 [10.882672] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training [10.889869] HW.GFX.GMA.DP_Info.Read_Link_Status [10.894563] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [10.900401] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [10.908064] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1 [10.916012] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [10.922523] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [10.930183] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A [10.937844] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [10.946751] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A [10.954406] HW.GFX.GMA.Registers.Read: 0x00770081 <- 0x00064014:DDI_AUX_DATA_A_1 [10.962355] HW.GFX.GMA.Registers.Read: 0x00440000 <- 0x00064018:DDI_AUX_DATA_A_2 [10.970491] Link Status: [10.972981] Lane0: [10.975087] CR_Done : 1 [10.978537] Channel_EQ_Done: 1 [10.981984] Symbol_Locked : 1 [10.985428] Lane1: [10.987534] CR_Done : 1 [10.990984] Channel_EQ_Done: 1 [10.994429] Symbol_Locked : 1 [10.997877] Interlane_Align_Done: 1 [11.001610] Adjust0: [11.003909] Voltage_Swing: 0 [11.007163] Pre_Emph : 1 [11.010416] Adjust1: [11.012713] Voltage_Swing: 0 [11.015972] Pre_Emph : 1 [11.019418] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Training_Pattern [11.027174] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A [11.033015] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A [11.040674] HW.GFX.GMA.Registers.Write: 0x80010200 -> 0x00064014:DDI_AUX_DATA_A_1 [11.048623] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064018:DDI_AUX_DATA_A_2 [11.056568] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A [11.063080] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A [11.070740] HW.GFX.GMA.Registers.Write: 0xd650023f -> 0x00064010:DDI_AUX_CTL_A [11.078401] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A [11.087309] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A [11.094956] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1 [11.102904] HW.GFX.GMA.Registers.Write: 0x80040200 -> 0x00064040:DP_TP_CTL_A [11.110375] HW.GFX.GMA.Registers.Write: 0x80040300 -> 0x00064040:DP_TP_CTL_A [11.117841] HW.GFX.GMA.Pipe_Setup.On [11.121481] HW.GFX.GMA.Transcoder.Setup [11.125403] HW.GFX.GMA.Transcoder.Setup_Link [11.129810] HW.GFX.GMA.DP_Info.Calculate_M_N [11.134213] HW.GFX.GMA.Registers.Write: 0x7e4bbbbb -> 0x0006f030:PIPE_EDP_DATA_M1 [11.142164] HW.GFX.GMA.Registers.Write: 0x00800000 -> 0x0006f034:PIPE_EDP_DATA_N1 [11.150111] HW.GFX.GMA.Registers.Write: 0x00086a31 -> 0x0006f040:PIPE_EDP_LINK_M1 [11.158056] HW.GFX.GMA.Registers.Write: 0x00100000 -> 0x0006f044:PIPE_EDP_LINK_N1 [11.166003] HW.GFX.GMA.Registers.Write: 0x00000001 -> 0x0006f410:PIPE_EDP_MSA_MISC [11.174046] HW.GFX.GMA.Registers.Write: 0x0833077f -> 0x0006f000:HTOTAL_EDP [11.181422] HW.GFX.GMA.Registers.Write: 0x0833077f -> 0x0006f004:HBLANK_EDP [11.188791] HW.GFX.GMA.Registers.Write: 0x081b07eb -> 0x0006f008:HSYNC_EDP [11.196071] HW.GFX.GMA.Registers.Write: 0x04650437 -> 0x0006f00c:VTOTAL_EDP [11.203443] HW.GFX.GMA.Registers.Write: 0x04650437 -> 0x0006f010:VBLANK_EDP [11.210814] HW.GFX.GMA.Registers.Write: 0x044b0441 -> 0x0006f014:VSYNC_EDP [11.218092] HW.GFX.GMA.Pipe_Setup.Setup_FB [11.222305] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070080:CUR_CTL_A [11.229583] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00070088:CUR_POS_A [11.236847] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070084:CUR_BASE_A [11.244220] HW.GFX.GMA.Pipe_Setup.Setup_Display [11.248914] HW.GFX.GMA.Registers.Write: 0x009f0008 -> 0x0007027c:PLANE_BUF_CFG_1_A [11.256956] HW.GFX.GMA.Registers.Write: 0x80008098 -> 0x00070240:PLANE_WM_1_A_0 [11.264713] HW.GFX.GMA.Registers.Write: 0x00070000 -> 0x0007017c:CUR_BUF_CFG_A [11.272369] HW.GFX.GMA.Registers.Write: 0x80008008 -> 0x00070140:CUR_WM_A_0 [11.279745] HW.GFX.GMA.Pipe_Setup.Setup_Hires_Plane [11.284820] HW.GFX.GMA.Registers.Write: 0x84002000 -> 0x00070180:DSPACNTR [11.291992] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000701a4:DSPATILEOFF [11.299458] HW.GFX.GMA.Registers.Write: 0x0437077f -> 0x00070190:PLANE_SIZE_1_A [11.307217] HW.GFX.GMA.Registers.Write: 0x00000078 -> 0x00070188:DSPASTRIDE [11.314588] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007018c:PLANE_POS_1_A [11.322249] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007019c:DSPASURF [11.329431] HW.GFX.GMA.Registers.Write: 0x077f0437 -> 0x0006001c:PIPEASRC [11.336612] HW.GFX.GMA.Registers.Write: 0x00000050 -> 0x00070030:PIPEAMISC [11.343888] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_1_A [11.350782] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068180:PS_CTRL_1_A [11.358250] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068180:PS_CTRL_1_A [11.365718] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068174:PS_WIN_SZ_1_A [11.373378] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_2_A [11.380274] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068280:PS_CTRL_2_A [11.387740] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068280:PS_CTRL_2_A [11.395212] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068274:PS_WIN_SZ_2_A [11.402869] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070080:CUR_CTL_A [11.410146] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00070088:CUR_POS_A [11.417425] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070084:CUR_BASE_A [11.424798] HW.GFX.GMA.Registers.Write: 0x82200002 -> 0x0006f400:PIPE_EDP_DDI_FUNC_CTL [11.433225] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x0007f008:PIPE_EDP_CONF [11.440883] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x0007f008:PIPE_EDP_CONF [11.448544] HW.GFX.GMA.Connectors.Post_On [11.452659] HW.GFX.GMA.Connectors.DDI.Post_On [11.457159] HW.GFX.GMA.Panel.Backlight_On [11.461278] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S BLC_PWM_PCH_CTL1 [11.468469] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c8250:BLC_PWM_PCH_CTL1 [11.476407] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c8250:BLC_PWM_PCH_CTL1 [11.484367] HW.GFX.GMA.Registers.Set_Mask: 0x00000004 .S PCH_PP_CONTROL [11.491350] HW.GFX.GMA.Registers.Read: 0x00000073 <- 0x000c7204:PCH_PP_CONTROL [11.499099] HW.GFX.GMA.Registers.Write: 0x00000077 -> 0x000c7204:PCH_PP_CONTROL [11.506866] Enabled port eDP framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32 x_res x y_res: 1920 x 1080, size: 8294400 at 0x90000000 PCI: 00:02.0 init finished in 6847 msecs POST: 0x75 PCI: 00:04.0 init PCI: 00:04.0 init finished in 0 msecs POST: 0x75 POST: 0x75 PCI: 00:12.0 init PCI: 00:12.0 init finished in 0 msecs POST: 0x75 PCI: 00:14.0 init PCI: 00:14.0 init finished in 0 msecs POST: 0x75 PCI: 00:14.2 init PCI: 00:14.2 init finished in 0 msecs POST: 0x75 PCI: 00:16.0 init PCI: 00:16.0 init finished in 0 msecs POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:1c.0 init Initializing PCH PCIe bridge. PCI: 00:1c.0 init finished in 2 msecs POST: 0x75 PCI: 00:1c.5 init Initializing PCH PCIe bridge. PCI: 00:1c.5 init finished in 2 msecs POST: 0x75 PCI: 00:1c.6 init Initializing PCH PCIe bridge. PCI: 00:1c.6 init finished in 3 msecs POST: 0x75 PCI: 00:1c.7 init Initializing PCH PCIe bridge. PCI: 00:1c.7 init finished in 2 msecs POST: 0x75 PCI: 00:1d.0 init Initializing PCH PCIe bridge. PCI: 00:1d.0 init finished in 3 msecs POST: 0x75 PCI: 00:1f.0 init IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x02 PCI: 00:1f.0 init finished in 10 msecs POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:1f.3 init HDA: codec_mask = 01 HDA: Initializing codec #0 HDA: codec viddid: 10ec0262 HDA: verb loaded. PCI: 00:1f.3 init finished in 14 msecs POST: 0x75 PCI: 00:1f.4 init PCI: 00:1f.4 init finished in 0 msecs POST: 0x75 POST: 0x75 PCI: 00:1f.6 init PCI: 00:1f.6 init finished in 0 msecs POST: 0x75 PCI: 01:00.0 init PCI: 01:00.0 init finished in 0 msecs POST: 0x75 PCI: 03:00.0 init PCI: 03:00.0 init finished in 0 msecs POST: 0x75 POST: 0x75 PNP: 002e.1 init PNP: 002e.1 init finished in 0 msecs POST: 0x75 PNP: 002e.2 init PNP: 002e.2 init finished in 0 msecs POST: 0x75 POST: 0x75 PNP: 002e.4 init Unsupported thermal mode 0x0 on TMPIN1 Unsupported thermal mode 0x0 on TMPIN2 Unsupported thermal mode 0x0 on TMPIN3 PNP: 002e.4 init finished in 11 msecs POST: 0x75 POST: 0x75 POST: 0x75 PNP: 002e.7 init PNP: 002e.7 init finished in 0 msecs POST: 0x75 PNP: 002e.8 init PNP: 002e.8 init finished in 0 msecs POST: 0x75 PNP: 002e.9 init PNP: 002e.9 init finished in 0 msecs POST: 0x75 POST: 0x75 POST: 0x75 Devices initialized BS: BS_DEV_INIT run times (exec / console): 6826 / 281 ms apm_control: Disabling ACPI. APMC done. BS: BS_DEV_INIT exit times (exec / console): 0 / 4 ms POST: 0x76 Finalize devices... PCI: 00:17.0 final Devices finalized BS: BS_POST_DEVICE run times (exec / console): 0 / 7 ms POST: 0x77 BS: BS_OS_RESUME_CHECK run times (exec / console): 0 / 1 ms ME: HFSTS1 : 0x90000255 ME: HFSTS2 : 0x30858106 ME: HFSTS3 : 0x00000030 ME: HFSTS4 : 0x00004000 ME: HFSTS5 : 0x00000000 ME: HFSTS6 : 0x00400000 ME: Manufacturing Mode : YES ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : YES ME: Boot Options Present : NO ME: Update In Progress : NO ME: D0i3 Support : YES ME: Low Power State Enabled : NO ME: CPU Replaced : NO ME: CPU Replacement Valid : YES ME: Current Working State : 5 ME: Current Operation State : 1 ME: Current Operation Mode : 0 ME: Error Code : 0 ME: CPU Debug Disabled : NO ME: TXT Support : NO BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 77 ms POST: 0x79 POST: 0x9c CBFS: Found 'fallback/dsdt.aml' @0x93800 size 0x280a in mcache @0x89d0d1c8 CBFS: 'fallback/slic' not found. ACPI: Writing ACPI tables at 89c05000. ACPI: * FACS ACPI: * DSDT PCI space above 4GB MMIO is at 0x106c800000, len = 0x6f93800000 ACPI: * FADT SCI is IRQ9 ACPI: added table 1/32, length now 40 ACPI: * SSDT Found 1 CPU(s) with 6/12 physical/logical core(s) each. PPI: Pending OS request: 0x0 (0x0) PPI: OS response: CMD 0x0 = 0x0 \_SB.PCI0.LPCB.TPM.TPM: LPC TPM PNP: 0c31.0 \_SB.PCI0.RP01.WF00: PCI: 01:00.0 ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TPM2 TPM2 log created at 0x89bf5000 ACPI: added table 4/32, length now 52 ACPI: * LPIT ACPI: added table 5/32, length now 56 ACPI: * MADT SCI is IRQ9 ACPI: added table 6/32, length now 60 current = 89c08f90 ACPI: * DMAR ACPI: added table 7/32, length now 64 acpi_write_dbg2_pci_uart: Device not found ACPI: * HPET ACPI: added table 8/32, length now 68 ACPI: done. ACPI tables: 16480 bytes. smbios_write_tables: 89bf4000 SMBIOS firmware version is set to coreboot_version: '4.13-3465-g567d4dbacd-dirty' Create SMBIOS type 16 Create SMBIOS type 17 PCI: 01:00.0 (unknown) SMBIOS tables: 1209 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum e61b Writing coreboot table at 0x89c29000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-0000000089bf3fff: RAM 4. 0000000089bf4000-0000000089c78fff: CONFIGURATION TABLES 5. 0000000089c79000-0000000089ce0fff: RAMSTAGE 6. 0000000089ce1000-0000000089ffffff: CONFIGURATION TABLES 7. 000000008a000000-000000008f7fffff: RESERVED 8. 00000000e0000000-00000000efffffff: RESERVED 9. 00000000fc000000-00000000fc000fff: RESERVED 10. 00000000fe000000-00000000fe00ffff: RESERVED 11. 00000000fed10000-00000000fed17fff: RESERVED 12. 00000000fed40000-00000000fed44fff: RESERVED 13. 00000000fed80000-00000000fed83fff: RESERVED 14. 00000000fed90000-00000000fed91fff: RESERVED 15. 00000000feda0000-00000000feda1fff: RESERVED 16. 0000000100000000-000000106c7fffff: RAM SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 Wrote coreboot table at: 0x89c29000, 0x4f6 bytes, checksum 685b coreboot table: 1294 bytes. IMD ROOT 0. 0x89fff000 0x00001000 IMD SMALL 1. 0x89ffe000 0x00001000 FSP MEMORY 2. 0x89d0e000 0x002f0000 RO MCACHE 3. 0x89d0d000 0x00000378 CONSOLE 4. 0x89ced000 0x00020000 TIME STAMP 5. 0x89cec000 0x00000910 ROMSTG STCK 6. 0x89ceb000 0x00001000 AFTER CAR 7. 0x89ce1000 0x0000a000 RAMSTAGE 8. 0x89c78000 0x00069000 REFCODE 9. 0x89c43000 0x00035000 SMM BACKUP 10. 0x89c33000 0x00010000 4f444749 11. 0x89c31000 0x00002000 COREBOOT 12. 0x89c29000 0x00008000 ACPI 13. 0x89c05000 0x00024000 TPM2 TCGLOG14. 0x89bf5000 0x00010000 SMBIOS 15. 0x89bf4000 0x00000800 IMD small region: IMD ROOT 0. 0x89ffec00 0x00000400 FSP RUNTIME 1. 0x89ffebe0 0x00000004 FMAP 2. 0x89ffeac0 0x0000010a POWER STATE 3. 0x89ffea80 0x00000040 ROMSTAGE 4. 0x89ffea60 0x00000004 MEM INFO 5. 0x89ffe880 0x000001e0 ACPI GNVS 6. 0x89ffe780 0x00000100 54505049 7. 0x89ffe620 0x0000015a BS: BS_WRITE_TABLES run times (exec / console): 1 / 332 ms MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x000000008a000000 size 0x89f40000 type 6 0x000000008a000000 - 0x0000000090000000 size 0x06000000 type 0 0x0000000090000000 - 0x00000000a0000000 size 0x10000000 type 1 0x00000000a0000000 - 0x0000000100000000 size 0x60000000 type 0 0x0000000100000000 - 0x000000106c800000 size 0xf6c800000 type 6 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 CPU physical address size: 39 bits MTRR: default type WB/UC MTRR counts: 5/9. MTRR: WB selected as default type. MTRR: 0 base 0x000000008a000000 mask 0x0000007ffe000000 type 0 MTRR: 1 base 0x000000008c000000 mask 0x0000007ffc000000 type 0 MTRR: 2 base 0x0000000090000000 mask 0x0000007ff0000000 type 1 MTRR: 3 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0 MTRR: 4 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 CPU physical address size: 39 bits BS: BS_WRITE_TABLES exit times (exec / console): 49 / 142 ms MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 CPU physical address size: 39 bits CPU physical address size: 39 bits MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 CPU physical address size: 39 bits CPU physical address size: 39 bits POST: 0x7a MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 CPU physical address size: 39 bits CPU physical address size: 39 bits MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 CPU physical address size: 39 bits CPU physical address size: 39 bits CBFS: Found 'fallback/payload' @0x1507c0 size 0xb1a94 in mcache @0x89d0d2e8 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 CPU physical address size: 39 bits CPU physical address size: 39 bits Checking segment from ROM address 0xff9a09ec Checking segment from ROM address 0xff9a0a08 Loading segment from ROM address 0xff9a09ec code (compression=1) New segment dstaddr 0x00800000 memsize 0x410000 srcaddr 0xff9a0a24 filesize 0xb1a5c Loading Segment: addr: 0x00800000 memsz: 0x0000000000410000 filesz: 0x00000000000b1a5c using LZMA Loading segment from ROM address 0xff9a0a08 Entry Point 0x008008f0 BS: BS_PAYLOAD_LOAD run times (exec / console): 1223 / 49 ms POST: 0x95 POST: 0x95 POST: 0x88 POST: 0x89 Finalizing chipset. apm_control: Finalizing SMM. APMC done. POST: 0xfe BS: BS_PAYLOAD_LOAD exit times (exec / console): 13 / 12 ms POST: 0x7b mp_park_aps done after 0 msecs. Jumping to boot code at 0x008008f0(0x89c29000) POST: 0xf8 3h