Nick: hell__
E-mail: NULL
Board: Toshiba A300-1ME (working)
Contents: 


coreboot-4.13-3666-gef04b0bf9e Mon May 10 09:51:33 UTC 2021 bootblock starting (log level: 8)...
FMAP: area COREBOOT found @ 20200 (1965568 bytes)
CBFS: mcache @0xfefc2e00 built for 15 files, used 0x320 of 0x2000 bytes
CBFS: Found 'fallback/romstage' @0x80 size 0x10bf8 in mcache @0xfefc2e2c
BS: bootblock times (exec / console): total (unknown) / 3 ms
PROG_RUN: Setting MTRR to cache XIP stage. base: 0xffe20000, size: 0x00020000


coreboot-4.13-3666-gef04b0bf9e Mon May 10 09:51:33 UTC 2021 romstage starting (log level: 8)...
SMBus controller enabled
Stepping B3
2 CPU cores
ME enabled
AMT enabled
capable of DDR2 of 800 MHz or lower
VT-d enabled
GMCH: PM45
TXT enabled
Render frequency: 667 MHz
PCIe-to-GMCH enabled
GMCH supports DDR3 with 1067 MT or less
GMCH supports FSB with up to 1067 MHz
0:50:8
2:52:ff
DDR mask 1, DDR 2
Bank 0 populated:
 Raw card type:    A
 Row addr bits:   13
 Col addr bits:   10
 byte width:       2
 page size:     2048
 banks:            8
 ranks:            2
 tAAmin:    3840
 tCKmin:    768
  Max clock: 333 MHz
 CAS:       0x0038
Trying CAS 5, tCK 768.
Found compatible clock / CAS pair: 333 / 5.
Timing values:
 tCLK:  768
 tRAS:   15
 tRP:     5
 tRCD:    5
 tRFC:   43
 tWR:     5
 tRD:     8
 tRRD:    4
 tFAW:   17
 tWL:     4
Changing memory frequency: old 3, new 4.
Skipping IGD memory frequency setting.
Memory configured in single-channel mode.
Memory map:
TOM   =   256MB
TOLUD =   256MB
TOUUD =   256MB
REMAP:	 base  = 65535MB
	 limit =     0MB
usedMEsize: 0MB
JEDEC init @0x00000000
JEDEC init @0x08000000
group 0, ch 0: 4.0.2.8.0
group 1, ch 0: 4.0.2.8.0
group 2, ch 0: 4.0.2.10.0
group 3, ch 0: 4.0.2.10.0
Memory configured in single-channel mode.
Memory map:
TOM   =  1024MB
TOLUD =   992MB
TOUUD =   992MB
REMAP:	 base  = 65535MB
	 limit =     0MB
usedMEsize: 32MB
Disabling IGD.
PEG x16 enabled, SDVO disabled
ICH9 waits for VC1 negotiation... done.
ICH9 waits for port arbitration table update... done.
CBMEM:
IMD: root @ 0x3dbff000 254 entries.
IMD: root @ 0x3dbfec00 62 entries.
FMAP: area COREBOOT found @ 20200 (1965568 bytes)
External stage cache:
IMD: root @ 0x3dfff000 254 entries.
IMD: root @ 0x3dffec00 62 entries.
exit main()
SMM Memory Map
SMRAM       : 0x3de00000 0x200000
 Subregion 0: 0x3de00000 0x100000
 Subregion 1: 0x3df00000 0x100000
 Subregion 2: 0x3e000000 0x0
MTRR Range: Start=3d400000 End=3d800000 (Size 400000)
MTRR Range: Start=3d800000 End=3dc00000 (Size 400000)
MTRR Range: Start=3de00000 End=3e000000 (Size 200000)
MTRR Range: Start=ffe00000 End=0 (Size 200000)
Normal boot
CBFS: Found 'fallback/postcar' @0x59a80 size 0x8148 in mcache @0xfefc3018
Loading module at 0x3dbcf000 with entry 0x3dbcf031. filesize: 0x7a10 memsize: 0xbe48
Processing 446 relocs. Offset value of 0x3bbcf000
BS: romstage times (exec / console): total (unknown) / 17 ms


coreboot-4.13-3666-gef04b0bf9e Mon May 10 09:51:33 UTC 2021 postcar starting (log level: 8)...
Normal boot
FMAP: area COREBOOT found @ 20200 (1965568 bytes)
CBFS: Found 'fallback/ramstage' @0x31d40 size 0x14f22 in mcache @0x3dbfd0dc
Loading module at 0x3db92000 with entry 0x3db92000. filesize: 0x2a050 memsize: 0x3b250
Processing 3115 relocs. Offset value of 0x3cd92000
BS: postcar times (exec / console): total (unknown) / 2 ms


coreboot-4.13-3666-gef04b0bf9e Mon May 10 09:51:33 UTC 2021 ramstage starting (log level: 8)...
Normal boot
Initializing i82801ix southbridge...
Enumerating buses...
Show all devs... Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
DOMAIN: 0000: enabled 1
APIC: 00: enabled 1
APIC: acac: enabled 0
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 0
PCI: 00:02.1: enabled 0
PCI: 00:03.0: enabled 0
PCI: 00:03.1: enabled 0
PCI: 00:03.2: enabled 0
PCI: 00:03.3: enabled 0
PCI: 00:19.0: enabled 0
PCI: 00:1a.0: enabled 1
PCI: 00:1a.1: enabled 1
PCI: 00:1a.2: enabled 0
PCI: 00:1a.7: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 1
PCI: 00:1c.1: enabled 0
PCI: 00:1c.2: enabled 0
PCI: 00:1c.3: enabled 0
PCI: 00:1c.4: enabled 1
PCI: 00:1c.5: enabled 0
PCI: 00:1d.0: enabled 1
PCI: 00:1d.1: enabled 1
PCI: 00:1d.2: enabled 1
PCI: 00:1d.7: enabled 1
PCI: 00:1e.0: enabled 1
PCI: 00:1f.0: enabled 1
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
PCI: 00:1f.5: enabled 0
PCI: 00:1f.6: enabled 0
Compare with tree...
Root Device: enabled 1
 CPU_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
  APIC: acac: enabled 0
 DOMAIN: 0000: enabled 1
  PCI: 00:00.0: enabled 1
  PCI: 00:01.0: enabled 1
  PCI: 00:02.0: enabled 0
  PCI: 00:02.1: enabled 0
  PCI: 00:03.0: enabled 0
  PCI: 00:03.1: enabled 0
  PCI: 00:03.2: enabled 0
  PCI: 00:03.3: enabled 0
  PCI: 00:19.0: enabled 0
  PCI: 00:1a.0: enabled 1
  PCI: 00:1a.1: enabled 1
  PCI: 00:1a.2: enabled 0
  PCI: 00:1a.7: enabled 1
  PCI: 00:1b.0: enabled 1
  PCI: 00:1c.0: enabled 1
  PCI: 00:1c.1: enabled 0
  PCI: 00:1c.2: enabled 0
  PCI: 00:1c.3: enabled 0
  PCI: 00:1c.4: enabled 1
  PCI: 00:1c.5: enabled 0
  PCI: 00:1d.0: enabled 1
  PCI: 00:1d.1: enabled 1
  PCI: 00:1d.2: enabled 1
  PCI: 00:1d.7: enabled 1
  PCI: 00:1e.0: enabled 1
  PCI: 00:1f.0: enabled 1
  PCI: 00:1f.2: enabled 1
  PCI: 00:1f.3: enabled 1
  PCI: 00:1f.5: enabled 0
  PCI: 00:1f.6: enabled 0
Root Device scanning...
scan_static_bus for Root Device
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/2a40] enabled
PCI: 00:01.0 subordinate bus PCI Express
PCI: 00:01.0 [8086/2a41] enabled
PCI: 00:1a.0 [8086/2937] enabled
PCI: 00:1a.1 [8086/2938] enabled
PCI: 00:1a.7 [8086/0000] ops
PCI: 00:1a.7 [8086/293c] enabled
PCI: 00:1b.0 [8086/293e] ops
PCI: 00:1b.0 [8086/293e] enabled
PCI: 00:1c.0 [8086/0000] bus ops
PCI: 00:1c.0 [8086/2940] enabled
PCI: 00:1c.4 [8086/0000] bus ops
PCI: 00:1c.4 [8086/2948] enabled
PCI: 00:1d.0 [8086/2934] enabled
PCI: 00:1d.1 [8086/2935] enabled
PCI: 00:1d.2 [8086/2936] enabled
PCI: 00:1d.7 [8086/0000] ops
PCI: 00:1d.7 [8086/293a] enabled
PCI: 00:1e.0 [8086/0000] bus ops
PCI: 00:1e.0 [8086/2448] enabled
PCI: 00:1f.0 [8086/0000] bus ops
PCI: 00:1f.0 [8086/2919] enabled
PCI: 00:1f.2 [8086/0000] ops
PCI: 00:1f.2 [8086/2928] enabled
PCI: 00:1f.3 [8086/2930] bus ops
PCI: 00:1f.3 [8086/2930] enabled
PCI: Leftover static devices:
PCI: 00:02.0
PCI: 00:02.1
PCI: 00:03.0
PCI: 00:03.1
PCI: 00:03.2
PCI: 00:03.3
PCI: 00:19.0
PCI: 00:1a.2
PCI: 00:1c.1
PCI: 00:1c.2
PCI: 00:1c.3
PCI: 00:1c.5
PCI: 00:1f.5
PCI: 00:1f.6
PCI: Check your devicetree.cb.
PCI: 00:01.0 scanning...
do_pci_scan_bridge for PCI: 00:01.0
PCI: 00:01.0: No LTR support
PCI: pci_scan_bus for bus 01
PCI: 01:00.0 [1002/95c4] enabled
PCI: 01:00.1 [1002/aa28] enabled
PCIe: Max_Payload_Size adjusted to 128
PCI: 01:00.0: No LTR support
PCIe: Max_Payload_Size adjusted to 128
PCI: 01:00.1: No LTR support
scan_bus: bus PCI: 00:01.0 finished in 1 msecs
PCI: 00:1c.0 scanning...
do_pci_scan_bridge for PCI: 00:1c.0
PCI: 00:1c.0: No LTR support
PCI: pci_scan_bus for bus 02
PCI: 02:00.0 [10ec/8136] enabled
PCIe: Max_Payload_Size adjusted to 128
PCI: 02:00.0: No LTR support
scan_bus: bus PCI: 00:1c.0 finished in 1 msecs
PCI: 00:1c.4 scanning...
do_pci_scan_bridge for PCI: 00:1c.4
PCI: 00:1c.4: No LTR support
PCI: pci_scan_bus for bus 03
scan_bus: bus PCI: 00:1c.4 finished in 0 msecs
PCI: 00:1e.0 scanning...
do_pci_scan_bridge for PCI: 00:1e.0
PCI: pci_scan_bus for bus 04
PCI: 04:06.0 [1180/0832] enabled
PCI: 04:06.1 [1180/0822] enabled
PCI: 04:06.2 [1180/0843] enabled
PCI: 04:06.3 [1180/0592] enabled
PCI: 04:06.4 [1180/0852] enabled
scan_bus: bus PCI: 00:1e.0 finished in 1 msecs
PCI: 00:1f.0 scanning...
scan_static_bus for PCI: 00:1f.0
scan_static_bus for PCI: 00:1f.0 done
scan_bus: bus PCI: 00:1f.0 finished in 0 msecs
PCI: 00:1f.3 scanning...
scan_generic_bus for PCI: 00:1f.3
scan_generic_bus for PCI: 00:1f.3 done
scan_bus: bus PCI: 00:1f.3 finished in 0 msecs
scan_bus: bus DOMAIN: 0000 finished in 13 msecs
scan_static_bus for Root Device done
scan_bus: bus Root Device finished in 14 msecs
done
BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 24 ms
found VGA at PCI: 01:00.0
Setting up VGA for PCI: 01:00.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0
CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
TOUUD 0x3e000000 TOLUD 0x3e000000 TOM 0x40000000
 and 2M TSEG
Unused RAM between cbmem_top and TOM: 0x800K
Available memory below 4GB: 988M
Adding UMA memory area base=0x3dc00000 size=0x400000
Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:1c.0 read_resources bus 2 link: 0
PCI: 00:1c.0 read_resources bus 2 link: 0 done
PCI: 00:1c.4 read_resources bus 3 link: 0
PCI: 00:1c.4 read_resources bus 3 link: 0 done
PCI: 00:1e.0 read_resources bus 4 link: 0
PCI: 00:1e.0 read_resources bus 4 link: 0 done
DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 CPU_CLUSTER: 0
  CPU_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
   APIC: acac
  DOMAIN: 0000 child on link 0 PCI: 00:00.0
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit fffffffff flags 40040200 index 10000100
  DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
  DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 4
  DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 5
  DOMAIN: 0000 resource base 100000 size 3db00000 align 0 gran 0 limit 0 flags e0004200 index 6
  DOMAIN: 0000 resource base 3dc00000 size 400000 align 0 gran 0 limit 0 flags f0000200 index 8
  DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 9
   PCI: 00:00.0
   PCI: 00:01.0 child on link 0 PCI: 01:00.0
   PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 01:00.0
    PCI: 01:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10
    PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
    PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 200 index 18
    PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
    PCI: 01:00.1
    PCI: 01:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
   PCI: 00:1a.0
   PCI: 00:1a.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:1a.1
   PCI: 00:1a.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:1a.7
   PCI: 00:1a.7 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
   PCI: 00:1b.0
   PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
   PCI: 00:1c.0 child on link 0 PCI: 02:00.0
   PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 02:00.0
    PCI: 02:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
    PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 1201 index 18
    PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 1201 index 20
   PCI: 00:1c.4
   PCI: 00:1c.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
   PCI: 00:1d.0
   PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:1d.1
   PCI: 00:1d.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:1d.2
   PCI: 00:1d.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:1d.7
   PCI: 00:1d.7 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
   PCI: 00:1e.0 child on link 0 PCI: 04:06.0
   PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 04:06.0
    PCI: 04:06.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 10
    PCI: 04:06.1
    PCI: 04:06.1 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
    PCI: 04:06.2
    PCI: 04:06.2 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
    PCI: 04:06.3
    PCI: 04:06.3 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
    PCI: 04:06.4
    PCI: 04:06.4 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10
   PCI: 00:1f.0
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
   PCI: 00:1f.2
   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
   PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
   PCI: 00:1f.3
   PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
   PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
 PCI: 00:01.0 io: size: 0 align: 12 gran: 12 limit: ffff
  PCI: 01:00.0 14 *  [0x0 - 0xff] io
 PCI: 00:01.0 io: size: 1000 align: 12 gran: 12 limit: ffff done
 PCI: 00:01.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  PCI: 01:00.0 30 *  [0x0 - 0x1ffff] mem
  PCI: 01:00.0 18 *  [0x20000 - 0x2ffff] mem
  PCI: 01:00.1 10 *  [0x30000 - 0x33fff] mem
 PCI: 00:01.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
 PCI: 00:01.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
  PCI: 01:00.0 10 *  [0x0 - 0xfffffff] prefmem
 PCI: 00:01.0 prefmem: size: 10000000 align: 28 gran: 20 limit: ffffffff done
 PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff
  PCI: 02:00.0 10 *  [0x0 - 0xff] io
 PCI: 00:1c.0 io: size: 1000 align: 12 gran: 12 limit: ffff done
 PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
 PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff done
 PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
  PCI: 02:00.0 20 *  [0x0 - 0xffff] prefmem
  PCI: 02:00.0 18 *  [0x10000 - 0x10fff] prefmem
 PCI: 00:1c.0 prefmem: size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done
 PCI: 00:1e.0 io: size: 0 align: 12 gran: 12 limit: ffff
 PCI: 00:1e.0 io: size: 0 align: 12 gran: 12 limit: ffff done
 PCI: 00:1e.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  PCI: 04:06.0 10 *  [0x0 - 0x7ff] mem
  PCI: 04:06.1 10 *  [0x1000 - 0x10ff] mem
  PCI: 04:06.2 10 *  [0x2000 - 0x20ff] mem
  PCI: 04:06.3 10 *  [0x3000 - 0x30ff] mem
  PCI: 04:06.4 10 *  [0x4000 - 0x40ff] mem
 PCI: 00:1e.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
 PCI: 00:1e.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
 PCI: 00:1e.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
=== Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
 update_constraints: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
 update_constraints: PCI: 00:1f.3 20 base 00000400 limit 0000041f io (fixed)
 DOMAIN: 0000: Resource ranges:
 * Base: 1000, Size: f000, Tag: 100
  PCI: 00:01.0 1c *  [0x1000 - 0x1fff] limit: 1fff io
  PCI: 00:1c.0 1c *  [0x2000 - 0x2fff] limit: 2fff io
  PCI: 00:1a.0 20 *  [0x3000 - 0x301f] limit: 301f io
  PCI: 00:1a.1 20 *  [0x3020 - 0x303f] limit: 303f io
  PCI: 00:1d.0 20 *  [0x3040 - 0x305f] limit: 305f io
  PCI: 00:1d.1 20 *  [0x3060 - 0x307f] limit: 307f io
  PCI: 00:1d.2 20 *  [0x3080 - 0x309f] limit: 309f io
  PCI: 00:1f.2 20 *  [0x30a0 - 0x30bf] limit: 30bf io
  PCI: 00:1f.2 10 *  [0x30c0 - 0x30c7] limit: 30c7 io
  PCI: 00:1f.2 18 *  [0x30c8 - 0x30cf] limit: 30cf io
  PCI: 00:1f.2 14 *  [0x30d0 - 0x30d3] limit: 30d3 io
  PCI: 00:1f.2 1c *  [0x30d4 - 0x30d7] limit: 30d7 io
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff
 update_constraints: DOMAIN: 0000 03 base 00000000 limit 0009ffff mem (fixed)
 update_constraints: DOMAIN: 0000 04 base 000a0000 limit 000bffff mem (fixed)
 update_constraints: DOMAIN: 0000 05 base 000c0000 limit 000fffff mem (fixed)
 update_constraints: DOMAIN: 0000 06 base 00100000 limit 3dbfffff mem (fixed)
 update_constraints: DOMAIN: 0000 08 base 3dc00000 limit 3dffffff mem (fixed)
 update_constraints: DOMAIN: 0000 09 base f0000000 limit f3ffffff mem (fixed)
 update_constraints: PCI: 00:1f.0 10000100 base ff800000 limit ffffffff mem (fixed)
 update_constraints: PCI: 00:1f.0 03 base fec00000 limit fec00fff mem (fixed)
 DOMAIN: 0000: Resource ranges:
 * Base: 3e000000, Size: b2000000, Tag: 200
 * Base: f4000000, Size: ac00000, Tag: 200
 * Base: fec01000, Size: bff000, Tag: 200
 * Base: 100000000, Size: f00000000, Tag: 100200
  PCI: 00:01.0 24 *  [0x40000000 - 0x4fffffff] limit: 4fffffff prefmem
  PCI: 00:01.0 20 *  [0x3e000000 - 0x3e0fffff] limit: 3e0fffff mem
  PCI: 00:1c.0 24 *  [0x3e100000 - 0x3e1fffff] limit: 3e1fffff prefmem
  PCI: 00:1e.0 20 *  [0x3e200000 - 0x3e2fffff] limit: 3e2fffff mem
  PCI: 00:1b.0 10 *  [0x3e300000 - 0x3e303fff] limit: 3e303fff mem
  PCI: 00:1f.2 24 *  [0x3e304000 - 0x3e3047ff] limit: 3e3047ff mem
  PCI: 00:1a.7 10 *  [0x3e305000 - 0x3e3053ff] limit: 3e3053ff mem
  PCI: 00:1d.7 10 *  [0x3e306000 - 0x3e3063ff] limit: 3e3063ff mem
  PCI: 00:1f.3 10 *  [0x3e307000 - 0x3e3070ff] limit: 3e3070ff mem
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done
PCI: 00:01.0 io: base: 1000 size: 1000 align: 12 gran: 12 limit: 1fff
 PCI: 00:01.0: Resource ranges:
 * Base: 1000, Size: 1000, Tag: 100
  PCI: 01:00.0 14 *  [0x1000 - 0x10ff] limit: 10ff io
PCI: 00:01.0 io: base: 1000 size: 1000 align: 12 gran: 12 limit: 1fff done
PCI: 00:01.0 prefmem: base: 40000000 size: 10000000 align: 28 gran: 20 limit: 4fffffff
 PCI: 00:01.0: Resource ranges:
 * Base: 40000000, Size: 10000000, Tag: 1200
  PCI: 01:00.0 10 *  [0x40000000 - 0x4fffffff] limit: 4fffffff prefmem
PCI: 00:01.0 prefmem: base: 40000000 size: 10000000 align: 28 gran: 20 limit: 4fffffff done
PCI: 00:01.0 mem: base: 3e000000 size: 100000 align: 20 gran: 20 limit: 3e0fffff
 PCI: 00:01.0: Resource ranges:
 * Base: 3e000000, Size: 100000, Tag: 200
  PCI: 01:00.0 30 *  [0x3e000000 - 0x3e01ffff] limit: 3e01ffff mem
  PCI: 01:00.0 18 *  [0x3e020000 - 0x3e02ffff] limit: 3e02ffff mem
  PCI: 01:00.1 10 *  [0x3e030000 - 0x3e033fff] limit: 3e033fff mem
PCI: 00:01.0 mem: base: 3e000000 size: 100000 align: 20 gran: 20 limit: 3e0fffff done
PCI: 00:1c.0 io: base: 2000 size: 1000 align: 12 gran: 12 limit: 2fff
 PCI: 00:1c.0: Resource ranges:
 * Base: 2000, Size: 1000, Tag: 100
  PCI: 02:00.0 10 *  [0x2000 - 0x20ff] limit: 20ff io
PCI: 00:1c.0 io: base: 2000 size: 1000 align: 12 gran: 12 limit: 2fff done
PCI: 00:1c.0 prefmem: base: 3e100000 size: 100000 align: 20 gran: 20 limit: 3e1fffff
 PCI: 00:1c.0: Resource ranges:
 * Base: 3e100000, Size: 100000, Tag: 1200
  PCI: 02:00.0 20 *  [0x3e100000 - 0x3e10ffff] limit: 3e10ffff prefmem
  PCI: 02:00.0 18 *  [0x3e110000 - 0x3e110fff] limit: 3e110fff prefmem
PCI: 00:1c.0 prefmem: base: 3e100000 size: 100000 align: 20 gran: 20 limit: 3e1fffff done
PCI: 00:1e.0 mem: base: 3e200000 size: 100000 align: 20 gran: 20 limit: 3e2fffff
 PCI: 00:1e.0: Resource ranges:
 * Base: 3e200000, Size: 100000, Tag: 200
  PCI: 04:06.0 10 *  [0x3e200000 - 0x3e2007ff] limit: 3e2007ff mem
  PCI: 04:06.1 10 *  [0x3e201000 - 0x3e2010ff] limit: 3e2010ff mem
  PCI: 04:06.2 10 *  [0x3e202000 - 0x3e2020ff] limit: 3e2020ff mem
  PCI: 04:06.3 10 *  [0x3e203000 - 0x3e2030ff] limit: 3e2030ff mem
  PCI: 04:06.4 10 *  [0x3e204000 - 0x3e2040ff] limit: 3e2040ff mem
PCI: 00:1e.0 mem: base: 3e200000 size: 100000 align: 20 gran: 20 limit: 3e2fffff done
=== Resource allocator: DOMAIN: 0000 - resource allocation complete ===
Root Device assign_resources, bus 0 link: 0
DOMAIN: 0000 03 <- [0x0000000000 - 0x000009ffff] size 0x000a0000 gran 0x00 mem
DOMAIN: 0000 04 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem
DOMAIN: 0000 05 <- [0x00000c0000 - 0x00000fffff] size 0x00040000 gran 0x00 mem
DOMAIN: 0000 06 <- [0x0000100000 - 0x003dbfffff] size 0x3db00000 gran 0x00 mem
DOMAIN: 0000 08 <- [0x003dc00000 - 0x003dffffff] size 0x00400000 gran 0x00 mem
DOMAIN: 0000 09 <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem
DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:01.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x0040000000 - 0x004fffffff] size 0x10000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x003e000000 - 0x003e0fffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 01:00.0 10 <- [0x0040000000 - 0x004fffffff] size 0x10000000 gran 0x1c prefmem
PCI: 01:00.0 14 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 01:00.0 18 <- [0x003e020000 - 0x003e02ffff] size 0x00010000 gran 0x10 mem
PCI: 01:00.0 30 <- [0x003e000000 - 0x003e01ffff] size 0x00020000 gran 0x11 romem
PCI: 01:00.1 10 <- [0x003e030000 - 0x003e033fff] size 0x00004000 gran 0x0e mem
PCI: 00:01.0 assign_resources, bus 1 link: 0 done
PCI: 00:1a.0 20 <- [0x0000003000 - 0x000000301f] size 0x00000020 gran 0x05 io
PCI: 00:1a.1 20 <- [0x0000003020 - 0x000000303f] size 0x00000020 gran 0x05 io
PCI: 00:1a.7 10 <- [0x003e305000 - 0x003e3053ff] size 0x00000400 gran 0x0a mem
PCI: 00:1b.0 10 <- [0x003e300000 - 0x003e303fff] size 0x00004000 gran 0x0e mem64
PCI: 00:1c.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 02 io
PCI: 00:1c.0 24 <- [0x003e100000 - 0x003e1fffff] size 0x00100000 gran 0x14 bus 02 prefmem
PCI: 00:1c.0 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 02 mem
PCI: 00:1c.0 assign_resources, bus 2 link: 0
PCI: 02:00.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
PCI: 02:00.0 18 <- [0x003e110000 - 0x003e110fff] size 0x00001000 gran 0x0c prefmem64
PCI: 02:00.0 20 <- [0x003e100000 - 0x003e10ffff] size 0x00010000 gran 0x10 prefmem64
PCI: 00:1c.0 assign_resources, bus 2 link: 0 done
PCI: 00:1c.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io
PCI: 00:1c.4 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 03 prefmem
PCI: 00:1c.4 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 03 mem
PCI: 00:1d.0 20 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io
PCI: 00:1d.1 20 <- [0x0000003060 - 0x000000307f] size 0x00000020 gran 0x05 io
PCI: 00:1d.2 20 <- [0x0000003080 - 0x000000309f] size 0x00000020 gran 0x05 io
PCI: 00:1d.7 10 <- [0x003e306000 - 0x003e3063ff] size 0x00000400 gran 0x0a mem
PCI: 00:1e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io
PCI: 00:1e.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 04 prefmem
PCI: 00:1e.0 20 <- [0x003e200000 - 0x003e2fffff] size 0x00100000 gran 0x14 bus 04 mem
PCI: 00:1e.0 assign_resources, bus 4 link: 0
PCI: 04:06.0 10 <- [0x003e200000 - 0x003e2007ff] size 0x00000800 gran 0x0b mem
PCI: 04:06.1 10 <- [0x003e201000 - 0x003e2010ff] size 0x00000100 gran 0x08 mem
PCI: 04:06.2 10 <- [0x003e202000 - 0x003e2020ff] size 0x00000100 gran 0x08 mem
PCI: 04:06.3 10 <- [0x003e203000 - 0x003e2030ff] size 0x00000100 gran 0x08 mem
PCI: 04:06.4 10 <- [0x003e204000 - 0x003e2040ff] size 0x00000100 gran 0x08 mem
PCI: 00:1e.0 assign_resources, bus 4 link: 0 done
PCI: 00:1f.2 10 <- [0x00000030c0 - 0x00000030c7] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 14 <- [0x00000030d0 - 0x00000030d3] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 18 <- [0x00000030c8 - 0x00000030cf] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 1c <- [0x00000030d4 - 0x00000030d7] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 20 <- [0x00000030a0 - 0x00000030bf] size 0x00000020 gran 0x05 io
PCI: 00:1f.2 24 <- [0x003e304000 - 0x003e3047ff] size 0x00000800 gran 0x0b mem
PCI: 00:1f.3 10 <- [0x003e307000 - 0x003e3070ff] size 0x00000100 gran 0x08 mem64
DOMAIN: 0000 assign_resources, bus 0 link: 0 done
Root Device assign_resources, bus 0 link: 0 done
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device child on link 0 CPU_CLUSTER: 0
  CPU_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
   APIC: acac
  DOMAIN: 0000 child on link 0 PCI: 00:00.0
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit fffffffff flags 40040200 index 10000100
  DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
  DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 4
  DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 5
  DOMAIN: 0000 resource base 100000 size 3db00000 align 0 gran 0 limit 0 flags e0004200 index 6
  DOMAIN: 0000 resource base 3dc00000 size 400000 align 0 gran 0 limit 0 flags f0000200 index 8
  DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 9
   PCI: 00:00.0
   PCI: 00:01.0 child on link 0 PCI: 01:00.0
   PCI: 00:01.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c
   PCI: 00:01.0 resource base 40000000 size 10000000 align 28 gran 20 limit 4fffffff flags 60081202 index 24
   PCI: 00:01.0 resource base 3e000000 size 100000 align 20 gran 20 limit 3e0fffff flags 60080202 index 20
    PCI: 01:00.0
    PCI: 01:00.0 resource base 40000000 size 10000000 align 28 gran 28 limit 4fffffff flags 60001200 index 10
    PCI: 01:00.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 14
    PCI: 01:00.0 resource base 3e020000 size 10000 align 16 gran 16 limit 3e02ffff flags 60000200 index 18
    PCI: 01:00.0 resource base 3e000000 size 20000 align 17 gran 17 limit 3e01ffff flags 60002200 index 30
    PCI: 01:00.1
    PCI: 01:00.1 resource base 3e030000 size 4000 align 14 gran 14 limit 3e033fff flags 60000200 index 10
   PCI: 00:1a.0
   PCI: 00:1a.0 resource base 3000 size 20 align 5 gran 5 limit 301f flags 60000100 index 20
   PCI: 00:1a.1
   PCI: 00:1a.1 resource base 3020 size 20 align 5 gran 5 limit 303f flags 60000100 index 20
   PCI: 00:1a.7
   PCI: 00:1a.7 resource base 3e305000 size 400 align 12 gran 10 limit 3e3053ff flags 60000200 index 10
   PCI: 00:1b.0
   PCI: 00:1b.0 resource base 3e300000 size 4000 align 14 gran 14 limit 3e303fff flags 60000201 index 10
   PCI: 00:1c.0 child on link 0 PCI: 02:00.0
   PCI: 00:1c.0 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c
   PCI: 00:1c.0 resource base 3e100000 size 100000 align 20 gran 20 limit 3e1fffff flags 60081202 index 24
   PCI: 00:1c.0 resource base ffffffff size 0 align 20 gran 20 limit ffffffff flags 20080202 index 20
    PCI: 02:00.0
    PCI: 02:00.0 resource base 2000 size 100 align 8 gran 8 limit 20ff flags 60000100 index 10
    PCI: 02:00.0 resource base 3e110000 size 1000 align 12 gran 12 limit 3e110fff flags 60001201 index 18
    PCI: 02:00.0 resource base 3e100000 size 10000 align 16 gran 16 limit 3e10ffff flags 60001201 index 20
   PCI: 00:1c.4
   PCI: 00:1c.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
   PCI: 00:1c.4 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
   PCI: 00:1c.4 resource base ffffffff size 0 align 20 gran 20 limit ffffffff flags 20080202 index 20
   PCI: 00:1d.0
   PCI: 00:1d.0 resource base 3040 size 20 align 5 gran 5 limit 305f flags 60000100 index 20
   PCI: 00:1d.1
   PCI: 00:1d.1 resource base 3060 size 20 align 5 gran 5 limit 307f flags 60000100 index 20
   PCI: 00:1d.2
   PCI: 00:1d.2 resource base 3080 size 20 align 5 gran 5 limit 309f flags 60000100 index 20
   PCI: 00:1d.7
   PCI: 00:1d.7 resource base 3e306000 size 400 align 12 gran 10 limit 3e3063ff flags 60000200 index 10
   PCI: 00:1e.0 child on link 0 PCI: 04:06.0
   PCI: 00:1e.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
   PCI: 00:1e.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
   PCI: 00:1e.0 resource base 3e200000 size 100000 align 20 gran 20 limit 3e2fffff flags 60080202 index 20
    PCI: 04:06.0
    PCI: 04:06.0 resource base 3e200000 size 800 align 12 gran 11 limit 3e2007ff flags 60000200 index 10
    PCI: 04:06.1
    PCI: 04:06.1 resource base 3e201000 size 100 align 12 gran 8 limit 3e2010ff flags 60000200 index 10
    PCI: 04:06.2
    PCI: 04:06.2 resource base 3e202000 size 100 align 12 gran 8 limit 3e2020ff flags 60000200 index 10
    PCI: 04:06.3
    PCI: 04:06.3 resource base 3e203000 size 100 align 12 gran 8 limit 3e2030ff flags 60000200 index 10
    PCI: 04:06.4
    PCI: 04:06.4 resource base 3e204000 size 100 align 12 gran 8 limit 3e2040ff flags 60000200 index 10
   PCI: 00:1f.0
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
   PCI: 00:1f.2
   PCI: 00:1f.2 resource base 30c0 size 8 align 3 gran 3 limit 30c7 flags 60000100 index 10
   PCI: 00:1f.2 resource base 30d0 size 4 align 2 gran 2 limit 30d3 flags 60000100 index 14
   PCI: 00:1f.2 resource base 30c8 size 8 align 3 gran 3 limit 30cf flags 60000100 index 18
   PCI: 00:1f.2 resource base 30d4 size 4 align 2 gran 2 limit 30d7 flags 60000100 index 1c
   PCI: 00:1f.2 resource base 30a0 size 20 align 5 gran 5 limit 30bf flags 60000100 index 20
   PCI: 00:1f.2 resource base 3e304000 size 800 align 12 gran 11 limit 3e3047ff flags 60000200 index 24
   PCI: 00:1f.3
   PCI: 00:1f.3 resource base 3e307000 size 100 align 12 gran 8 limit 3e3070ff flags 60000201 index 10
   PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
Done allocating resources.
BS: BS_DEV_RESOURCES run times (exec / console): 23 / 114 ms
Enabling resources...
PCI: 00:00.0 subsystem <- 1179/ff1e
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 001b
PCI: 00:01.0 cmd <- 07
PCI: 00:1a.0 subsystem <- 1179/ff1e
PCI: 00:1a.0 cmd <- 01
PCI: 00:1a.1 subsystem <- 1179/ff1e
PCI: 00:1a.1 cmd <- 01
PCI: 00:1a.7 subsystem <- 1179/ff1e
PCI: 00:1a.7 cmd <- 102
PCI: 00:1b.0 subsystem <- 1179/ff1e
PCI: 00:1b.0 cmd <- 102
PCI: 00:1c.0 bridge ctrl <- 0013
PCI: 00:1c.0 subsystem <- 1179/ff1e
PCI: 00:1c.0 cmd <- 107
PCI: 00:1c.4 bridge ctrl <- 0013
PCI: 00:1c.4 subsystem <- 1179/ff1e
PCI: 00:1c.4 cmd <- 100
PCI: 00:1d.0 subsystem <- 1179/ff1e
PCI: 00:1d.0 cmd <- 01
PCI: 00:1d.1 subsystem <- 1179/ff1e
PCI: 00:1d.1 cmd <- 01
PCI: 00:1d.2 subsystem <- 1179/ff1e
PCI: 00:1d.2 cmd <- 01
PCI: 00:1d.7 subsystem <- 1179/ff1e
PCI: 00:1d.7 cmd <- 102
PCI: 00:1e.0 bridge ctrl <- 0013
PCI: 00:1e.0 subsystem <- 1179/ff1e
PCI: 00:1e.0 cmd <- 106
PCI: 00:1f.0 subsystem <- 1179/ff1e
PCI: 00:1f.0 cmd <- 107
PCI: 00:1f.2 subsystem <- 1179/ff1e
PCI: 00:1f.2 cmd <- 03
PCI: 00:1f.3 subsystem <- 1179/ff1e
PCI: 00:1f.3 cmd <- 103
PCI: 01:00.0 cmd <- 03
PCI: 01:00.1 cmd <- 02
PCI: 02:00.0 cmd <- 03
PCI: 04:06.0 cmd <- 02
PCI: 04:06.1 cmd <- 06
PCI: 04:06.2 cmd <- 06
PCI: 04:06.3 cmd <- 06
PCI: 04:06.4 cmd <- 06
done.
BS: BS_DEV_ENABLE run times (exec / console): 0 / 7 ms
Initializing devices...
CPU_CLUSTER: 0 init
FMAP: area COREBOOT found @ 20200 (1965568 bytes)
CBFS: Found 'cpu_microcode_blob.bin' @0x10d00 size 0x21000 in mcache @0x3dbfd0ac
microcode: sig=0x10676 pf=0x80 revision=0x0
microcode: updated to revision 0x60f date=2010-09-29
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x000000003dc00000 size 0x3db40000 type 6
0x000000003dc00000 - 0x0000000040000000 size 0x02400000 type 0
0x0000000040000000 - 0x0000000050000000 size 0x10000000 type 1
0x0000000050000000 - 0x0000000100000000 size 0xb0000000 type 0
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
call enable_fixed_mtrr()
CPU physical address size: 36 bits
MTRR: default type WB/UC MTRR counts: 6/4.
MTRR: UC selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x0000000fc0000000 type 6
MTRR: 1 base 0x000000003dc00000 mask 0x0000000fffc00000 type 0
MTRR: 2 base 0x000000003e000000 mask 0x0000000ffe000000 type 0
MTRR: 3 base 0x0000000040000000 mask 0x0000000ff0000000 type 1

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

CPU has 2 cores.
Setting up SMI for CPU
Will perform SMM setup.
CPU: Intel(R) Core(TM)2 Duo CPU     P8400  @ 2.26GHz.
Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
Processing 16 relocs. Offset value of 0x00030000
Attempting to start 1 APs
Waiting for 10ms after sending INIT.
Waiting for 1st SIPI to complete...AP: slot 1 apic_id 1, MCU rev: 0x0000060f
done.
Waiting for 2nd SIPI to complete...done.
smm_setup_relocation_handler: enter
smm_setup_relocation_handler: exit
smm_stub_place_stacks: cpus: 2 : stack space: needed -> 800
smm_stub_place_stacks: exit, stack_top 0x3de00800
Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a0 memsize: 0x1a0
Processing 11 relocs. Offset value of 0x00038000
smm_module_setup_stub: stack_end = 0x3de00000
smm_module_setup_stub: stack_top = 0x3de00800
smm_module_setup_stub: stack_size = 0x400
smm_module_setup_stub: runtime.start32_offset = 0x4c
smm_module_setup_stub: runtime.smm_size = 0x10000
SMM Module: stub loaded at 0x00038000. Will call 0x3dba6a23
Installing permanent SMM handler to 0x3de00000
smm_load_module: total_smm_space_needed 5280, available -> 100000
Loading module at 0x3defc000 with entry 0x3defc071. filesize: 0x670 memsize: 0x4680
Processing 28 relocs. Offset value of 0x3defc000
smm_load_module: smram_start: 0x0x3de00000
smm_load_module: smram_end: 0x3df00000
smm_load_module: stack_top: 0x3de00800
smm_load_module: handler start 0x3defc071
smm_load_module: handler_size 5100
smm_load_module: fxsave_area 0x3deffc00
smm_load_module: fxsave_size 400
smm_load_module: CONFIG_MSEG_SIZE 0x0
smm_load_module: CONFIG_BIOS_RESOURCE_LIST_SIZE 0x0
smm_load_module: handler_mod_params.smbase = 0x3de00000
smm_load_module: per_cpu_save_state_size = 0x400
smm_load_module: num_cpus = 0x2
smm_load_module: total_save_state_size = 0x800
smm_load_module: cpu0 entry: 0x3deec000
smm_create_map: cpus allowed in one segment 30
smm_create_map: min # of segments needed 1
CPU 0x0
    smbase 3deec000  entry 3def4000
           ss_start 3defbc00  code_end 3def41a0
CPU 0x1
    smbase 3deebc00  entry 3def3c00
           ss_start 3defb800  code_end 3def3da0
smm_stub_place_stacks: cpus: 2 : stack space: needed -> 800
smm_stub_place_stacks: exit, stack_top 0x3de00800
Loading module at 0x3def4000 with entry 0x3def4000. filesize: 0x1a0 memsize: 0x1a0
Processing 11 relocs. Offset value of 0x3def4000
smm_place_entry_code: smbase 3deebc00, stack_top 3de00800
SMM Module: placing smm entry code at 3def3c00,  cpu # 0x1
smm_place_entry_code: copying from 3def4000 to 3def3c00 0x1a0 bytes
smm_module_setup_stub: stack_end = 0x3de00000
smm_module_setup_stub: stack_top = 0x3de00800
smm_module_setup_stub: stack_size = 0x400
smm_module_setup_stub: runtime.start32_offset = 0x4c
smm_module_setup_stub: runtime.smm_size = 0x100000
SMM Module: stub loaded at 0x3def4000. Will call 0x3defc071
Initializing southbridge SMI... ... pmbase = 0x0500

smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x3deec000, cpu = 0
In relocation handler: cpu 0
New SMBASE=0x3deec000
SMM revision: 0x00030100
SMRR not enabled, skip writing SMRR...
Relocation complete.
VMX status: enabled
VMX status: enabled
smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x3deebc00, cpu = 1
In relocation handler: cpu 1
New SMBASE=0x3deebc00
SMM revision: 0x00030100
Writing SMRR. base = 0x3de00000, mask=0xffe00800
Relocation complete.
Initializing CPU #0
CPU: vendor Intel device 10676
CPU: family 06, model 17, stepping 06
CPU: Intel(R) Core(TM)2 Duo CPU     P8400  @ 2.26GHz.
Setting up local APIC...
 apic_id: 0x0 done.
writing P-State 1: 0, 0,  6, 0x17, 15000; encoded: 0x0617
writing P-State 1: 0, 0,  6, 0x17, 15000; encoded: 0x0617
writing P-State 1: 0, 0,  6, 0x17, 15000; encoded: 0x0617
writing P-State 1: 0, 0,  6, 0x17, 15000; encoded: 0x0617
writing P-State 1: 0, 0,  6, 0x17, 15000; encoded: 0x0617
writing P-State 0: 0, 1,  8, 0x20, 35000; encoded: 0x4820
CPU #0 initialized
Initializing CPU #1
CPU: vendor Intel device 10676
CPU: family 06, model 17, stepping 06
CPU: Intel(R) Core(TM)2 Duo CPU     P8400  @ 2.26GHz.
Setting up local APIC...
 apic_id: 0x1 done.
writing P-State 2: 0, 0,  6, 0x17, 15000; encoded: 0x0617
writing P-State 2: 0, 0,  6, 0x17, 15000; encoded: 0x0617
writing P-State 2: 0, 0,  6, 0x17, 15000; encoded: 0x0617
writing P-State 2: 0, 0,  6, 0x17, 15000; encoded: 0x0617
writing P-State 2: 0, 0,  6, 0x17, 15000; encoded: 0x0617
writing P-State 1: 0, 1,  8, 0x20, 35000; encoded: 0x4820
CPU #1 initialized
bsp_do_flight_plan done after 22 msecs.
CPU 1 going down...
Initializing southbridge SMI... ... pmbase = 0x0500

SMI_STS: 
PM1_STS: 
PM1_EN: 100
GPE0_STS: GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 
ALT_GP_SMI_STS: GPI13 GPI11 GPI10 GPI9 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 
TCO_STS: 
Locking SMM.
CPU_CLUSTER: 0 init finished in 70 msecs
DOMAIN: 0000 init
DOMAIN: 0000 init finished in 0 msecs
PCI: 00:00.0 init
PCI: 00:00.0 init finished in 0 msecs
PCI: 00:1a.0 init
PCI: 00:1a.0 init finished in 0 msecs
PCI: 00:1a.1 init
PCI: 00:1a.1 init finished in 0 msecs
PCI: 00:1a.7 init
EHCI: Setting up controller.. done.
PCI: 00:1a.7 init finished in 0 msecs
PCI: 00:1b.0 init
Azalia: base = 0x3e300000
Azalia: codec_mask = 03
Azalia: Initializing codec #1
Azalia: codec viddid: 11c11040
Azalia: No verb!
Azalia: Initializing codec #0
Azalia: codec viddid: 10ec0268
Azalia: No verb!
PCI: 00:1b.0 init finished in 3 msecs
PCI: 00:1c.0 init
Initializing ICH9 PCIe root port.
PCI: 00:1c.0 init finished in 0 msecs
PCI: 00:1c.4 init
Initializing ICH9 PCIe root port.
PCI: 00:1c.4 init finished in 0 msecs
PCI: 00:1d.0 init
PCI: 00:1d.0 init finished in 0 msecs
PCI: 00:1d.1 init
PCI: 00:1d.1 init finished in 0 msecs
PCI: 00:1d.2 init
PCI: 00:1d.2 init finished in 0 msecs
PCI: 00:1d.7 init
EHCI: Setting up controller.. done.
PCI: 00:1d.7 init finished in 0 msecs
PCI: 00:1e.0 init
PCI: 00:1e.0 init finished in 0 msecs
PCI: 00:1f.0 init
i82801ix: lpc_init
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x02
IOAPIC: Dumping registers
  reg 0x0000: 0x02000000
  reg 0x0001: 0x00170020
  reg 0x0002: 0x00170020
IOAPIC: 24 interrupts
IOAPIC: Enabling interrupts on FSB
IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
Set power on after power failure.
NMI sources disabled.
rtc_failed = 0x0
RTC Init
apm_control: Disabling ACPI.
APMC done.
PCI: 00:1f.0 init finished in 8 msecs
PCI: 00:1f.2 init
i82801ix_sata: initializing...
SATA controller in AHCI mode.
ABAR: 0x3e304000
PCI: 00:1f.2 init finished in 0 msecs
PCI: 00:1f.3 init
PCI: 00:1f.3 init finished in 0 msecs
PCI: 01:00.0 init
PCI: 01:00.0 init finished in 0 msecs
PCI: 01:00.1 init
PCI: 01:00.1 init finished in 0 msecs
PCI: 02:00.0 init
PCI: 02:00.0 init finished in 0 msecs
PCI: 04:06.0 init
PCI: 04:06.0 init finished in 0 msecs
PCI: 04:06.1 init
PCI: 04:06.1 init finished in 0 msecs
PCI: 04:06.2 init
PCI: 04:06.2 init finished in 0 msecs
PCI: 04:06.3 init
PCI: 04:06.3 init finished in 0 msecs
PCI: 04:06.4 init
PCI: 04:06.4 init finished in 0 msecs
Devices initialized
Show all devs... After init.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
DOMAIN: 0000: enabled 1
APIC: 00: enabled 1
APIC: acac: enabled 0
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 0
PCI: 00:02.1: enabled 0
PCI: 00:03.0: enabled 0
PCI: 00:03.1: enabled 0
PCI: 00:03.2: enabled 0
PCI: 00:03.3: enabled 0
PCI: 00:19.0: enabled 0
PCI: 00:1a.0: enabled 1
PCI: 00:1a.1: enabled 1
PCI: 00:1a.2: enabled 0
PCI: 00:1a.7: enabled 1
PCI: 00:1b.0: enabled 1
PCI: 00:1c.0: enabled 1
PCI: 00:1c.1: enabled 0
PCI: 00:1c.2: enabled 0
PCI: 00:1c.3: enabled 0
PCI: 00:1c.4: enabled 1
PCI: 00:1c.5: enabled 0
PCI: 00:1d.0: enabled 1
PCI: 00:1d.1: enabled 1
PCI: 00:1d.2: enabled 1
PCI: 00:1d.7: enabled 1
PCI: 00:1e.0: enabled 1
PCI: 00:1f.0: enabled 1
PCI: 00:1f.2: enabled 1
PCI: 00:1f.3: enabled 1
PCI: 00:1f.5: enabled 0
PCI: 00:1f.6: enabled 0
PCI: 01:00.0: enabled 1
PCI: 01:00.1: enabled 1
PCI: 02:00.0: enabled 1
PCI: 04:06.0: enabled 1
PCI: 04:06.1: enabled 1
PCI: 04:06.2: enabled 1
PCI: 04:06.3: enabled 1
PCI: 04:06.4: enabled 1
APIC: 01: enabled 1
BS: BS_DEV_INIT run times (exec / console): 34 / 63 ms
Finalize devices...
Devices finalized
CBFS: Found 'fallback/dsdt.aml' @0x471c0 size 0x2573 in mcache @0x3dbfd198
CBFS: 'fallback/slic' not found.
ACPI: Writing ACPI tables at 3db55000.
ACPI:    * FACS
ACPI:    * DSDT
ACPI:    * FADT
ACPI: added table 1/32, length now 40
ACPI:     * SSDT
Found 1 CPU(s) with 2 core(s) each.
clocks between 800 and 2400 MHz.
adding 4 P-States between busratio 6 and 9, incl. P0
PSS: 2267MHz power 35000 control 0x927 status 0x927
PSS: 2266MHz power 35000 control 0x4820 status 0x4820
PSS: 1600MHz power 15000 control 0x617 status 0x617
PSS: 800MHz power 12000 control 0x8611 status 0x8611
clocks between 800 and 2400 MHz.
adding 4 P-States between busratio 6 and 9, incl. P0
PSS: 2267MHz power 35000 control 0x927 status 0x927
PSS: 2266MHz power 35000 control 0x4820 status 0x4820
PSS: 1600MHz power 15000 control 0x617 status 0x617
PSS: 800MHz power 12000 control 0x8611 status 0x8611
Generating ACPI PIRQ entries
ACPI_PIRQ_GEN: PCI: 00:01.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1a.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1a.1: pin=1 pirq=1
ACPI_PIRQ_GEN: PCI: 00:1a.7: pin=2 pirq=2
ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1d.1: pin=1 pirq=1
ACPI_PIRQ_GEN: PCI: 00:1d.2: pin=2 pirq=2
ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=1 pirq=1
ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=2 pirq=2
CBFS: Found 'pci1002,95c4.rom' @0x49c40 size 0xfe00 in mcache @0x3dbfd1ec
In CBFS, ROM address for PCI: 01:00.0 = 0xffe69e6c
PCI expansion ROM, signature 0xaa55, INIT size 0xfe00, data ptr 0x01b8
PCI ROM image, vendor ID 1002, device ID 95c4,
PCI ROM image, Class Code 030000, Code Type 00
PCI: 01:00.0: Missing ACPI scope
ACPI: added table 2/32, length now 44
ACPI:    * MCFG
ACPI: added table 3/32, length now 48
ACPI:    * MADT
ACPI: added table 4/32, length now 52
current = 3db57ff0
ACPI:     * DMAR
ACPI: added table 5/32, length now 56
current = 3db58050
ACPI:    * HPET
ACPI: added table 6/32, length now 60
CBFS: Found 'pci1002,95c4.rom' @0x49c40 size 0xfe00 in mcache @0x3dbfd1ec
In CBFS, ROM address for PCI: 01:00.0 = 0xffe69e6c
PCI expansion ROM, signature 0xaa55, INIT size 0xfe00, data ptr 0x01b8
PCI ROM image, vendor ID 1002, device ID 95c4,
PCI ROM image, Class Code 030000, Code Type 00
           Copying VBIOS image from 0xffe69e6c
ACPI:    * VFCT at 3db58090
ACPI: added table 7/32, length now 64
ACPI: done.
ACPI tables: 77568 bytes.
smbios_write_tables: 3db54000
SMBIOS firmware version is set to coreboot_version: '4.13-3666-gef04b0bf9e'
SMBIOS tables: 508 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 3227
Writing coreboot table at 0x3db79000
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000a0000-00000000000fffff: RESERVED
 3. 0000000000100000-000000003db53fff: RAM
 4. 000000003db54000-000000003db91fff: CONFIGURATION TABLES
 5. 000000003db92000-000000003dbcdfff: RAMSTAGE
 6. 000000003dbce000-000000003dbfffff: CONFIGURATION TABLES
 7. 000000003dc00000-000000003dffffff: RESERVED
 8. 00000000f0000000-00000000f3ffffff: RESERVED
Wrote coreboot table at: 0x3db79000, 0x31c bytes, checksum f608
coreboot table: 820 bytes.
IMD ROOT    0. 0x3dbff000 0x00001000
IMD SMALL   1. 0x3dbfe000 0x00001000
RO MCACHE   2. 0x3dbfd000 0x00000320
CONSOLE     3. 0x3dbdd000 0x00020000
TIME STAMP  4. 0x3dbdc000 0x00000910
ROMSTG STCK 5. 0x3dbdb000 0x00001000
AFTER CAR   6. 0x3dbce000 0x0000d000
RAMSTAGE    7. 0x3db91000 0x0003d000
SMM BACKUP  8. 0x3db81000 0x00010000
COREBOOT    9. 0x3db79000 0x00008000
ACPI       10. 0x3db55000 0x00024000
SMBIOS     11. 0x3db54000 0x00000800
IMD small region:
  IMD ROOT    0. 0x3dbfec00 0x00000400
  FMAP        1. 0x3dbfeb20 0x000000e0
  ROMSTAGE    2. 0x3dbfeb00 0x00000004
  ACPI GNVS   3. 0x3dbfea00 0x00000100
BS: BS_WRITE_TABLES run times (exec / console): 40 / 21 ms
CBFS: Found 'fallback/payload' @0x61c40 size 0x10e46 in mcache @0x3dbfd25c
Checking segment from ROM address 0xffe81e6c
Payload being loaded at below 1MiB without region being marked as RAM usable.
Checking segment from ROM address 0xffe81e88
Loading segment from ROM address 0xffe81e6c
  code (compression=1)
  New segment dstaddr 0x000dffa0 memsize 0x20060 srcaddr 0xffe81ea4 filesize 0x10e0e
Loading Segment: addr: 0x000dffa0 memsz: 0x0000000000020060 filesz: 0x0000000000010e0e
using LZMA
[ 0x000dffa0, 00100000, 0x00100000) <- ffe81ea4
Loading segment from ROM address 0xffe81e88
  Entry Point 0x000fd265
Loaded segments
BS: BS_PAYLOAD_LOAD run times (exec / console): 38 / 3 ms
ICH-NM10-PCH: watchdog disabled
Jumping to boot code at 0x000fd265(0x3db79000)
CPU0: stack: 0x3dbc1000 - 0x3dbc2000, lowest used address 0x3dbc183c, stack used: 1988 bytes
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