Nick: anonymous E-mail: none Board: denverton Contents: coreboot-4.13-3160-g67d099a7f2 Mon Apr 12 17:26:52 UTC 2021 bootblock starting (log level: 7)... FSP TempRamInit successful... FMAP: Found "FLASH" version 1.1 at 0xf10000. FMAP: base = 0xff000000 size = 0x1000000 #areas = 4 FMAP: area COREBOOT found @ f10200 (982528 bytes) CBFS: Found 'fallback/romstage' @0x80 size 0x7f90 BS: bootblock times (exec / console): total (unknown) / 30 ms coreboot-4.13-3160-g67d099a7f2 Mon Apr 12 17:26:52 UTC 2021 romstage starting (log level: 7)... FSP TempRamInit was successful... GPIO table: 0xfff17440, entry num: 0x98! Changing GpioPad PID: c2 Offset: 0x400 PadModeP1: 0 P2: 1 R: 0x45000200 Fx45000600 ! Changing GpioPad PID: c2 Offset: 0x408 PadModeP1: 0 P2: 1 R: 0x45000200 Fx45000600 ! Changing GpioPad PID: c2 Offset: 0x410 PadModeP1: 0 P2: 2 R: 0x45000200 Fx45000a00 ! Changing GpioPad PID: c2 Offset: 0x418 PadModeP1: 0 P2: 2 R: 0x45000200 Fx45000a00 ! Changing GpioPad PID: c2 Offset: 0x420 PadModeP1: 0 P2: 2 R: 0x45000200 Fx45000a00 ! Changing GpioPad PID: c2 Offset: 0x428 PadModeP1: 0 P2: 2 R: 0x45000200 Fx45000a00 ! Changing GpioPad PID: c2 Offset: 0x430 PadModeP1: 0 P2: 2 R: 0x45000200 Fx45000a00 ! Changing GpioPad PID: c2 Offset: 0x438 PadModeP1: 0 P2: 2 R: 0x45000200 Fx45000a00 ! Changing GpioPad PID: c2 Offset: 0x470 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! Changing GpioPad PID: c2 Offset: 0x478 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! Changing GpioPad PID: c2 Offset: 0x480 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! Changing GpioPad PID: c2 Offset: 0x488 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! Changing GpioPad PID: c2 Offset: 0x490 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! Changing GpioPad PID: c2 Offset: 0x498 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! Changing GpioPad PID: c2 Offset: 0x4a0 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! Changing GpioPad PID: c2 Offset: 0x4a8 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! Changing GpioPad PID: c2 Offset: 0x4b0 PadModeP1: 0 P2: 2 R: 0x45000300 Fx05000b00 ! Changing GpioPad PID: c2 Offset: 0x4d8 PadModeP1: 0 P2: 3 R: 0x45000200 Fx45000e00 ! Changing GpioPad PID: c2 Offset: 0x500 PadModeP1: 1 P2: 0 R: 0x45000602 Fx45000202 ! Changing GpioPad PID: c2 Offset: 0x508 PadModeP1: 0 P2: 1 R: 0x45000200 Fx45000600 ! Changing GpioPad PID: c2 Offset: 0x510 PadModeP1: 0 P2: 1 R: 0x45000200 Fx45000600 ! Changing GpioPad PID: c5 Offset: 0x498 PadModeP1: 2 P2: 3 R: 0x45000a02 Fx05000e02 ! Changing GpioPad PID: c5 Offset: 0x4a0 PadModeP1: 3 P2: 0 R: 0x45000e00 Fx45040100 ! Changing GpioPad PID: c5 Offset: 0x4a8 PadModeP1: 1 P2: 0 R: 0x45000602 Fx45020102 ! Changing GpioPad PID: c5 Offset: 0x4b0 PadModeP1: 1 P2: 3 R: 0x45000602 Fx45000e02 ! Changing GpioPad PID: c5 Offset: 0x4c8 PadModeP1: 0 P2: 3 R: 0x45000300 Fx05000f00 ! Changing GpioPad PID: c5 Offset: 0x4d0 PadModeP1: 0 P2: 3 R: 0x45000300 Fx05000f00 ! Changing GpioPad PID: c5 Offset: 0x538 PadModeP1: 0 P2: 1 R: 0x45000200 Fx45000600 ! Changing GpioPad PID: c5 Offset: 0x540 PadModeP1: 0 P2: 1 R: 0x45000200 Fx45000600 ! Changing GpioPad PID: c5 Offset: 0x560 PadModeP1: 0 P2: 1 R: 0x45000200 Fx45000600 ! Changing GpioPad PID: c5 Offset: 0x568 PadModeP1: 0 P2: 3 R: 0x45000200 Fx45000e00 ! Changing GpioPad PID: c5 Offset: 0x570 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x578 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x580 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x5c8 PadModeP1: 0 P2: 3 R: 0x45000300 Fx45000f00 ! Changing GpioPad PID: c5 Offset: 0x5d0 PadModeP1: 0 P2: 3 R: 0x45000300 Fx45000f00 ! Changing GpioPad PID: c5 Offset: 0x610 PadModeP1: 1 P2: 0 R: 0x45000602 Fx45000102 ! Changing GpioPad PID: c5 Offset: 0x618 PadModeP1: 1 P2: 0 R: 0x45000600 Fx45000100 ! Changing GpioPad PID: c5 Offset: 0x620 PadModeP1: 0 P2: 0 R: 0x44000300 Fx44000000 ! Changing GpioPad PID: c5 Offset: 0x628 PadModeP1: 0 P2: 0 R: 0x44000300 Fx44000100 ! Changing GpioPad PID: c5 Offset: 0x630 PadModeP1: 0 P2: 0 R: 0x44000300 Fx44000100 ! Changing GpioPad PID: c5 Offset: 0x648 PadModeP1: 0 P2: 1 R: 0x45000200 Fx45000600 ! Changing GpioPad PID: c5 Offset: 0x688 PadModeP1: 1 P2: 0 R: 0x44000600 Fx44000100 ! Changing GpioPad PID: c5 Offset: 0x710 PadModeP1: 1 P2: 0 R: 0x45000700 Fx45000100 ! Changing GpioPad PID: c5 Offset: 0x718 PadModeP1: 1 P2: 2 R: 0x45000702 Fx45000b02 ! Changing GpioPad PID: c5 Offset: 0x728 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x730 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x738 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x740 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x748 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x750 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x758 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x760 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x768 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x770 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x778 PadModeP1: 0 P2: 1 R: 0x45000300 Fx45000700 ! Changing GpioPad PID: c5 Offset: 0x780 PadModeP1: 0 P2: 0 R: 0x45000200 Fx45000200 ! TCO base address set to 0x400! FMAP: area COREBOOT found @ f10200 (982528 bytes) CBFS: Found 'fspm.bin' @0x21dc0 size 0x90000 FMAP: area RW_MRC_CACHE found @ f00000 (65536 bytes) MRC: no data in 'RW_MRC_CACHE' ============= FSP Spec v2.0 Header Revision v3 (DNV-FSP0 v0.0.1.11) ============= Fsp BootFirmwareVolumeBase - 0xFFF32000 Fsp BootFirmwareVolumeSize - 0x90000 Fsp TemporaryRamBase - 0xFEF60000 Fsp TemporaryRamSize - 0x4FF00 Fsp PeiTemporaryRamBase - 0xFEF60000 Fsp PeiTemporaryRamSize - 0x27F80 Fsp StackBase - 0xFEF87F80 Fsp StackSize - 0x27F80 Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000FFF32000, size is 0x00090000, handle is 0x0 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389 Loading PEIM at 0x000FFF3E588 EntryPoint=0x000FFF3E668 Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480 Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1 Install PPI: 4D8B155B-C059-4C8F-8926-06FD4331DB8A Install PPI: A60C6B59-E459-425D-9C69-0BCC9CB27D81 Loading PEIM at 0x000FFF42654 EntryPoint=0x000FFF42734 FSP BUILD ID : 0015.D99 Initialise SYSTEM_CONFIGURATION Initialise PCH_SETUP CustomerRevision: version xxx Updating Policies with Memory Init UPD PCDs... 0x03 : PcdInterleaveMode 0x00 : PcdHalfWidthEnable 0x01 : PcdTclIdle 0x00 : PcdMemoryPreservation 0x00 : PcdMemoryThermalThrottling Install PPI: 70CEA1D9-0FEE-4E68-8F26-5FCD6D092FCC Build PCH_SETUP HOB at 0xFEF61350(0x16C bytes) Build SYSTEM_CONFIGURATION HOB at 0xFEF614D8(0x650 bytes) Build PLATFORM_INFO_HOB HOB at 0xFEF61B40(0xC6 bytes) Install PPI: 2AB86EF5-ECB5-4134-B556-3854CA1FE1B4 Loading PEIM at 0x000FFF45DD4 EntryPoint=0x000FFF45EB4 Force an S5 exit path. Install PPI: D14319E2-407A-9580-8DE5-51A8FFC6D7D7 Install PPI: EE0EA811-FBD9-4777-B95A-BA4F71101F74 Loading PEIM at 0x000FFF49484 EntryPoint=0x000FFF49554 FspInitPreMemEntryPoint() - Start Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56 Install PPI: EF398D58-9DFD-4103-BF94-78C6F4FE712F Setting BootMode to BOOT_WITH_FULL_CONFIGURATION [SPS] (ICC) MeFiaMuxConfigGet [HECI] Resetting HECI interface (CSR: 80000000/80000008, MEFS1:000F0352) [HECI] Send msg: 80140008 00040000 ... [HECI] Got msg: 80240008 00040000 ... [SPS] (ICC) MeFiaMuxConfigGet: no FIA Mux configuration in ME Flash [SPS] (ICC) MeFiaMuxConfigGet: Softstraps Configuration will be used [SPS] (ICC) MeFiaMuxConfigGet: Received number of Lanes allowed = 0xC [SPS] (ICC) MeFiaMuxConfigGet: Received FIA Mux Lanes Configuration = 0xAA55550000 [SPS] (ICC) MeFiaMuxConfigGet: Received SATA Lanes Configuration = 0x155555 [SPS] (ICC) MeFiaMuxConfigGet: Received PCIE Root Ports Configuration = 0xFFFF0000F0 [SPS] (ICC) MeFiaMuxConfigGet: End - Success FiaMuxCreatePolicyDefaults() MeFiaMuxConfigGet status = Success, MuxConfiguration 0xAA55550000, NumLanesAllowed 0xC SataLaneConfiguration 0x155555, PcieRootPortsConfiguration 0xFFFF0000F0 UpdatePeiFiaMuxPolicy SkuNumLanesAllowed: 0xC FiaMuxConfig.MuxConfiguration: 0xAA55550000 FiaMuxConfig.SataLaneConfiguration: 0x155555 FiaMuxConfig.PcieRootPortsConfiguration: 0xFFFF0000F0 FiaMuxConfigRequest.MuxConfiguration: 0xAA55550000 FiaMuxConfigRequest.SataLaneConfiguration: 0x155555 FiaMuxConfigRequest.PcieRootPortsConfiguration: 0xFFFF0000F0 FIA Mux Policy ready!! Install PPI: 43CC4396-68AF-42DA-A905-4AF2EDEC2847 FIA MUX PEI Policy Initialization Done Install PPI: AEBFFA01-7EDC-49FF-8D88-CB848C5E8670 Silicon PEI Policy Initialization Done policy 80400042 ------------------ PCH SATA Config 0 Policy Override ------------------ Sata controller 0 is not on FIA config ------------------ PCH SATA Config 1 Policy Override ------------------ FIA: SATA controller 1 is enabled FIA Mux Lane 0xC config is 0x1 Disabling port: 0x0 FIA Mux Lane 0xD config is 0x1 Disabling port: 0x1 FIA Mux Lane 0xE config is 0x1 Disabling port: 0x2 FIA Mux Lane 0xF config is 0x1 Disabling port: 0x3 FIA Mux Lane 0x10 config is 0x2 FIA Mux Lane 0x11 config is 0x2 FIA Mux Lane 0x12 config is 0x2 FIA Mux Lane 0x13 config is 0x2 ------------------ PCH USB Config Policy Override ------------------ None FIA lanes are assigned to XHCI controller PCH_PWRON: NvmSafeRegister = 1 PCH_PWRON: GpioSafeRegister = 0 PCH_PWRON: DmiSafeRegister = 1 PCH_PWRON: SmbusSafeRegister = 0 PCH_PWRON: RtcSafeRegister = 0 PCH_PWRON: ItssSafeRegister = 0 PCH_PWRON: P2sbSafeRegister = 1 PCH_PWRON: PsthSafeRegister = 1 PCH_PWRON: HostPmSafeRegister = 1 PCH_PWRON: ScsSafeRegister = 1 PCH_PWRON: ThermalSafeRegister = 1 PCH_PWRON: PcieSafeRegister = 1 PCH_PWRON: PsfSafeRegister = 1 PCH_PWRON: XhciSafeSettings = 0 PCH_PWRON: XdciSafeSettings = 1 PCH_PWRON: SataPmSafeRegister = 0 PCH_PWRON: FiaSafeRegister = 0 PCH_PWRON: LpcSafeRegister = 0 PCH_PWRON: IshSafeRegister = 1 PCH_PWRON: HdaSafeRegister = 1 PCH_PWRON: DciSafeRegister = 0 PCH_PWRON: CSI2SafeRegister = 1 ------------------------ PCH Print Platform Protocol Start ------------------------ Revision= C AcpiBase= 1800 MctpBroadcastCycle= 0 ------------------ PCH General Config ------------------ SubSystemVendorId= 8086 SubSystemId= 7270 Crid= 0 ------------------ PCH SATA Config 0 ----------------- Enable= 0 SataMode= 0 PortSettings[0] Enabled= 1 PortSettings[0] HotPlug= 1 PortSettings[0] InterlockSw= 0 PortSettings[0] External= 0 PortSettings[0] SpinUp= 0 PortSettings[0] SolidStateDrive= 0 PortSettings[0] DevSlp= 0 PortSettings[0] EnableDitoConfig= 0 PortSettings[0] DmVal= F PortSettings[0] DitoVal= 271 PortSettings[0] ZpOdd= 0 PortSettings[0] HsioRxGen1EqBoostMagEnable= 0 PortSettings[0] HsioRxGen1EqBoostMag= 0 PortSettings[0] HsioRxGen2EqBoostMagEnable= 0 PortSettings[0] HsioRxGen2EqBoostMag= 0 PortSettings[0] HsioRxGen3EqBoostMagEnable= 0 PortSettings[0] HsioRxGen3EqBoostMag= 0 PortSettings[0] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[0] HsioTxGen1DownscaleAmp= 0 PortSettings[0] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[0] HsioTxGen2DownscaleAmp= 0 PortSettings[0] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[0] HsioTxGen3DownscaleAmp= 0 PortSettings[0] HsioTxGen1DeEmphEnable= 0 PortSettings[0] HsioTxGen1DeEmph= 0 PortSettings[0] HsioTxGen2DeEmphEnable= 0 PortSettings[0] HsioTxGen2DeEmph= 0 PortSettings[0] HsioTxGen3DeEmphEnable= 0 PortSettings[0] HsioTxGen3DeEmph= 0 PortSettings[1] Enabled= 1 PortSettings[1] HotPlug= 1 PortSettings[1] InterlockSw= 0 PortSettings[1] External= 0 PortSettings[1] SpinUp= 0 PortSettings[1] SolidStateDrive= 0 PortSettings[1] DevSlp= 0 PortSettings[1] EnableDitoConfig= 0 PortSettings[1] DmVal= F PortSettings[1] DitoVal= 271 PortSettings[1] ZpOdd= 0 PortSettings[1] HsioRxGen1EqBoostMagEnable= 0 PortSettings[1] HsioRxGen1EqBoostMag= 0 PortSettings[1] HsioRxGen2EqBoostMagEnable= 0 PortSettings[1] HsioRxGen2EqBoostMag= 0 PortSettings[1] HsioRxGen3EqBoostMagEnable= 0 PortSettings[1] HsioRxGen3EqBoostMag= 0 PortSettings[1] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[1] HsioTxGen1DownscaleAmp= 0 PortSettings[1] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[1] HsioTxGen2DownscaleAmp= 0 PortSettings[1] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[1] HsioTxGen3DownscaleAmp= 0 PortSettings[1] HsioTxGen1DeEmphEnable= 0 PortSettings[1] HsioTxGen1DeEmph= 0 PortSettings[1] HsioTxGen2DeEmphEnable= 0 PortSettings[1] HsioTxGen2DeEmph= 0 PortSettings[1] HsioTxGen3DeEmphEnable= 0 PortSettings[1] HsioTxGen3DeEmph= 0 PortSettings[2] Enabled= 1 PortSettings[2] HotPlug= 1 PortSettings[2] InterlockSw= 0 PortSettings[2] External= 0 PortSettings[2] SpinUp= 0 PortSettings[2] SolidStateDrive= 0 PortSettings[2] DevSlp= 0 PortSettings[2] EnableDitoConfig= 0 PortSettings[2] DmVal= F PortSettings[2] DitoVal= 271 PortSettings[2] ZpOdd= 0 PortSettings[2] HsioRxGen1EqBoostMagEnable= 0 PortSettings[2] HsioRxGen1EqBoostMag= 0 PortSettings[2] HsioRxGen2EqBoostMagEnable= 0 PortSettings[2] HsioRxGen2EqBoostMag= 0 PortSettings[2] HsioRxGen3EqBoostMagEnable= 0 PortSettings[2] HsioRxGen3EqBoostMag= 0 PortSettings[2] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[2] HsioTxGen1DownscaleAmp= 0 PortSettings[2] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[2] HsioTxGen2DownscaleAmp= 0 PortSettings[2] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[2] HsioTxGen3DownscaleAmp= 0 PortSettings[2] HsioTxGen1DeEmphEnable= 0 PortSettings[2] HsioTxGen1DeEmph= 0 PortSettings[2] HsioTxGen2DeEmphEnable= 0 PortSettings[2] HsioTxGen2DeEmph= 0 PortSettings[2] HsioTxGen3DeEmphEnable= 0 PortSettings[2] HsioTxGen3DeEmph= 0 PortSettings[3] Enabled= 1 PortSettings[3] HotPlug= 1 PortSettings[3] InterlockSw= 0 PortSettings[3] External= 0 PortSettings[3] SpinUp= 0 PortSettings[3] SolidStateDrive= 0 PortSettings[3] DevSlp= 0 PortSettings[3] EnableDitoConfig= 0 PortSettings[3] DmVal= F PortSettings[3] DitoVal= 271 PortSettings[3] ZpOdd= 0 PortSettings[3] HsioRxGen1EqBoostMagEnable= 0 PortSettings[3] HsioRxGen1EqBoostMag= 0 PortSettings[3] HsioRxGen2EqBoostMagEnable= 0 PortSettings[3] HsioRxGen2EqBoostMag= 0 PortSettings[3] HsioRxGen3EqBoostMagEnable= 0 PortSettings[3] HsioRxGen3EqBoostMag= 0 PortSettings[3] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[3] HsioTxGen1DownscaleAmp= 0 PortSettings[3] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[3] HsioTxGen2DownscaleAmp= 0 PortSettings[3] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[3] HsioTxGen3DownscaleAmp= 0 PortSettings[3] HsioTxGen1DeEmphEnable= 0 PortSettings[3] HsioTxGen1DeEmph= 0 PortSettings[3] HsioTxGen2DeEmphEnable= 0 PortSettings[3] HsioTxGen2DeEmph= 0 PortSettings[3] HsioTxGen3DeEmphEnable= 0 PortSettings[3] HsioTxGen3DeEmph= 0 PortSettings[4] Enabled= 1 PortSettings[4] HotPlug= 1 PortSettings[4] InterlockSw= 0 PortSettings[4] External= 0 PortSettings[4] SpinUp= 0 PortSettings[4] SolidStateDrive= 0 PortSettings[4] DevSlp= 0 PortSettings[4] EnableDitoConfig= 0 PortSettings[4] DmVal= F PortSettings[4] DitoVal= 271 PortSettings[4] ZpOdd= 0 PortSettings[4] HsioRxGen1EqBoostMagEnable= 0 PortSettings[4] HsioRxGen1EqBoostMag= 0 PortSettings[4] HsioRxGen2EqBoostMagEnable= 0 PortSettings[4] HsioRxGen2EqBoostMag= 0 PortSettings[4] HsioRxGen3EqBoostMagEnable= 0 PortSettings[4] HsioRxGen3EqBoostMag= 0 PortSettings[4] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[4] HsioTxGen1DownscaleAmp= 0 PortSettings[4] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[4] HsioTxGen2DownscaleAmp= 0 PortSettings[4] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[4] HsioTxGen3DownscaleAmp= 0 PortSettings[4] HsioTxGen1DeEmphEnable= 0 PortSettings[4] HsioTxGen1DeEmph= 0 PortSettings[4] HsioTxGen2DeEmphEnable= 0 PortSettings[4] HsioTxGen2DeEmph= 0 PortSettings[4] HsioTxGen3DeEmphEnable= 0 PortSettings[4] HsioTxGen3DeEmph= 0 PortSettings[5] Enabled= 1 PortSettings[5] HotPlug= 1 PortSettings[5] InterlockSw= 0 PortSettings[5] External= 0 PortSettings[5] SpinUp= 0 PortSettings[5] SolidStateDrive= 0 PortSettings[5] DevSlp= 0 PortSettings[5] EnableDitoConfig= 0 PortSettings[5] DmVal= F PortSettings[5] DitoVal= 271 PortSettings[5] ZpOdd= 0 PortSettings[5] HsioRxGen1EqBoostMagEnable= 0 PortSettings[5] HsioRxGen1EqBoostMag= 0 PortSettings[5] HsioRxGen2EqBoostMagEnable= 0 PortSettings[5] HsioRxGen2EqBoostMag= 0 PortSettings[5] HsioRxGen3EqBoostMagEnable= 0 PortSettings[5] HsioRxGen3EqBoostMag= 0 PortSettings[5] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[5] HsioTxGen1DownscaleAmp= 0 PortSettings[5] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[5] HsioTxGen2DownscaleAmp= 0 PortSettings[5] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[5] HsioTxGen3DownscaleAmp= 0 PortSettings[5] HsioTxGen1DeEmphEnable= 0 PortSettings[5] HsioTxGen1DeEmph= 0 PortSettings[5] HsioTxGen2DeEmphEnable= 0 PortSettings[5] HsioTxGen2DeEmph= 0 PortSettings[5] HsioTxGen3DeEmphEnable= 0 PortSettings[5] HsioTxGen3DeEmph= 0 PortSettings[6] Enabled= 1 PortSettings[6] HotPlug= 1 PortSettings[6] InterlockSw= 0 PortSettings[6] External= 0 PortSettings[6] SpinUp= 0 PortSettings[6] SolidStateDrive= 0 PortSettings[6] DevSlp= 0 PortSettings[6] EnableDitoConfig= 0 PortSettings[6] DmVal= F PortSettings[6] DitoVal= 271 PortSettings[6] ZpOdd= 0 PortSettings[6] HsioRxGen1EqBoostMagEnable= 0 PortSettings[6] HsioRxGen1EqBoostMag= 0 PortSettings[6] HsioRxGen2EqBoostMagEnable= 0 PortSettings[6] HsioRxGen2EqBoostMag= 0 PortSettings[6] HsioRxGen3EqBoostMagEnable= 0 PortSettings[6] HsioRxGen3EqBoostMag= 0 PortSettings[6] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[6] HsioTxGen1DownscaleAmp= 0 PortSettings[6] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[6] HsioTxGen2DownscaleAmp= 0 PortSettings[6] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[6] HsioTxGen3DownscaleAmp= 0 PortSettings[6] HsioTxGen1DeEmphEnable= 0 PortSettings[6] HsioTxGen1DeEmph= 0 PortSettings[6] HsioTxGen2DeEmphEnable= 0 PortSettings[6] HsioTxGen2DeEmph= 0 PortSettings[6] HsioTxGen3DeEmphEnable= 0 PortSettings[6] HsioTxGen3DeEmph= 0 PortSettings[7] Enabled= 1 PortSettings[7] HotPlug= 1 PortSettings[7] InterlockSw= 0 PortSettings[7] External= 0 PortSettings[7] SpinUp= 0 PortSettings[7] SolidStateDrive= 0 PortSettings[7] DevSlp= 0 PortSettings[7] EnableDitoConfig= 0 PortSettings[7] DmVal= F PortSettings[7] DitoVal= 271 PortSettings[7] ZpOdd= 0 PortSettings[7] HsioRxGen1EqBoostMagEnable= 0 PortSettings[7] HsioRxGen1EqBoostMag= 0 PortSettings[7] HsioRxGen2EqBoostMagEnable= 0 PortSettings[7] HsioRxGen2EqBoostMag= 0 PortSettings[7] HsioRxGen3EqBoostMagEnable= 0 PortSettings[7] HsioRxGen3EqBoostMag= 0 PortSettings[7] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[7] HsioTxGen1DownscaleAmp= 0 PortSettings[7] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[7] HsioTxGen2DownscaleAmp= 0 PortSettings[7] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[7] HsioTxGen3DownscaleAmp= 0 PortSettings[7] HsioTxGen1DeEmphEnable= 0 PortSettings[7] HsioTxGen1DeEmph= 0 PortSettings[7] HsioTxGen2DeEmphEnable= 0 PortSettings[7] HsioTxGen2DeEmph= 0 PortSettings[7] HsioTxGen3DeEmphEnable= 0 PortSettings[7] HsioTxGen3DeEmph= 0 RaidAlternateId= 0 Raid0= 1 Raid1= 1 Raid10= 1 Raid5= 1 Irrt= 1 OromUiBanner= 1 OromUiDelay= 0 HddUnlock= 0 LedLocate= 0 IrrtOnly= 1 SmartStorage= 1 SpeedSupport= 3 eSATASpeedLimit= 0 TestMode= 0 SalpSupport= 0 RstPcieStorageRemap[0].Enable = 0 RstPcieStorageRemap[0].RstPcieStoragePort = 0 RstPcieStorageRemap[0].DeviceResetDelay = 64 RstPcieStorageRemap[0].RstPcieStorageTestMode = 0 RstPcieStorageRemap[0].RstPcieStoragePortConfigCheck = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceInterface = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceBarSizeCheck = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceBarSelect = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceInterrupt = 0 RstPcieStorageRemap[0].RstPcieStorageAspmProgramming = 0 RstPcieStorageRemap[0].RstPcieStorageSaveRestore = 0 RstPcieStorageRemap[1].Enable = 0 RstPcieStorageRemap[1].RstPcieStoragePort = 0 RstPcieStorageRemap[1].DeviceResetDelay = 64 RstPcieStorageRemap[1].RstPcieStorageTestMode = 0 RstPcieStorageRemap[1].RstPcieStoragePortConfigCheck = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceInterface = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceBarSizeCheck = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceBarSelect = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceInterrupt = 0 RstPcieStorageRemap[1].RstPcieStorageAspmProgramming = 0 RstPcieStorageRemap[1].RstPcieStorageSaveRestore = 0 RstPcieStorageRemap[2].Enable = 0 RstPcieStorageRemap[2].RstPcieStoragePort = 0 RstPcieStorageRemap[2].DeviceResetDelay = 64 RstPcieStorageRemap[2].RstPcieStorageTestMode = 0 RstPcieStorageRemap[2].RstPcieStoragePortConfigCheck = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceInterface = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceBarSizeCheck = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceBarSelect = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceInterrupt = 0 RstPcieStorageRemap[2].RstPcieStorageAspmProgramming = 0 RstPcieStorageRemap[2].RstPcieStorageSaveRestore = 0 LtrEnable= 0 LtrConfigLock= 0 LtrOverride= 0 SnoopLatencyOverrideMultiplier= 2 SataAssel= 0 RstPcieStorageRemapSataMsix= 0 SnoopLatencyOverrideValue= A ------------------ PCH SATA Config 1 ----------------- Enable= 1 SataMode= 0 PortSettings[0] Enabled= 0 PortSettings[0] HotPlug= 1 PortSettings[0] InterlockSw= 0 PortSettings[0] External= 0 PortSettings[0] SpinUp= 0 PortSettings[0] SolidStateDrive= 0 PortSettings[0] DevSlp= 0 PortSettings[0] EnableDitoConfig= 0 PortSettings[0] DmVal= F PortSettings[0] DitoVal= 271 PortSettings[0] ZpOdd= 0 PortSettings[0] HsioRxGen1EqBoostMagEnable= 0 PortSettings[0] HsioRxGen1EqBoostMag= 0 PortSettings[0] HsioRxGen2EqBoostMagEnable= 0 PortSettings[0] HsioRxGen2EqBoostMag= 0 PortSettings[0] HsioRxGen3EqBoostMagEnable= 0 PortSettings[0] HsioRxGen3EqBoostMag= 0 PortSettings[0] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[0] HsioTxGen1DownscaleAmp= 0 PortSettings[0] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[0] HsioTxGen2DownscaleAmp= 0 PortSettings[0] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[0] HsioTxGen3DownscaleAmp= 0 PortSettings[0] HsioTxGen1DeEmphEnable= 0 PortSettings[0] HsioTxGen1DeEmph= 0 PortSettings[0] HsioTxGen2DeEmphEnable= 0 PortSettings[0] HsioTxGen2DeEmph= 0 PortSettings[0] HsioTxGen3DeEmphEnable= 0 PortSettings[0] HsioTxGen3DeEmph= 0 PortSettings[1] Enabled= 0 PortSettings[1] HotPlug= 1 PortSettings[1] InterlockSw= 0 PortSettings[1] External= 0 PortSettings[1] SpinUp= 0 PortSettings[1] SolidStateDrive= 0 PortSettings[1] DevSlp= 0 PortSettings[1] EnableDitoConfig= 0 PortSettings[1] DmVal= F PortSettings[1] DitoVal= 271 PortSettings[1] ZpOdd= 0 PortSettings[1] HsioRxGen1EqBoostMagEnable= 0 PortSettings[1] HsioRxGen1EqBoostMag= 0 PortSettings[1] HsioRxGen2EqBoostMagEnable= 0 PortSettings[1] HsioRxGen2EqBoostMag= 0 PortSettings[1] HsioRxGen3EqBoostMagEnable= 0 PortSettings[1] HsioRxGen3EqBoostMag= 0 PortSettings[1] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[1] HsioTxGen1DownscaleAmp= 0 PortSettings[1] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[1] HsioTxGen2DownscaleAmp= 0 PortSettings[1] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[1] HsioTxGen3DownscaleAmp= 0 PortSettings[1] HsioTxGen1DeEmphEnable= 0 PortSettings[1] HsioTxGen1DeEmph= 0 PortSettings[1] HsioTxGen2DeEmphEnable= 0 PortSettings[1] HsioTxGen2DeEmph= 0 PortSettings[1] HsioTxGen3DeEmphEnable= 0 PortSettings[1] HsioTxGen3DeEmph= 0 PortSettings[2] Enabled= 0 PortSettings[2] HotPlug= 1 PortSettings[2] InterlockSw= 0 PortSettings[2] External= 0 PortSettings[2] SpinUp= 0 PortSettings[2] SolidStateDrive= 0 PortSettings[2] DevSlp= 0 PortSettings[2] EnableDitoConfig= 0 PortSettings[2] DmVal= F PortSettings[2] DitoVal= 271 PortSettings[2] ZpOdd= 0 PortSettings[2] HsioRxGen1EqBoostMagEnable= 0 PortSettings[2] HsioRxGen1EqBoostMag= 0 PortSettings[2] HsioRxGen2EqBoostMagEnable= 0 PortSettings[2] HsioRxGen2EqBoostMag= 0 PortSettings[2] HsioRxGen3EqBoostMagEnable= 0 PortSettings[2] HsioRxGen3EqBoostMag= 0 PortSettings[2] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[2] HsioTxGen1DownscaleAmp= 0 PortSettings[2] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[2] HsioTxGen2DownscaleAmp= 0 PortSettings[2] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[2] HsioTxGen3DownscaleAmp= 0 PortSettings[2] HsioTxGen1DeEmphEnable= 0 PortSettings[2] HsioTxGen1DeEmph= 0 PortSettings[2] HsioTxGen2DeEmphEnable= 0 PortSettings[2] HsioTxGen2DeEmph= 0 PortSettings[2] HsioTxGen3DeEmphEnable= 0 PortSettings[2] HsioTxGen3DeEmph= 0 PortSettings[3] Enabled= 0 PortSettings[3] HotPlug= 1 PortSettings[3] InterlockSw= 0 PortSettings[3] External= 0 PortSettings[3] SpinUp= 0 PortSettings[3] SolidStateDrive= 0 PortSettings[3] DevSlp= 0 PortSettings[3] EnableDitoConfig= 0 PortSettings[3] DmVal= F PortSettings[3] DitoVal= 271 PortSettings[3] ZpOdd= 0 PortSettings[3] HsioRxGen1EqBoostMagEnable= 0 PortSettings[3] HsioRxGen1EqBoostMag= 0 PortSettings[3] HsioRxGen2EqBoostMagEnable= 0 PortSettings[3] HsioRxGen2EqBoostMag= 0 PortSettings[3] HsioRxGen3EqBoostMagEnable= 0 PortSettings[3] HsioRxGen3EqBoostMag= 0 PortSettings[3] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[3] HsioTxGen1DownscaleAmp= 0 PortSettings[3] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[3] HsioTxGen2DownscaleAmp= 0 PortSettings[3] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[3] HsioTxGen3DownscaleAmp= 0 PortSettings[3] HsioTxGen1DeEmphEnable= 0 PortSettings[3] HsioTxGen1DeEmph= 0 PortSettings[3] HsioTxGen2DeEmphEnable= 0 PortSettings[3] HsioTxGen2DeEmph= 0 PortSettings[3] HsioTxGen3DeEmphEnable= 0 PortSettings[3] HsioTxGen3DeEmph= 0 PortSettings[4] Enabled= 1 PortSettings[4] HotPlug= 1 PortSettings[4] InterlockSw= 0 PortSettings[4] External= 0 PortSettings[4] SpinUp= 0 PortSettings[4] SolidStateDrive= 0 PortSettings[4] DevSlp= 0 PortSettings[4] EnableDitoConfig= 0 PortSettings[4] DmVal= F PortSettings[4] DitoVal= 271 PortSettings[4] ZpOdd= 0 PortSettings[4] HsioRxGen1EqBoostMagEnable= 0 PortSettings[4] HsioRxGen1EqBoostMag= 0 PortSettings[4] HsioRxGen2EqBoostMagEnable= 0 PortSettings[4] HsioRxGen2EqBoostMag= 0 PortSettings[4] HsioRxGen3EqBoostMagEnable= 0 PortSettings[4] HsioRxGen3EqBoostMag= 0 PortSettings[4] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[4] HsioTxGen1DownscaleAmp= 0 PortSettings[4] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[4] HsioTxGen2DownscaleAmp= 0 PortSettings[4] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[4] HsioTxGen3DownscaleAmp= 0 PortSettings[4] HsioTxGen1DeEmphEnable= 0 PortSettings[4] HsioTxGen1DeEmph= 0 PortSettings[4] HsioTxGen2DeEmphEnable= 0 PortSettings[4] HsioTxGen2DeEmph= 0 PortSettings[4] HsioTxGen3DeEmphEnable= 0 PortSettings[4] HsioTxGen3DeEmph= 0 PortSettings[5] Enabled= 1 PortSettings[5] HotPlug= 1 PortSettings[5] InterlockSw= 0 PortSettings[5] External= 0 PortSettings[5] SpinUp= 0 PortSettings[5] SolidStateDrive= 0 PortSettings[5] DevSlp= 0 PortSettings[5] EnableDitoConfig= 0 PortSettings[5] DmVal= F PortSettings[5] DitoVal= 271 PortSettings[5] ZpOdd= 0 PortSettings[5] HsioRxGen1EqBoostMagEnable= 0 PortSettings[5] HsioRxGen1EqBoostMag= 0 PortSettings[5] HsioRxGen2EqBoostMagEnable= 0 PortSettings[5] HsioRxGen2EqBoostMag= 0 PortSettings[5] HsioRxGen3EqBoostMagEnable= 0 PortSettings[5] HsioRxGen3EqBoostMag= 0 PortSettings[5] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[5] HsioTxGen1DownscaleAmp= 0 PortSettings[5] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[5] HsioTxGen2DownscaleAmp= 0 PortSettings[5] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[5] HsioTxGen3DownscaleAmp= 0 PortSettings[5] HsioTxGen1DeEmphEnable= 0 PortSettings[5] HsioTxGen1DeEmph= 0 PortSettings[5] HsioTxGen2DeEmphEnable= 0 PortSettings[5] HsioTxGen2DeEmph= 0 PortSettings[5] HsioTxGen3DeEmphEnable= 0 PortSettings[5] HsioTxGen3DeEmph= 0 PortSettings[6] Enabled= 1 PortSettings[6] HotPlug= 1 PortSettings[6] InterlockSw= 0 PortSettings[6] External= 0 PortSettings[6] SpinUp= 0 PortSettings[6] SolidStateDrive= 0 PortSettings[6] DevSlp= 0 PortSettings[6] EnableDitoConfig= 0 PortSettings[6] DmVal= F PortSettings[6] DitoVal= 271 PortSettings[6] ZpOdd= 0 PortSettings[6] HsioRxGen1EqBoostMagEnable= 0 PortSettings[6] HsioRxGen1EqBoostMag= 0 PortSettings[6] HsioRxGen2EqBoostMagEnable= 0 PortSettings[6] HsioRxGen2EqBoostMag= 0 PortSettings[6] HsioRxGen3EqBoostMagEnable= 0 PortSettings[6] HsioRxGen3EqBoostMag= 0 PortSettings[6] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[6] HsioTxGen1DownscaleAmp= 0 PortSettings[6] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[6] HsioTxGen2DownscaleAmp= 0 PortSettings[6] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[6] HsioTxGen3DownscaleAmp= 0 PortSettings[6] HsioTxGen1DeEmphEnable= 0 PortSettings[6] HsioTxGen1DeEmph= 0 PortSettings[6] HsioTxGen2DeEmphEnable= 0 PortSettings[6] HsioTxGen2DeEmph= 0 PortSettings[6] HsioTxGen3DeEmphEnable= 0 PortSettings[6] HsioTxGen3DeEmph= 0 PortSettings[7] Enabled= 1 PortSettings[7] HotPlug= 1 PortSettings[7] InterlockSw= 0 PortSettings[7] External= 0 PortSettings[7] SpinUp= 0 PortSettings[7] SolidStateDrive= 0 PortSettings[7] DevSlp= 0 PortSettings[7] EnableDitoConfig= 0 PortSettings[7] DmVal= F PortSettings[7] DitoVal= 271 PortSettings[7] ZpOdd= 0 PortSettings[7] HsioRxGen1EqBoostMagEnable= 0 PortSettings[7] HsioRxGen1EqBoostMag= 0 PortSettings[7] HsioRxGen2EqBoostMagEnable= 0 PortSettings[7] HsioRxGen2EqBoostMag= 0 PortSettings[7] HsioRxGen3EqBoostMagEnable= 0 PortSettings[7] HsioRxGen3EqBoostMag= 0 PortSettings[7] HsioTxGen1DownscaleAmpEnable= 0 PortSettings[7] HsioTxGen1DownscaleAmp= 0 PortSettings[7] HsioTxGen2DownscaleAmpEnable= 0 PortSettings[7] HsioTxGen2DownscaleAmp= 0 PortSettings[7] HsioTxGen3DownscaleAmpEnable= 0 PortSettings[7] HsioTxGen3DownscaleAmp= 0 PortSettings[7] HsioTxGen1DeEmphEnable= 0 PortSettings[7] HsioTxGen1DeEmph= 0 PortSettings[7] HsioTxGen2DeEmphEnable= 0 PortSettings[7] HsioTxGen2DeEmph= 0 PortSettings[7] HsioTxGen3DeEmphEnable= 0 PortSettings[7] HsioTxGen3DeEmph= 0 RaidAlternateId= 0 Raid0= 1 Raid1= 1 Raid10= 1 Raid5= 1 Irrt= 1 OromUiBanner= 1 OromUiDelay= 0 HddUnlock= 0 LedLocate= 0 IrrtOnly= 1 SmartStorage= 1 SpeedSupport= 3 eSATASpeedLimit= 0 TestMode= 0 SalpSupport= 0 RstPcieStorageRemap[0].Enable = 0 RstPcieStorageRemap[0].RstPcieStoragePort = 0 RstPcieStorageRemap[0].DeviceResetDelay = 64 RstPcieStorageRemap[0].RstPcieStorageTestMode = 0 RstPcieStorageRemap[0].RstPcieStoragePortConfigCheck = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceInterface = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceBarSizeCheck = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceBarSelect = 0 RstPcieStorageRemap[0].RstPcieStorageDeviceInterrupt = 0 RstPcieStorageRemap[0].RstPcieStorageAspmProgramming = 0 RstPcieStorageRemap[0].RstPcieStorageSaveRestore = 0 RstPcieStorageRemap[1].Enable = 0 RstPcieStorageRemap[1].RstPcieStoragePort = 0 RstPcieStorageRemap[1].DeviceResetDelay = 64 RstPcieStorageRemap[1].RstPcieStorageTestMode = 0 RstPcieStorageRemap[1].RstPcieStoragePortConfigCheck = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceInterface = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceBarSizeCheck = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceBarSelect = 0 RstPcieStorageRemap[1].RstPcieStorageDeviceInterrupt = 0 RstPcieStorageRemap[1].RstPcieStorageAspmProgramming = 0 RstPcieStorageRemap[1].RstPcieStorageSaveRestore = 0 RstPcieStorageRemap[2].Enable = 0 RstPcieStorageRemap[2].RstPcieStoragePort = 0 RstPcieStorageRemap[2].DeviceResetDelay = 64 RstPcieStorageRemap[2].RstPcieStorageTestMode = 0 RstPcieStorageRemap[2].RstPcieStoragePortConfigCheck = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceInterface = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceBarSizeCheck = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceBarSelect = 0 RstPcieStorageRemap[2].RstPcieStorageDeviceInterrupt = 0 RstPcieStorageRemap[2].RstPcieStorageAspmProgramming = 0 RstPcieStorageRemap[2].RstPcieStorageSaveRestore = 0 LtrEnable= 0 LtrConfigLock= 0 LtrOverride= 0 SnoopLatencyOverrideMultiplier= 2 SataAssel= 0 RstPcieStorageRemapSataMsix= 0 SnoopLatencyOverrideValue= A ------------------ PCH USB Config ------------------ UsbPrecondition= 0 DisableComplianceMode= 0 PortUsb20[0].Enabled= 1 PortUsb20[0].OverCurrentPin= OC8 PortUsb20[0].Afe.Petxiset= 4 PortUsb20[0].Afe.Txiset= 0 PortUsb20[0].Afe.Predeemp= 3 PortUsb20[0].Afe.Pehalfbit= 0 PortUsb20[1].Enabled= 1 PortUsb20[1].OverCurrentPin= OC8 PortUsb20[1].Afe.Petxiset= 4 PortUsb20[1].Afe.Txiset= 0 PortUsb20[1].Afe.Predeemp= 3 PortUsb20[1].Afe.Pehalfbit= 0 PortUsb20[2].Enabled= 1 PortUsb20[2].OverCurrentPin= OC8 PortUsb20[2].Afe.Petxiset= 4 PortUsb20[2].Afe.Txiset= 0 PortUsb20[2].Afe.Predeemp= 3 PortUsb20[2].Afe.Pehalfbit= 0 PortUsb20[3].Enabled= 1 PortUsb20[3].OverCurrentPin= OC8 PortUsb20[3].Afe.Petxiset= 4 PortUsb20[3].Afe.Txiset= 0 PortUsb20[3].Afe.Predeemp= 3 PortUsb20[3].Afe.Pehalfbit= 0 PortUsb30[0] Enabled= 0 PortUsb30[0].OverCurrentPin= OC8 PortUsb30[0].HsioTxDeEmph = 0 PortUsb30[0].HsioTxDeEmphEnable = 0 PortUsb30[0].HsioTxDownscaleAmp = 0 PortUsb30[0].HsioTxDownscaleAmpEnable = 0 PortUsb30[1] Enabled= 0 PortUsb30[1].OverCurrentPin= OC8 PortUsb30[1].HsioTxDeEmph = 0 PortUsb30[1].HsioTxDeEmphEnable = 0 PortUsb30[1].HsioTxDownscaleAmp = 0 PortUsb30[1].HsioTxDownscaleAmpEnable = 0 PortUsb30[2] Enabled= 0 PortUsb30[2].OverCurrentPin= OC8 PortUsb30[2].HsioTxDeEmph = 0 PortUsb30[2].HsioTxDeEmphEnable = 0 PortUsb30[2].HsioTxDownscaleAmp = 0 PortUsb30[2].HsioTxDownscaleAmpEnable = 0 PortUsb30[3] Enabled= 0 PortUsb30[3].OverCurrentPin= OC8 PortUsb30[3].HsioTxDeEmph = 0 PortUsb30[3].HsioTxDeEmphEnable = 0 PortUsb30[3].HsioTxDownscaleAmp = 0 PortUsb30[3].HsioTxDownscaleAmpEnable = 0 XhciEnabled = 0 XhciSsicHalt = 0 EPTypeLockPolicy = 0x00000000 EPTypeLockPolicyPortControl1 = 0x00000000 EPTypeLockPolicyPortControl2 = 0x00000000 TstMnuUnlockUsbForNoa= 0 ------------------ PCH IOAPIC Config ------------------ BdfValid= 1 BusNumber= F0 DeviceNumber= 1F FunctionNumber= 0 IoApicId= 2 ApicRangeSelect= 0 IoApicEntry24_119= 0 ------------------ PCH HPET Config ------------------ Enable 1 BdfValid 0 BusNumber 0 DeviceNumber 0 FunctionNumber 0 Base FED00000 ------------------ PCH SMBUS Config ------------------ Enable= 1 ArpEnable= 0 DynamicPowerGating= 0 SmbusIoBase= EFA0 NumRsvdSmbusAddresses= 4 RsvdSmbusAddressTable= { A2h A0h A2h A0h } ------------------ PCH Lock Down Config ------------------ GlobalSmi= 1 BiosInterface= 1 RtcLock= 1 BiosLock= 1 SpiEiss= 1 ------------------ PCH PM Config ------------------ PowerResetStatusClear MeWakeSts = 0 PowerResetStatusClear MeHrstColdSts = 0 PowerResetStatusClear MeHrstWarmSts = 0 PowerResetStatusClear MeHostPowerDn = 0 PowerResetStatusClear WolOvrWkSts = 0 WakeConfig PmeB0S5Dis = 0 WakeConfig WolEnableOverride = 0 WakeConfig LanWakeFromDeepSx = 0 WakeConfig PcieWakeFromDeepSx = 0 WakeConfig WoWlanEnable = 0 WakeConfig WoWlanDeepSxEnable = 0 PchDeepSxPol = 0 PchSlpS3MinAssert = 0 PchSlpS4MinAssert = 0 PchSlpSusMinAssert = 0 PchSlpAMinAssert = 0 PciClockRun = 0 SlpStrchSusUp = 0 SlpLanLowDc = 0 PwrBtnOverridePeriod = 0 DisableEnergyReport = 0 DisableDsxAcPresentPulldown = 0 PmcReadDisable = 1 PchPwrCycDur = 0 PciePllSsc = 0 CapsuleResetType = 0 PchPmRegisterLock = 0 SlpS0CsMePgQDis = 0 SlpS0GbeDiscQDis = 0 SlpS0ADspD3QDis = 0 SlpS0XhciD3QDis = 0 SlpS0LpioD3QDis = 0 SlpS0IccPllWBEn = 0 SlpS0PUGBEn = 0 ------------------ PCH LPC SIRQ Config ------------------ SirqEnable= 1 SirqMode= 0 StartFramePulse= 0 ------------------ PCH Interrupt Config ------------------ Interrupt assignment: Dxx:Fx INTx IRQ D31:F4 1 023 D31:F7 1 023 D28:F0 1 016 D27:F0 1 016 D27:F1 2 017 D27:F3 3 018 D27:F4 4 019 D26:F2 3 018 D26:F1 2 017 D26:F0 1 016 D24:F0 1 016 D24:F1 2 017 D24:F3 3 018 D24:F4 4 019 D23:F0 1 017 D22:F0 1 016 D21:F0 1 019 D20:F0 1 021 D19:F0 1 020 D18:F0 1 016 D17:F0 4 023 D16:F0 3 022 D15:F0 2 021 D14:F0 1 020 D12:F0 4 019 D11:F0 3 018 D10:F0 2 017 D09:F0 1 016 D06:F0 1 018 D05:F0 1 023 Legacy PIC interrupt routing: PIRQx IRQx PIRQA -> IRQ11 PIRQB -> IRQ10 PIRQC -> IRQ6 PIRQD -> IRQ7 PIRQE -> IRQ12 PIRQF -> IRQ14 PIRQG -> IRQ15 PIRQH -> IRQ15 Other interrupt configuration: GpioIrqRoute= 14 SciIrqSelect= 9 TcoIrqEnable= 0 TcoIrqSelect= 9 ------------------ PCH HSUART Config ---------------- HsUartMode[0]= 0 HsUartMode[1]= 0 HsUartMode[2]= 0 ------------------ PCH TraceHub Config ------------------ TraceHubEnable = 1 TraceHubFwEnable = 1 TraceHubFwDestination = 1 TraceHubPtiMode = 2 TraceHubPtiTraining = 0 TraceHubPtiSpeed = 0 TraceHubMemBaseRegion0 = 0 TraceHubMemBaseRegion1 = 0 EnableMode= 0 MemReg0Size= 100000 MemReg1Size= 100000 ------------------ PCH Flash Protection Config ------------------ WriteProtectionEnable[0]= 1 ReadProtectionEnable[0]= 0 ProtectedRangeLimit[0]= 0 ProtectedRangeBase[0]= 0 WriteProtectionEnable[1]= 1 ReadProtectionEnable[1]= 0 ProtectedRangeLimit[1]= 0 ProtectedRangeBase[1]= 0 WriteProtectionEnable[2]= 1 ReadProtectionEnable[2]= 0 ProtectedRangeLimit[2]= 0 ProtectedRangeBase[2]= 0 WriteProtectionEnable[3]= 1 ReadProtectionEnable[3]= 0 ProtectedRangeLimit[3]= 0 ProtectedRangeBase[3]= 0 WriteProtectionEnable[4]= 1 ReadProtectionEnable[4]= 0 ProtectedRangeLimit[4]= 0 ProtectedRangeBase[4]= 0 ------------------ PCH WDT Config ------------------ DisableAndLock= 1 ------------------ PCH P2SB Config ------------------ SbiUnlock= 0 PsfUnlock= 0 ------------------ PCH DCI Config ------------------ DciEn= 0 DciAutoDetect= 1 ------------------ PCH LPC Config ------------------ EnhancePort8xhDecoding= 1 ------------------ PCH SPI Config ------------------ ShowSpiController= 0 ------------------------ PCH Print Platform Protocol End -------------------------- Install PPI: DFE2B897-0E8E-4926-BC69-E5EDD3F938E1 PCH PEI Policy Initialization Done in Pre-Memory TotalBlockCount = 0x5 TotalPolicySize after adding Block[0x0]= 0x68 TotalPolicySize after adding Block[0x1]= 0x84 TotalPolicySize after adding Block[0x2]= 0xA34 TotalPolicySize after adding Block[0x3]= 0xA48 TotalPolicySize after adding Block[0x4]= 0xA60 TotalPolicySize Final = 0xA60 SaInitPolicy= 0xFEF62BB8 Inside case EnumPlatformConfigId Exiting case EnumPlatformConfigId Addnew config block for SaIpBlocks[BlockCount].BlockId = 0x0 Inside case EnumVtdConfigId Vtd->BlockId = 0x3 Vtd->BlockSize = 0x1C Vtd 0x1C and remapping 0x0 Exiting case EnumVtdConfigId Addnew config block for SaIpBlocks[BlockCount].BlockId = 0x3 Exiting case EnumMemConfigId Addnew config block for SaIpBlocks[BlockCount].BlockId = 0x1 Exiting case EnumNvMemConfigId Addnew config block for SaIpBlocks[BlockCount].BlockId = 0x2 Exiting case EnumSaRestrictedConfigId Addnew config block for SaIpBlocks[BlockCount].BlockId = 0x4 SiSaPolicyPpi->Header.BlockCount = 0x5 UpdatePeiSaPolicy() vtd 1 and remapping 1 Install PPI: F5621AF5-F70B-4360-84F3-C2CF5143CDB8 SA Data HOB installed SystemAgent PEI Platform Policy Initialization Done Pcie IP Policy ready!! Install PPI: BB159A68-8300-43EF-A2A7-F2ADE6C964A6 PCIE IP PEI Policy Initialization Done IQAT IP Policy ready!! Install PPI: AC6BD8E9-0B89-45B1-AE09-A2C017334B6A IQAT IP PEI Policy Initialization Done FspInitPreMemEntryPoint() - End Loading PEIM at 0x000FFF56C4C EntryPoint=0x000FFF56D1C SiInitPrePolicy : Entry Install PPI: 75AFD0B3-1F2F-4871-AFF2-7AA48AF259D8 PchInitPrePolicy : Entry PCH Series : SKL PCH-H PCH Revision ID: 0x11 PCH Stepping : B1 PCH SKU : (WDT) Readback = 0x00002000 (WDT) Status OK. Install PPI: F38D1338-AF7A-4FB6-91DB-1A9C2183570D Install PPI: 17865DC0-0B8B-4DA8-8B42-7C46B85CCA4D InstallPchReset() Start Install PPI: 433E0F9F-05AE-410A-A0C3-BF298ECB25AC InstallPchReset() End InstallPchSpi() Start Flash Region read Permission : FF Flash Region write Permission : FF Component 0 SFDP VSCC value : B1D82084 Component 1 SFDP VSCC value : 2000 Component Number : 1 Total Flash Size : 1000000 PchStrapBaseAddr : 100 PchStrapSize : FC CpuStrapBaseAddr : 300 CpuStrapSize : 4 Install PPI: FBF26154-4E55-4BDC-AF7B-D918AC443F61 SPI PPI Installed InstallPchSpi() End PchInitPreMem : Entry PCH PWRM Base needs to be programmed before here PCH Revision ID: 0x11 PCH Revision ID: 0x11 PchEarlyInit : Entry PRSTS = 0xFED03010 Value = 0x10100900 ETR3 = 0xE00FA0AC Value = 0x00000000 ConfigureLpcOnEarlyPei() PchEarlyInit : Exit PchInitPreMem : Exit PchInitPrePolicy : Exit Register PPI Notify: AEBFFA01-7EDC-49FF-8D88-CB848C5E8670 Notify: PPI Guid: AEBFFA01-7EDC-49FF-8D88-CB848C5E8670, Peim notify entry point: FFF56D4C SiInitPreMemOnPolicy : Entry PmcStPgInit : Entry ST_PG_FDIS_PMC_1 = 0x00000000 PmcStPgInit : Exit PchOnPolicyInstalled : Entry (Wdt) IsWdtEnabled - no xHCI: USB not pressent. Skiping AFE programing PCH Revision ID: 0x11 MePolicyPpi not located! Error: Not Found (Hsio) ChipsetInitHob not found [HECI] Send msg: 80040007 000001F2 [HECI] Got msg: 80080007 000081F2 ... (Hsio) Creating HOB to adjust Hsio settings in PchInit, if required (Hsio) ME Reported CRC=0x12FD (Hsio) BIOS Hsio CRC=0x12FD PchHsioBiosProg() Start PostCode <> FIA LOS1 = 22220000 FIA LOS2 = 00000000 FIA LOS3 = 00002222 PCH Revision ID: 0x11 Was detected stepping 3 POSTCODE << C5 >> LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported LaneNum unsupported POSTCODE << C6 >> PchHsioBiosProg() End PostCode <> PchDciConfiguration : Entry ECTRL = 0x00000000 PchDciConfiguration : Exit TraceHubManagePowerGateControl() Hide config space of Trace Hub device TraceHubManagePowerGateControl() Disable config space of Trace Hub ACPI device TraceHubManagePowerGateControl() Power gating Trace Hub device ConfigurePchHSata() Start SataDeviceNumber: 0x13 DisablePchHSataController: DisablePchHSataController() Started Sata Controller Device Number: 0x13 DisablePchHSataController: DisablePchHSataController() Ended ConfigurePchSataAhci() Start SataDeviceNumber: 13 SATA: LPM disable SATA: SALP disable ConfigurePchSataAhci() End ConfigurePchHSata() End ConfigurePchHSata() Start SataDeviceNumber: 0x14 Setting PMC message to enable controller 0x14 ConfigurePchSataAhci() Start SataDeviceNumber: 14 SATA: LPM disable SATA: SALP disable ConfigurePchSataAhci() End ConfigurePchHSata() End InitializePchSmbus() Start Install PPI: 9CA93627-B65B-4324-A202-C0B461764543 InitializePchSmbus() End PchProgramSvidSid : Entry PchProgramSvidSid : Exit PCH Revision ID: 0x11 ConfigureXhciPreMem : Entry xHCI: xHCI controller not pressent ConfigureLpcOnPolicy() PchOnPolicyInstalled : Exit SiInitPreMemOnPolicy : Exit SiInitPrePolicy : Exit Loading PEIM at 0x000FFF65AE4 EntryPoint=0x000FFF65BB4 ME UMA: ME UMA PPI Driver EntryPoint Install PPI: 8C376010-2400-4D7D-B47B-9D851DF3C9D1 ME UMA: ME UMA PPI Installation status Success Loading PEIM at 0x000FFF695EC EntryPoint=0x000FFF696C4 [ME Policy] SSC enabled. Install PPI: 9F685891-4E6F-445C-BB9E-E57A28FA53A0 [ME Policy] ME PEI Platform Policy PPI Installed Loading PEIM at 0x000FFF6C0A0 EntryPoint=0x000FFF6C180 [SPS] SpsPeiEntryPoint called. [SPS] Pre-DID reset is disabled [SPS] Non S3 boot path Register PPI Notify: 12AA57CB-E6F0-40A3-BDF4-B0690C9CCF06 Loading PEIM at 0x000FFF7138C EntryPoint=0x000FFF7145C Install PPI: C884CCCD-2760-400E-AA9D-6D1A9241D539 Platform Policy read successfully UMA: ME UMA size set to 0. Isoc is Disabled. SMBus Legacy: SPD Write Disable bit is locked now! SMBus Host: SPD Write Disable bit is locked now! MRC VERSION: 0x950440 MRCDATA Size: 115F0 MRC_SAVE_RESTORE Size: 6F2C SocStepping: 16 Warning: MspData data structure hasn't been locked yet Dunit Fuse Configuration SCRAMBLER_SUPPORTED: 1 DDR_MAX_FREQ_LIMIT: 2 DDR_CURRENT_FREQ: 2 SINGLE_CHANNEL: 0 IPROCTRIM: 2 TIMING_1N_SUPPORTED: 1 X4_SUPPORTED: 1 X8_SUPPORTED: 1 DDR4_SUPPORTED: 1 DDR3_SUPPORTED: 1 DOUBLE_RANK_SUPPORTED: 1 POPULATE_2DPC_SUPPORTED: 1 ECC_SUPPORTED: 1 MAX_DEN_SUPPORTED: 3 MAX_MEM_SUPPORTED: 7 Warning: MspData data structure hasn't been locked yet Dunit Fuse Configuration SCRAMBLER_SUPPORTED: 1 DDR_MAX_FREQ_LIMIT: 2 DDR_CURRENT_FREQ: 2 SINGLE_CHANNEL: 0 IPROCTRIM: 2 TIMING_1N_SUPPORTED: 1 X4_SUPPORTED: 1 X8_SUPPORTED: 1 DDR4_SUPPORTED: 1 DDR3_SUPPORTED: 1 DOUBLE_RANK_SUPPORTED: 1 POPULATE_2DPC_SUPPORTED: 1 ECC_SUPPORTED: 1 MAX_DEN_SUPPORTED: 3 MAX_MEM_SUPPORTED: 7 DDR4 dimm detected C0.D0: SPD byte 1 = 0x12 C0.D0: SPD byte 2 = 0xC C0.D0: SPD byte 3 = 0x1 C0.D0: SPD byte 4 = 0x84 C0.D0: SPD byte 5 = 0x21 C0.D0: SPD byte 6 = 0x0 C0.D0: SPD byte 7 = 0x8 C0.D0: SPD byte 8 = 0x0 C0.D0: SPD byte 9 = 0x40 C0.D0: SPD byte 11 = 0x3 C0.D0: SPD byte 12 = 0x0 C0.D0: SPD byte 13 = 0xB C0.D0: SPD byte 14 = 0x80 C0.D0: SPD byte 17 = 0x0 C0.D0: SPD byte 18 = 0x8 C0.D0: SPD byte 19 = 0xD C0.D0: SPD byte 20 = 0xF4 C0.D0: SPD byte 21 = 0x3 C0.D0: SPD byte 22 = 0x0 C0.D0: SPD byte 23 = 0x0 C0.D0: SPD byte 24 = 0x6C C0.D0: SPD byte 25 = 0x6C C0.D0: SPD byte 26 = 0x6C C0.D0: SPD byte 27 = 0x11 C0.D0: SPD byte 28 = 0x8 C0.D0: SPD byte 29 = 0x74 C0.D0: SPD byte 30 = 0x20 C0.D0: SPD byte 31 = 0x8 C0.D0: SPD byte 36 = 0x0 C0.D0: SPD byte 37 = 0x78 C0.D0: SPD byte 38 = 0x1E C0.D0: SPD byte 39 = 0x2B C0.D0: SPD byte 40 = 0x2E C0.D0: SPD byte 117 = 0x86 C0.D0: SPD byte 120 = 0x0 C0.D0: SPD byte 121 = 0x0 C0.D0: SPD byte 122 = 0x0 C0.D0: SPD byte 123 = 0x0 C0.D0: SPD byte 124 = 0xE7 C0.D0: SPD byte 125 = 0xC1 C0.D0: SPD byte 131 = 0x5 C0.D0: SPD byte 133 = 0x80 C0.D0: SPD byte 134 = 0xB3 C0.D0: SPD byte 135 = 0x30 C0.D0: SPD byte 136 = 0x0 C0.D0: SPD byte 137 = 0x55 C0.D0: SPD byte 138 = 0x5 C0.D0: SPD byte 320 = 0x1 C0.D0: SPD byte 321 = 0x98 C0.D0: SPD byte 322 = 0x4 C0.D0: SPD byte 323 = 0x17 C0.D0: SPD byte 325 = 0x30 C0.D0: SPD byte 326 = 0x26 C0.D0: SPD byte 327 = 0x8B C0.D0: SPD byte 328 = 0x60 C0.D0: SPD byte 329 = 0x39 C0.D0: SPD byte 330 = 0x39 C0.D0: SPD byte 331 = 0x36 C0.D0: SPD byte 332 = 0x35 C0.D0: SPD byte 333 = 0x35 C0.D0: SPD byte 334 = 0x38 C0.D0: SPD byte 335 = 0x39 C0.D0: SPD byte 336 = 0x2D C0.D0: SPD byte 337 = 0x30 C0.D0: SPD byte 338 = 0x30 C0.D0: SPD byte 339 = 0x36 C0.D0: SPD byte 340 = 0x2E C0.D0: SPD byte 341 = 0x45 C0.D0: SPD byte 342 = 0x30 C0.D0: SPD byte 343 = 0x30 C0.D0: SPD byte 344 = 0x47 C0.D0: SPD byte 345 = 0x20 C0.D0: SPD byte 346 = 0x20 C0.D0: SPD byte 347 = 0x20 C0.D0: SPD byte 348 = 0x20 C0.D0: SPD byte 349 = 0x0 C0.D0: SPD byte 350 = 0x80 C0.D0: SPD byte 351 = 0xAD C0.D0: SPD byte 352 = 0xFF C0.D0: SPD byte 382 = 0x0 C0.D0: SPD byte 383 = 0x0 DDR Common Frequency - DIMM capability: 5 Setup DDR Frequency - minimum of setup and cap: 5 Warning: MspData data structure hasn't been locked yet MrcFlowStatus = 0x00000000 SpdResetStatus (Fuse) = 0x00000000 SPD_RESET_PCODE (Soft Strap) = 0x00000000 SPD_BIOS_RESET = 0x00000000 SpdSpeedCurrentHw = 0x00000002 DDR Frequency : 2133 VSafe VDDQ_DDR4 Command = 8 Address = 3 Data = BF Polling Busy Bit MEM read to offset=0xFED17084; data=0x00000000 Writing Data register 7080 = BF MEM write to offset=0xFED17080; data=0x000000BF Writing Interface register 7084 = 80000308 MEM write to offset=0xFED17084; data=0x80000308 MEM read to offset=0xFED17084; data=0x0000000A MEM read to offset=0xFED17084; data=0x0000000A VSafe message code[10]: mailbox_cc_illegal_vr_id SPD_DDR4_MMIDH: 0x0098 PPR: 1 S/H: 0 taaminall 13500, tckminall 938, CLdesired 15 CH0 TCL 15 TRAS = 36 TRP = 15 TRCD = 15 TWR = 16 TRFCL = 278 TWTR = 8 TRRDS = 6 TRTP = 8 TFAW = 16 TCCD = 6 DimmConfig = 0x00001126 DimmConfigs = 135 Ch 0, Dimm 0, Rank 0, MaxDq: 18 DevWidth: 4 Normal Path Ch 0 3N timing Ch 0 TWCL = 14 Ch 0 TWTP = 34 Ch 0 TFAW = 16 Ch 0 TCCD = 6 CmdOffsetValue = 148 CH0 P: 0x40 CH0 F: 0x04 CH0 C: 0x04 CH0 T: 0x02 CH1 P: 0x40 CH1 F: 0x04 CH1 C: 0x04 CH1 T: 0x01 DESTROY_CONTENT_S0: 1:1 DIMM0 Memory Size: 8192MB CH0 R[0]: 1 / 1 (RDIMM) R[1]: 0 / 0 (RDIMM) R[2]: 0 / 0 (RDIMM) R[3]: 0 / 0 (RDIMM) TSegSize: 0x00000002 MmioAllocation: 0x00000800 TOM: 0x00002000 LowMemory: 0x00000800 HighMemory: 0x00002800 Channel 0 state: 1 Channel 1 state: 0 C[0] at 1N Common at 1N C0 TRRD_S: 0 TRRD_L: 2 Channel[0] Self Refresh = 0 Channel[0] using 30us (0x000007CE) Self Refreshed Delay for DDR 2132MHz Channel 0 PMOP Level = 0 LeakRate - 0x0000000000000000 Demand scrub enabled. CH 0 RK2RK: 1 C0 TCCD_RD: 0 TCCD_WR: 0 TCCD_L_RD: 2 TCCD_L_WR: 2 C0 TWTR_L: 4 TRWSR: 7 TRRDR: 4 TWWDR: 4 TRWDR: 4 TWRDR: 4 TRRDD: 4 TWWDD: 4 TRWDD: 4 TWRDD: 4 C0 0 A0DllWorkAroundEnabled:0 Setting MEMHOT THRT Crit/Hi/Med levels to customer defaults... Setting MEMHOT THRT Crit/Hi/Med levels to customer defaults... MEMHOT set to Critical Level... Disabling MEMTRIP because MTM is disabled... Warning: MspData data structure hasn't been locked yet CP B1 CP 02 CP 03 CP 04 CP 05 CP 06 CP 07 CP 08 CP 09 CP 10 CP 11 CP 12 CP 13 CP 1A CP 14 CP 15 CP 16 CP 17 CP 18 CP 19 CP 20 CP 21 CP 22 CP 23 CP 24 CP 25 CP 26 CP 27 CP 28 CP 29 CP 30 CP 31 CP 32 CP 33 CP 34 CP 35 CP 35 CP 56 CmdOverrideSettings elapsedTime: 32763(us) CP 37 EnableChannels Box Port Offset Mask Action Delay Value +DUNIT_COMMON MEM 0xFED11400 0x0000000000000004 SET 0x00000000 0x0000000000000004 +AUNIT_MCHBAR MEM 0xFED165C0 0x00000000000000FF SET 0x00000000 0x0000000000000001 +DUNIT_COMMON MEM 0xFED11400 0x00000000000000FF SET 0x00000000 0x0000000000000005 CP 37 DisableChannel CP 36 CP 39 elapsedTime: 40(us) CP 40 elapsedTime: 513(us) CP D0 GroupSaveRestore Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- CtlGrp0 00 00 00 00 00 -- 02 00 - 3 - 2 -- 0192 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- CtlGrp1 00 00 00 00 00 -- 02 00 - 3 - 2 -- 0192 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- CtlGrp2 00 00 00 00 00 -- 02 00 - 3 - 2 -- 0192 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------ -- -- -- -- -- --- --- --- - --- --- --- ---- ---- CkAll 00 00 00 00 00 -- 02 00 - 3 - 2 -- 0192 elapsedTime: 297606(us) CP 44 elapsedTime: 34(us) CP 45 elapsedTime: 235(us) CP 46 MmapForTrain Box Port Offset Mask Action Delay Value +DUNIT MEM 0xFED11174 0x00000000FFFFFFFF SET 0x00000000 0x0000000020F08107 +DUNIT MEM 0xFED110B4 0x00000000FFFFFFFF SET 0x00000000 0x000000000000003F +DUNIT MEM 0xFED11148 0x00000000FFFFFFFF SET 0x00000000 0x0000000020F7358B +DUNIT MEM 0xFED1114C 0x00000000FFFFFFFF SET 0x00000000 0x00000000315A4E51 +DUNIT MEM 0xFED11150 0x00000000FFFFFFFF SET 0x00000000 0x000000003FFFFF59 +DUNIT MEM 0xFED11154 0x00000000FFFFFFFF SET 0x00000000 0x00000000065432A9 elapsedTime: 274079(us) CP 47 elapsedTime: 128(us) CP 48 elapsedTime: 4(us) CP 49 ReInitializeFunction ReInitializeFunction DISABLE_CKE Box Port Offset Mask Action Delay Value +DUNIT MEM 0xFED11170 0x000000000000000F SET_DELAY 0x00000064 0x0000000000000000 +DUNIT MEM 0xFED11170 0x0000000000000010 SET_DELAY 0x00000064 0x0000000000000010 RESETDRAMS_COMMON_SET Box Port Offset Mask Action Delay Value +DDRCC1_PHY MEM 0xFD15501C 0x0000000000000001 SET_DELAY 0x00000064 0x0000000000000000 +DDRCC1_PHY MEM 0xFD15501C 0x0000000000000002 SET_DELAY 0x00000064 0x0000000000000002 DELAY: 200us RESETDRAMS_COMMON_CLEAR Box Port Offset Mask Action Delay Value +DDRCC1_PHY MEM 0xFD15501C 0x0000000000000002 SET_DELAY 0x00000064 0x0000000000000000 +DDRCC1_PHY MEM 0xFD15501C 0x0000000000000001 SET_DELAY 0x00000064 0x0000000000000001 +DELAY: 500000ns ENABLE_RELEASE_CKE Box Port Offset Mask Action Delay Value +DUNIT MEM 0xFED11170 0x000000000000001F SET_DELAY 0x00000064 0x000000000000001F +DUNIT MEM 0xFED11170 0x000000000000001F SET_DELAY 0x00001388 0x000000000000000F FORCEODT_OFF Box Port Offset Mask Action Delay Value +DUNIT MEM 0xFED11170 0x0000000000000F00 SET_DELAY 0x00000032 0x0000000000000000 +DUNIT MEM 0xFED11170 0x0000000000001000 SET 0x00000000 0x0000000000001000 DoRegisterInit Box Port Offset Mask Action Delay Value +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000000078 RC0_R0 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000001078 RC1 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000002078 RC2 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000003578 RC3 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000004578 RC4 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000005578 RC5 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000040F78 RC4x +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000008B78 RC8 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x000000000000A278 RCA +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x000000000000B878 RCB +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x000000000000C078 RCC +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x000000000000E078 RCE +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x000000000000F478 RCF +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000032778 RC3X RELEASE_CKE Box Port Offset Mask Action Delay Value +DUNIT MEM 0xFED11170 0x000000000000000F SET_DELAY 0x00000064 0x000000000000000F +DUNIT MEM 0xFED11170 0x0000000000000010 SET_DELAY 0x00000064 0x0000000000000000 DoRegisterInitCke Box Port Offset Mask Action Delay Value +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000009C78 RC9 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x000000000000D478 RCD R0 PRE_A R0 NOP JedecInit Box Port Offset Mask Action Delay Value +DELAY: 400ns +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000020038 MR3_R0 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x000000000229F8C8 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000089168 MR6.Vref=1 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000089168 MR6.VrefValue +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000081168 MR6 Vref = 0 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000002236998 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000002236998 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x000000000223E998 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000004058 MR5 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x00000000022BB8A8 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000000048 MR4 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x00000000022BF8B8 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x000000000000E028 MR2 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x00000000022B18D8 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000000318 MR1 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x00000000022BFBE8 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x0000000000073008 MR0 +DUNIT MEM 0xFED11098 0x00000000FFFFFFFF SET_DELAY 0x00000032 0x00000000022CC8F8 R0 PRE_A R0 ZqCal Long FORCEODT_REL Box Port Offset Mask Action Delay Value +DUNIT MEM 0xFED11170 0x0000000000001000 SET_DELAY 0x00000032 0x0000000000000000 +DUNIT MEM 0xFED11170 0x0000000000000F00 SET 0x00000000 0x0000000000000000 CP 50 elapsedTime: 17(us) CP 51 elapsedTime: 66(us) CP 52 CP 53 elapsedTime: 12(us) CP 54 elapsedTime: 8(us) CP 55 CP 56 VocTraining R[0] = 0 R[1] = 255 C = 0 C0RxVocEn = 1 Pull Up = 27 Pull Down = 20 VREF Set RxVoc = 0 SL00:54:56:54:51 SL01:53:53:52:55 SL02:56:54:57:54 SL03:51:53:51:53 SL04:55:52:54:53 SL05:52:51:55:55 SL06:53:51:53:51 SL07:56:52:54:57 SL08:59:55:52:53 SL09:46:53:55:50 SL10:53:52:56:52 SL11:56:56:54:54 SL12:53:52:54:51 SL13:56:55:55:55 SL14:54:54:54:52 SL15:53:52:52:51 SL16:52:51:55:53 SL17:56:55:60:57 Set RxVoc = 1 SL00:57:59:56:54 SL01:56:56:54:57 SL02:58:57:59:57 SL03:54:56:54:56 SL04:57:55:57:55 SL05:54:52:58:57 SL06:55:54:56:54 SL07:58:54:56:59 SL08:61:58:54:56 SL09:48:56:57:53 SL10:55:54:58:55 SL11:58:58:56:56 SL12:56:55:56:53 SL13:58:57:57:58 SL14:57:56:57:54 SL15:56:54:54:54 SL16:56:54:58:56 SL17:59:58:62:59 Set RxVoc = 2 SL00:60:61:59:57 SL01:59:58:57:60 SL02:61:59:62:59 SL03:57:59:57:58 SL04:60:57:59:58 SL05:57:55:61:61 SL06:58:57:59:57 SL07:60:56:59:61 SL08:63:60:56:58 SL09:51:58:60:55 SL10:58:57:61:58 SL11:61:61:60:59 SL12:58:58:59:56 SL13:61:59:60:60 SL14:60:59:60:57 SL15:58:57:57:57 SL16:58:57:60:58 SL17:61:61:65:62 Set RxVoc = 3 SL00:62:64:62:60 SL01:61:61:59:63 SL02:63:62:64:62 SL03:60:62:60:61 SL04:62:60:62:61 SL05:60:58:63:63 SL06:60:59:62:60 SL07:62:59:62:64 SL08:65:63:59:60 SL09:54:61:63:58 SL10:60:60:63:60 SL11:63:64:62:62 SL12:61:60:62:58 SL13:64:62:62:63 SL14:62:61:62:60 SL15:61:60:60:59 SL16:60:59:62:60 SL17:64:62:67:64 Set RxVoc = 4 SL00:65:67:65:63 SL01:65:64:63:65 SL02:66:65:67:65 SL03:63:65:63:63 SL04:65:63:65:64 SL05:63:61:67:66 SL06:64:62:65:63 SL07:66:62:64:66 SL08:68:66:62:63 SL09:58:64:66:62 SL10:63:63:66:63 SL11:66:66:65:65 SL12:64:63:65:62 SL13:66:65:65:66 SL14:66:65:65:63 SL15:63:63:63:62 SL16:64:62:66:64 SL17:66:65:70:67 Set RxVoc = 5 SL00:68:70:68:66 SL01:68:67:65:68 SL02:68:68:70:68 SL03:66:68:66:67 SL04:68:66:67:66 SL05:66:64:70:69 SL06:67:66:68:66 SL07:68:65:66:68 SL08:71:69:65:66 SL09:61:67:68:65 SL10:66:66:69:66 SL11:69:69:68:68 SL12:68:67:68:64 SL13:70:68:68:68 SL14:68:68:68:65 SL15:67:66:66:65 SL16:66:65:69:66 SL17:69:68:72:69 Set RxVoc = 6 SL00:71:73:72:69 SL01:71:70:69:72 SL02:72:71:74:71 SL03:69:72:70:70 SL04:71:69:71:70 SL05:70:68:73:72 SL06:70:69:71:69 SL07:71:68:69:72 SL08:74:72:68:69 SL09:65:70:72:68 SL10:70:70:72:70 SL11:72:72:71:71 SL12:72:71:72:68 SL13:73:71:72:72 SL14:72:71:71:69 SL15:70:70:69:68 SL16:70:68:72:70 SL17:72:71:75:72 Set RxVoc = 7 SL00:74:75:75:73 SL01:75:73:72:74 SL02:74:74:76:74 SL03:73:75:73:73 SL04:74:72:73:72 SL05:72:71:75:75 SL06:73:72:74:73 SL07:74:71:71:75 SL08:76:75:71:72 SL09:68:73:74:71 SL10:72:73:75:73 SL11:75:75:74:74 SL12:74:75:75:71 SL13:75:74:75:75 SL14:75:74:74:72 SL15:73:73:72:71 SL16:72:72:75:72 SL17:75:74:77:75 TargetVref 0=56 1=56 2=57 3=54 4=56 5=55 6=53 7=57 8=60 9=56 10=56 11=57 12=54 13=56 14=55 15=53 16=57 17=60 VREF table VREF46: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: 00:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF47: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF48: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: 01:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF49: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF50: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:00: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF51: --:--:--:00: --:--:--:--: --:--:--:--: 00:--:00:--: --:--:--:--: --:00:--:--: --:00:--:00: --:--:--:--: --:--:--:--: 02:--:--:--: --:--:--:--: --:--:--:--: --:--:--:00: --:--:--:--: --:--:--:--: --:--:--:00: --:00:--:--: --:--:--:--: VREF52: --:--:--:--: --:--:00:--: --:--:--:--: --:--:--:--: --:00:--:--: 00:01:--:--: --:--:--:--: --:00:--:--: --:--:00:--: --:--:--:--: --:00:--:00: --:--:--:--: --:00:--:--: --:--:--:--: --:--:--:00: --:00:00:--: 00:--:--:--: --:--:--:--: VREF53: --:--:--:--: 00:00:--:--: --:--:--:--: --:00:--:00: --:--:--:00: --:--:--:--: 00:--:00:--: --:--:--:--: --:--:--:00: --:00:--:01: 00:--:--:--: --:--:--:--: 00:--:--:01: --:--:--:--: --:--:--:--: 00:--:--:--: --:--:--:00: --:--:--:--: VREF54: 00:--:00:01: --:--:01:--: --:00:--:00: 01:--:01:--: --:--:00:--: 01:--:--:--: --:01:--:01: --:01:00:--: --:--:01:--: 03:--:--:--: --:01:--:--: --:--:00:00: --:--:00:--: --:--:--:--: 00:00:00:01: --:01:01:01: --:01:--:--: --:--:--:--: VREF55: --:--:--:--: --:--:--:00: --:--:--:--: --:--:--:--: 00:01:--:01: --:02:00:00: 01:--:--:--: --:--:--:--: --:00:--:--: --:--:00:02: 01:--:--:01: --:--:--:--: --:01:--:--: --:00:00:00: --:--:--:--: --:--:--:--: --:--:00:--: --:00:--:--: VREF56: --:00:01:--: 01:01:--:--: 00:--:--:--: --:01:--:01: --:--:--:--: --:--:--:--: --:--:01:--: 00:02:01:--: --:--:02:01: --:01:--:--: --:--:00:--: 00:00:01:01: 01:--:01:02: 00:--:--:--: --:01:--:--: 01:--:--:--: 01:--:--:01: 00:--:--:--: VREF57: 01:--:--:02: --:--:02:01: --:01:00:01: 02:--:02:--: 01:02:01:--: 02:--:--:01: --:02:--:02: --:--:--:00: --:--:--:--: --:--:01:--: --:02:--:--: --:--:--:--: --:--:--:--: --:01:01:--: 01:--:01:02: --:02:02:02: --:02:--:--: --:--:--:00: VREF58: --:--:--:--: --:02:--:--: 01:--:--:--: --:--:--:02: --:--:--:02: --:03:01:--: 02:--:--:--: 01:--:--:--: --:01:--:02: 04:02:--:03: 02:--:01:02: 01:01:--:--: 02:02:--:03: 01:--:--:01: --:--:--:--: 02:--:--:--: 02:--:01:02: --:01:--:--: VREF59: --:01:02:--: 02:--:03:--: --:02:01:02: --:02:--:--: --:--:02:--: --:--:--:--: --:03:02:--: --:03:02:01: 00:--:03:--: --:--:--:--: --:--:--:--: --:--:--:02: --:--:02:--: --:02:--:--: --:02:--:--: --:--:--:03: --:03:--:--: 01:--:--:01: VREF60: 02:--:--:03: --:--:--:02: --:--:--:--: 03:--:03:--: 02:03:--:--: 03:--:--:--: 03:--:--:03: 02:--:--:--: --:02:--:03: --:--:02:--: 03:03:--:03: --:--:02:--: --:03:--:--: --:--:02:02: 02:--:02:03: --:03:03:--: 03:--:02:03: --:--:00:--: VREF61: --:02:--:--: 03:03:--:--: 02:--:--:--: --:--:--:03: --:--:--:03: --:04:02:02: --:--:--:--: --:--:--:02: 01:--:--:--: --:03:--:--: --:--:02:--: 02:02:--:--: 03:--:--:--: 02:--:--:--: --:03:--:--: 03:--:--:--: --:--:--:--: 02:02:--:--: VREF62: 03:--:03:--: --:--:--:--: --:03:02:03: --:03:--:--: 03:--:03:--: --:--:--:--: --:04:03:--: 03:04:03:--: --:--:04:--: --:--:--:04: --:--:--:--: --:--:03:03: --:--:03:04: --:03:03:--: 03:--:03:--: --:--:--:04: --:04:03:--: --:03:01:02: VREF63: --:--:--:04: --:--:04:03: 03:--:--:--: 04:--:04:04: --:04:--:--: 04:--:03:03: --:--:--:04: --:--:--:--: 02:03:--:04: --:--:03:--: 04:04:03:04: 03:--:--:--: --:04:--:--: --:--:--:03: --:--:--:04: 04:04:04:--: --:--:--:--: --:--:--:--: VREF64: --:03:--:--: --:04:--:--: --:--:03:--: --:--:--:--: --:--:--:04: --:--:--:--: 04:--:--:--: --:--:04:03: --:--:--:--: --:04:--:--: --:--:--:--: --:03:--:--: 04:--:--:--: 03:--:--:--: --:--:--:--: --:--:--:--: 04:--:--:04: 03:--:--:03: VREF65: 04:--:04:--: 04:--:--:04: --:04:--:04: --:04:--:--: 04:--:04:--: --:--:--:--: --:--:04:--: --:--:--:--: 03:--:--:--: --:--:--:--: --:--:--:--: --:--:04:04: --:--:04:--: --:04:04:--: --:04:04:--: --:--:--:--: --:--:--:--: --:04:02:--: VREF66: --:--:--:--: --:--:--:--: 04:--:--:--: --:--:--:--: --:--:--:--: --:--:--:04: --:--:--:--: 04:--:--:04: --:04:--:--: --:--:04:--: --:--:04:--: 04:04:--:--: --:--:--:--: 04:--:--:04: 04:--:--:--: --:--:--:--: --:--:04:--: 04:--:--:--: VREF67: --:04:--:--: --:--:--:--: --:--:04:--: --:--:--:--: --:--:--:--: --:--:04:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:03:04: VREF68: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: 04:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF69: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF70: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:04:--: VREF71: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF72: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF73: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF74: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF75: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF76: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VREF77: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: --:--:--:--: VOC SL00:01:00:01:02 SL01:01:01:02:01 SL02:01:01:00:01 SL03:01:00:01:00 SL04:01:02:01:01 SL05:01:02:00:00 SL06:00:01:00:01 SL07:01:02:01:00 SL08:01:02:03:03 SL09:04:01:01:02 SL10:01:02:00:01 SL11:01:01:01:01 SL12:00:01:00:01 SL13:00:01:01:00 SL14:00:01:00:01 SL15:00:01:01:01 SL16:02:02:01:02 SL17:02:02:00:01 VREF SL00:57:56:56:57 SL01:56:56:57:57 SL02:58:57:57:57 SL03:54:53:54:53 SL04:57:58:56:55 SL05:54:55:56:55 SL06:53:54:54:54 SL07:58:57:56:57 SL08:61:60:59:61 SL09:58:55:57:55 SL10:56:57:56:55 SL11:58:58:57:56 SL12:53:55:53:52 SL13:56:57:57:55 SL14:54:56:55:54 SL15:53:54:54:54 SL16:58:57:58:58 SL17:61:60:60:59 elapsedTime: 5551540(us) CP 57 START_ReceiveEnable Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ---------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- RecEnDelay 00 00 00 00 00 12 05 59 - 2 - 5 -- 1979 RecEnDelay 00 00 01 00 00 12 05 26 - 1 - 5 -- 1946 RecEnDelay 00 00 02 00 00 12 05 02 - 3 - 5 -- 1922 RecEnDelay 00 00 03 00 00 12 05 41 - 0 - 5 -- 1897 RecEnDelay 00 00 04 00 00 12 04 21 - 1 - 4 -- 1877 RecEnDelay 00 00 05 00 00 12 05 07 - 3 - 5 -- 1927 RecEnDelay 00 00 06 00 00 12 05 18 - 1 - 5 -- 1938 RecEnDelay 00 00 07 00 00 12 06 42 - 0 - 6 -- 1962 RecEnDelay 00 00 08 00 00 12 04 05 - 3 - 4 -- 1861 RecEnDelay 00 00 09 00 00 12 05 57 - 2 - 5 -- 1977 RecEnDelay 00 00 10 00 00 12 06 38 - 0 - 6 -- 1958 RecEnDelay 00 00 11 00 00 12 05 04 - 3 - 5 -- 1924 RecEnDelay 00 00 12 00 00 12 04 48 - 2 - 4 -- 1904 RecEnDelay 00 00 13 00 00 12 04 22 - 1 - 4 -- 1878 RecEnDelay 00 00 14 00 00 12 04 53 - 2 - 4 -- 1909 RecEnDelay 00 00 15 00 00 12 05 22 - 1 - 5 -- 1942 RecEnDelay 00 00 16 00 00 12 05 49 - 2 - 5 -- 1969 RecEnDelay 00 00 17 00 00 12 04 07 - 3 - 4 -- 1863 S00 S01 S02 S03 S04 S05 S06 S07 S08 S09 S10 S11 S12 S13 S14 S15 S16 S17 R0 443 410 386 361 341 391 402 426 325 441 422 388 368 342 373 406 433 327 elapsedTime: 786714(us) CP 58 STOP_ReceiveEnable START_EarlyMprRead CH00 RxVref = 000 CH00 RxVref = 002 CH00 RxVref = 004 CH00 RxVref = 006 CH00 RxVref = 008 CH00 RxVref = 010 CH00 RxVref = 012 CH00 RxVref = 014 CH00 RxVref = 016 CH00 RxVref = 018 CH00 RxVref = 020 CH00 RxVref = 022 CH00 RxVref = 024 CH00 RxVref = 026 CH00 RxVref = 028 CH00 RxVref = 030 CH00 RxVref = 032 CH00 RxVref = 034 CH00 RxVref = 036 CH00 RxVref = 038 CH00 RxVref = 040 CH00 RxVref = 042 CH00 RxVref = 044 CH00 RxVref = 046 CH00 RxVref = 048 CH00 RxVref = 050 CH00 RxVref = 052 CH00 RxVref = 054 CH00 RxVref = 056 CH00 RxVref = 058 CH00 RxVref = 060 CH00 RxVref = 062 CH00 RxVref = 064 CH00 RxVref = 066 CH00 RxVref = 068 CH00 RxVref = 070 CH00 RxVref = 072 CH00 RxVref = 074 CH00 RxVref = 076 CH00 RxVref = 078 CH00 RxVref = 080 CH00 RxVref = 082 CH00 RxVref = 084 CH00 RxVref = 086 CH00 RxVref = 088 CH00 RxVref = 090 CH00 RxVref = 092 CH00 RxVref = 094 C0.R0.S0: DQ7, DQ6, DQ5, DQ4, DQ3, DQ2, DQ1, DQ0, Cx: 28 Cy: 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S1: DQ15, DQ14, DQ13, DQ12, DQ11, DQ10, DQ9, DQ8, Cx: 34 Cy: 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S2: DQ23, DQ22, DQ21, DQ20, DQ19, DQ18, DQ17, DQ16, Cx: 27 Cy: 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S3: DQ31, DQ30, DQ29, DQ28, DQ27, DQ26, DQ25, DQ24, Cx: 28 Cy: 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S4: DQ39, DQ38, DQ37, DQ36, DQ35, DQ34, DQ33, DQ32, Cx: 27 Cy: 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S5: DQ47, DQ46, DQ45, DQ44, DQ43, DQ42, DQ41, DQ40, Cx: 26 Cy: 68 * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S6: DQ55, DQ54, DQ53, DQ52, DQ51, DQ50, DQ49, DQ48, Cx: 29 Cy: 65 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S7: DQ63, DQ62, DQ61, DQ60, DQ59, DQ58, DQ57, DQ56, Cx: 30 Cy: 70 * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S8: DQ71, DQ70, DQ69, DQ68, DQ67, DQ66, DQ65, DQ64, Cx: 27 Cy: 70 * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S9: DQ79, DQ78, DQ77, DQ76, DQ75, DQ74, DQ73, DQ72, Cx: 28 Cy: 68 * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S10: DQ87, DQ86, DQ85, DQ84, DQ83, DQ82, DQ81, DQ80, Cx: 26 Cy: 66 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S11: DQ95, DQ94, DQ93, DQ92, DQ91, DQ90, DQ89, DQ88, Cx: 25 Cy: 64 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S12: DQ103, DQ102, DQ101, DQ100, DQ99, DQ98, DQ97, DQ96, Cx: 25 Cy: 62 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S13: DQ111, DQ110, DQ109, DQ108, DQ107, DQ106, DQ105, DQ104, Cx: 26 Cy: 65 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S14: DQ119, DQ118, DQ117, DQ116, DQ115, DQ114, DQ113, DQ112, Cx: 37 Cy: 68 * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S15: DQ127, DQ126, DQ125, DQ124, DQ123, DQ122, DQ121, DQ120, Cx: 21 Cy: 62 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S16: DQ135, DQ134, DQ133, DQ132, DQ131, DQ130, DQ129, DQ128, Cx: 23 Cy: 65 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C0.R0.S17: DQ143, DQ142, DQ141, DQ140, DQ139, DQ138, DQ137, DQ136, Cx: 23 Cy: 67 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * + * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ----------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- RxDqsPDelay 00 00 00 00 00 -- -- 28 - - - - 0068 0028 RxDqsPDelay 00 00 01 00 00 -- -- 34 - - - - 0066 0034 RxDqsPDelay 00 00 02 00 00 -- -- 27 - - - - 0064 0027 RxDqsPDelay 00 00 03 00 00 -- -- 28 - - - - 0062 0028 RxDqsPDelay 00 00 04 00 00 -- -- 27 - - - - 0065 0027 RxDqsPDelay 00 00 05 00 00 -- -- 26 - - - - 0068 0026 RxDqsPDelay 00 00 06 00 00 -- -- 29 - - - - 0062 0029 RxDqsPDelay 00 00 07 00 00 -- -- 30 - - - - 0065 0030 RxDqsPDelay 00 00 08 00 00 -- -- 27 - - - - 0067 0027 RxDqsPDelay 00 00 09 00 00 -- -- 28 - - - - 0068 0028 RxDqsPDelay 00 00 10 00 00 -- -- 26 - - - - 0066 0026 RxDqsPDelay 00 00 11 00 00 -- -- 25 - - - - 0064 0025 RxDqsPDelay 00 00 12 00 00 -- -- 25 - - - - 0062 0025 RxDqsPDelay 00 00 13 00 00 -- -- 26 - - - - 0065 0026 RxDqsPDelay 00 00 14 00 00 -- -- 37 - - - - 0068 0037 RxDqsPDelay 00 00 15 00 00 -- -- 21 - - - - 0062 0021 RxDqsPDelay 00 00 16 00 00 -- -- 23 - - - - 0065 0023 RxDqsPDelay 00 00 17 00 00 -- -- 23 - - - - 0067 0023 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ----------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- RxDqsNDelay 00 00 00 00 00 -- -- 28 - - - - 0068 0028 RxDqsNDelay 00 00 01 00 00 -- -- 34 - - - - 0066 0034 RxDqsNDelay 00 00 02 00 00 -- -- 27 - - - - 0064 0027 RxDqsNDelay 00 00 03 00 00 -- -- 28 - - - - 0062 0028 RxDqsNDelay 00 00 04 00 00 -- -- 27 - - - - 0065 0027 RxDqsNDelay 00 00 05 00 00 -- -- 26 - - - - 0068 0026 RxDqsNDelay 00 00 06 00 00 -- -- 29 - - - - 0062 0029 RxDqsNDelay 00 00 07 00 00 -- -- 30 - - - - 0065 0030 RxDqsNDelay 00 00 08 00 00 -- -- 27 - - - - 0067 0027 RxDqsNDelay 00 00 09 00 00 -- -- 28 - - - - 0068 0028 RxDqsNDelay 00 00 10 00 00 -- -- 26 - - - - 0066 0026 RxDqsNDelay 00 00 11 00 00 -- -- 25 - - - - 0064 0025 RxDqsNDelay 00 00 12 00 00 -- -- 25 - - - - 0062 0025 RxDqsNDelay 00 00 13 00 00 -- -- 26 - - - - 0065 0026 RxDqsNDelay 00 00 14 00 00 -- -- 37 - - - - 0068 0037 RxDqsNDelay 00 00 15 00 00 -- -- 21 - - - - 0062 0021 RxDqsNDelay 00 00 16 00 00 -- -- 23 - - - - 0065 0023 RxDqsNDelay 00 00 17 00 00 -- -- 23 - - - - 0067 0023 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------------ -- -- -- -- -- --- --- --- - --- --- --- ---- ---- RxDqBitDelay 00 00 00 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 00 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 00 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 00 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 01 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 01 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 01 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 01 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 02 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 02 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 02 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 02 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 03 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 03 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 03 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 03 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 04 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 04 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 04 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 04 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 05 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 05 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 05 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 05 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 06 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 06 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 06 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 06 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 07 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 07 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 07 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 07 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 08 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 08 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 08 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 08 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 09 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 09 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 09 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 09 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 10 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 10 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 10 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 10 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 11 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 11 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 11 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 11 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 12 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 12 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 12 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 12 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 13 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 13 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 13 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 13 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 14 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 14 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 14 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 14 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 15 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 15 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 15 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 15 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 16 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 16 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 16 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 16 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 17 00 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 17 01 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 17 02 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 17 03 00 -- -- 991 - - - - -- 0991 elapsedTime: 19247782(us) CP 57 DnvNibbleTrainingHook CP 59 STOP_EarlyMprRead START_FineWriteLeveling Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ---------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- TxDqsDelay 00 00 00 00 00 -- 04 57 - 2 - 4 -- 0377 TxDqsDelay 00 00 01 00 00 -- 04 52 - 2 - 4 -- 0372 TxDqsDelay 00 00 02 00 00 -- 04 31 - 1 - 4 -- 0351 TxDqsDelay 00 00 03 00 00 -- 04 20 - 1 - 4 -- 0340 TxDqsDelay 00 00 04 00 00 -- 04 47 - 0 - 4 -- 0303 TxDqsDelay 00 00 05 00 00 -- 03 53 - 2 - 3 -- 0309 TxDqsDelay 00 00 06 00 00 -- 04 20 - 1 - 4 -- 0340 TxDqsDelay 00 00 07 00 00 -- 05 36 - 0 - 5 -- 0356 TxDqsDelay 00 00 08 00 00 -- 03 55 - 2 - 3 -- 0311 TxDqsDelay 00 00 09 00 00 -- 04 54 - 2 - 4 -- 0374 TxDqsDelay 00 00 10 00 00 -- 05 40 - 0 - 5 -- 0360 TxDqsDelay 00 00 11 00 00 -- 04 25 - 1 - 4 -- 0345 TxDqsDelay 00 00 12 00 00 -- 04 10 - 3 - 4 -- 0330 TxDqsDelay 00 00 13 00 00 -- 03 49 - 2 - 3 -- 0305 TxDqsDelay 00 00 14 00 00 -- 04 03 - 3 - 4 -- 0323 TxDqsDelay 00 00 15 00 00 -- 04 16 - 1 - 4 -- 0336 TxDqsDelay 00 00 16 00 00 -- 05 34 - 0 - 5 -- 0354 TxDqsDelay 00 00 17 00 00 -- 04 47 - 0 - 4 -- 0303 S00 S01 S02 S03 S04 S05 S06 S07 S08 S09 S10 S11 S12 S13 S14 S15 S16 S17 R0 377 372 351 340 303 309 340 356 311 374 360 345 330 305 323 336 354 303 elapsedTime: 681748(us) CP 60 STOP_FineWriteLeveling START_CoarseWriteLeveling Dq: 336 Dq: 327 Dq: 309 Dq: 294 Dq: 259 Dq: 266 Dq: 295 Dq: 310 Dq: 272 Dq: 331 Dq: 319 Dq: 306 Dq: 285 Dq: 266 Dq: 274 Dq: 301 Dq: 315 Dq: 266 Enabling R0 S00 S01 S02 S03 S04 S05 S06 S07 S08 S09 S10 S11 S12 S13 S14 S15 S16 S17 R0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Failing 0x00000000 Enabling R0 S00 S01 S02 S03 S04 S05 S06 S07 S08 S09 S10 S11 S12 S13 S14 S15 S16 S17 R0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Failing 0x00000000 Enabling R0 S00 S01 S02 S03 S04 S05 S06 S07 S08 S09 S10 S11 S12 S13 S14 S15 S16 S17 R0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Failing 0x00000000 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ---------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- TxDqsDelay 00 00 00 00 00 -- 04 57 - 2 - 4 -- 0377 TxDqsDelay 00 00 01 00 00 -- 04 52 - 2 - 4 -- 0372 TxDqsDelay 00 00 02 00 00 -- 04 31 - 1 - 4 -- 0351 TxDqsDelay 00 00 03 00 00 -- 04 20 - 1 - 4 -- 0340 TxDqsDelay 00 00 04 00 00 -- 04 47 - 0 - 4 -- 0303 TxDqsDelay 00 00 05 00 00 -- 03 53 - 2 - 3 -- 0309 TxDqsDelay 00 00 06 00 00 -- 04 20 - 1 - 4 -- 0340 TxDqsDelay 00 00 07 00 00 -- 05 36 - 0 - 5 -- 0356 TxDqsDelay 00 00 08 00 00 -- 03 55 - 2 - 3 -- 0311 TxDqsDelay 00 00 09 00 00 -- 04 54 - 2 - 4 -- 0374 TxDqsDelay 00 00 10 00 00 -- 05 40 - 0 - 5 -- 0360 TxDqsDelay 00 00 11 00 00 -- 04 25 - 1 - 4 -- 0345 TxDqsDelay 00 00 12 00 00 -- 04 10 - 3 - 4 -- 0330 TxDqsDelay 00 00 13 00 00 -- 03 49 - 2 - 3 -- 0305 TxDqsDelay 00 00 14 00 00 -- 04 03 - 3 - 4 -- 0323 TxDqsDelay 00 00 15 00 00 -- 04 16 - 1 - 4 -- 0336 TxDqsDelay 00 00 16 00 00 -- 05 34 - 0 - 5 -- 0354 TxDqsDelay 00 00 17 00 00 -- 04 47 - 0 - 4 -- 0303 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly --------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- TxDqDelay 00 00 00 00 00 -- 04 16 - 1 - 4 0040 0336 TxDqDelay 00 00 01 00 00 -- 04 07 - 3 - 4 0040 0327 TxDqDelay 00 00 02 00 00 -- 03 53 - 2 - 3 0040 0309 TxDqDelay 00 00 03 00 00 -- 04 38 - 0 - 4 0040 0294 TxDqDelay 00 00 04 00 00 -- 03 03 - 3 - 3 0040 0259 TxDqDelay 00 00 05 00 00 -- 03 10 - 3 - 3 0040 0266 TxDqDelay 00 00 06 00 00 -- 04 39 - 0 - 4 0040 0295 TxDqDelay 00 00 07 00 00 -- 03 54 - 2 - 3 0040 0310 TxDqDelay 00 00 08 00 00 -- 03 16 - 1 - 3 0040 0272 TxDqDelay 00 00 09 00 00 -- 04 11 - 3 - 4 0040 0331 TxDqDelay 00 00 10 00 00 -- 03 63 - 2 - 3 0040 0319 TxDqDelay 00 00 11 00 00 -- 03 50 - 2 - 3 0040 0306 TxDqDelay 00 00 12 00 00 -- 03 29 - 1 - 3 0040 0285 TxDqDelay 00 00 13 00 00 -- 03 10 - 3 - 3 0040 0266 TxDqDelay 00 00 14 00 00 -- 03 18 - 1 - 3 0040 0274 TxDqDelay 00 00 15 00 00 -- 04 45 - 0 - 4 0040 0301 TxDqDelay 00 00 16 00 00 -- 03 59 - 2 - 3 0040 0315 TxDqDelay 00 00 17 00 00 -- 03 10 - 3 - 3 0040 0266 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------------ -- -- -- -- -- --- --- --- - --- --- --- ---- ---- TxDqDrvDelay 00 00 00 00 00 -- 04 16 - 1 - 4 -- 0336 TxDqDrvDelay 00 00 01 00 00 -- 04 07 - 3 - 4 -- 0327 TxDqDrvDelay 00 00 02 00 00 -- 03 53 - 2 - 3 -- 0309 TxDqDrvDelay 00 00 03 00 00 -- 04 38 - 0 - 4 -- 0294 TxDqDrvDelay 00 00 04 00 00 -- 03 03 - 3 - 3 -- 0259 TxDqDrvDelay 00 00 05 00 00 -- 03 10 - 3 - 3 -- 0266 TxDqDrvDelay 00 00 06 00 00 -- 04 39 - 0 - 4 -- 0295 TxDqDrvDelay 00 00 07 00 00 -- 03 54 - 2 - 3 -- 0310 TxDqDrvDelay 00 00 08 00 00 -- 03 16 - 1 - 3 -- 0272 TxDqDrvDelay 00 00 09 00 00 -- 04 11 - 3 - 4 -- 0331 TxDqDrvDelay 00 00 10 00 00 -- 03 63 - 2 - 3 -- 0319 TxDqDrvDelay 00 00 11 00 00 -- 03 50 - 2 - 3 -- 0306 TxDqDrvDelay 00 00 12 00 00 -- 03 29 - 1 - 3 -- 0285 TxDqDrvDelay 00 00 13 00 00 -- 03 10 - 3 - 3 -- 0266 TxDqDrvDelay 00 00 14 00 00 -- 03 18 - 1 - 3 -- 0274 TxDqDrvDelay 00 00 15 00 00 -- 04 45 - 0 - 4 -- 0301 TxDqDrvDelay 00 00 16 00 00 -- 03 59 - 2 - 3 -- 0315 TxDqDrvDelay 00 00 17 00 00 -- 03 10 - 3 - 3 -- 0266 S00 S01 S02 S03 S04 S05 S06 S07 S08 S09 S10 S11 S12 S13 S14 S15 S16 S17 R0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 elapsedTime: 2976713(us) CP 57 DnvNibbleTrainingExitHook CP 62 STOP_CoarseWriteLeveling START_ReadTraining bSweepFlags = 0x01 aSweepFlags = 0x13 2nd Timing: 2nd Timing: 2nd Timing: 2nd Timing: 2nd Timing: Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ----------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- RxDqsPDelay 00 00 00 00 00 -- -- 29 - - - - 0063 0029 RxDqsPDelay 00 00 01 00 00 -- -- 33 - - - - 0062 0033 RxDqsPDelay 00 00 02 00 00 -- -- 25 - - - - 0063 0025 RxDqsPDelay 00 00 03 00 00 -- -- 29 - - - - 0061 0029 RxDqsPDelay 00 00 04 00 00 -- -- 26 - - - - 0063 0026 RxDqsPDelay 00 00 05 00 00 -- -- 26 - - - - 0062 0026 RxDqsPDelay 00 00 06 00 00 -- -- 28 - - - - 0060 0028 RxDqsPDelay 00 00 07 00 00 -- -- 27 - - - - 0064 0027 RxDqsPDelay 00 00 08 00 00 -- -- 25 - - - - 0067 0025 RxDqsPDelay 00 00 09 00 00 -- -- 26 - - - - 0063 0026 RxDqsPDelay 00 00 10 00 00 -- -- 24 - - - - 0062 0024 RxDqsPDelay 00 00 11 00 00 -- -- 22 - - - - 0063 0022 RxDqsPDelay 00 00 12 00 00 -- -- 23 - - - - 0061 0023 RxDqsPDelay 00 00 13 00 00 -- -- 25 - - - - 0063 0025 RxDqsPDelay 00 00 14 00 00 -- -- 37 - - - - 0062 0037 RxDqsPDelay 00 00 15 00 00 -- -- 19 - - - - 0060 0019 RxDqsPDelay 00 00 16 00 00 -- -- 20 - - - - 0064 0020 RxDqsPDelay 00 00 17 00 00 -- -- 20 - - - - 0067 0020 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ----------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- RxDqsNDelay 00 00 00 00 00 -- -- 32 - - - - 0063 0032 RxDqsNDelay 00 00 01 00 00 -- -- 33 - - - - 0062 0033 RxDqsNDelay 00 00 02 00 00 -- -- 26 - - - - 0063 0026 RxDqsNDelay 00 00 03 00 00 -- -- 29 - - - - 0061 0029 RxDqsNDelay 00 00 04 00 00 -- -- 29 - - - - 0063 0029 RxDqsNDelay 00 00 05 00 00 -- -- 30 - - - - 0062 0030 RxDqsNDelay 00 00 06 00 00 -- -- 29 - - - - 0060 0029 RxDqsNDelay 00 00 07 00 00 -- -- 29 - - - - 0064 0029 RxDqsNDelay 00 00 08 00 00 -- -- 26 - - - - 0067 0026 RxDqsNDelay 00 00 09 00 00 -- -- 28 - - - - 0063 0028 RxDqsNDelay 00 00 10 00 00 -- -- 25 - - - - 0062 0025 RxDqsNDelay 00 00 11 00 00 -- -- 26 - - - - 0063 0026 RxDqsNDelay 00 00 12 00 00 -- -- 25 - - - - 0061 0025 RxDqsNDelay 00 00 13 00 00 -- -- 26 - - - - 0063 0026 RxDqsNDelay 00 00 14 00 00 -- -- 40 - - - - 0062 0040 RxDqsNDelay 00 00 15 00 00 -- -- 20 - - - - 0060 0020 RxDqsNDelay 00 00 16 00 00 -- -- 20 - - - - 0064 0020 RxDqsNDelay 00 00 17 00 00 -- -- 22 - - - - 0067 0022 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------------ -- -- -- -- -- --- --- --- - --- --- --- ---- ---- RxDqBitDelay 00 00 00 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 00 01 00 -- -- 639 - - - - -- 0639 RxDqBitDelay 00 00 00 02 00 -- -- 495 - - - - -- 0495 RxDqBitDelay 00 00 00 03 00 -- -- 415 - - - - -- 0415 RxDqBitDelay 00 00 01 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 01 01 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 01 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 01 03 00 -- -- 831 - - - - -- 0831 RxDqBitDelay 00 00 02 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 02 01 00 -- -- 879 - - - - -- 0879 RxDqBitDelay 00 00 02 02 00 -- -- 735 - - - - -- 0735 RxDqBitDelay 00 00 02 03 00 -- -- 767 - - - - -- 0767 RxDqBitDelay 00 00 03 00 00 -- -- 767 - - - - -- 0767 RxDqBitDelay 00 00 03 01 00 -- -- 479 - - - - -- 0479 RxDqBitDelay 00 00 03 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 03 03 00 -- -- 383 - - - - -- 0383 RxDqBitDelay 00 00 04 00 00 -- -- 607 - - - - -- 0607 RxDqBitDelay 00 00 04 01 00 -- -- 559 - - - - -- 0559 RxDqBitDelay 00 00 04 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 04 03 00 -- -- 687 - - - - -- 0687 RxDqBitDelay 00 00 05 00 00 -- -- 543 - - - - -- 0543 RxDqBitDelay 00 00 05 01 00 -- -- 319 - - - - -- 0319 RxDqBitDelay 00 00 05 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 05 03 00 -- -- 431 - - - - -- 0431 RxDqBitDelay 00 00 06 00 00 -- -- 495 - - - - -- 0495 RxDqBitDelay 00 00 06 01 00 -- -- 479 - - - - -- 0479 RxDqBitDelay 00 00 06 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 06 03 00 -- -- 655 - - - - -- 0655 RxDqBitDelay 00 00 07 00 00 -- -- 847 - - - - -- 0847 RxDqBitDelay 00 00 07 01 00 -- -- 575 - - - - -- 0575 RxDqBitDelay 00 00 07 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 07 03 00 -- -- 479 - - - - -- 0479 RxDqBitDelay 00 00 08 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 08 01 00 -- -- 543 - - - - -- 0543 RxDqBitDelay 00 00 08 02 00 -- -- 1007 - - - - -- 1007 RxDqBitDelay 00 00 08 03 00 -- -- 703 - - - - -- 0703 RxDqBitDelay 00 00 09 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 09 01 00 -- -- 639 - - - - -- 0639 RxDqBitDelay 00 00 09 02 00 -- -- 607 - - - - -- 0607 RxDqBitDelay 00 00 09 03 00 -- -- 735 - - - - -- 0735 RxDqBitDelay 00 00 10 00 00 -- -- 831 - - - - -- 0831 RxDqBitDelay 00 00 10 01 00 -- -- 623 - - - - -- 0623 RxDqBitDelay 00 00 10 02 00 -- -- 783 - - - - -- 0783 RxDqBitDelay 00 00 10 03 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 11 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 11 01 00 -- -- 879 - - - - -- 0879 RxDqBitDelay 00 00 11 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 11 03 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 12 00 00 -- -- 591 - - - - -- 0591 RxDqBitDelay 00 00 12 01 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 12 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 12 03 00 -- -- 687 - - - - -- 0687 RxDqBitDelay 00 00 13 00 00 -- -- 719 - - - - -- 0719 RxDqBitDelay 00 00 13 01 00 -- -- 591 - - - - -- 0591 RxDqBitDelay 00 00 13 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 13 03 00 -- -- 847 - - - - -- 0847 RxDqBitDelay 00 00 14 00 00 -- -- 463 - - - - -- 0463 RxDqBitDelay 00 00 14 01 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 14 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 14 03 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 15 00 00 -- -- 815 - - - - -- 0815 RxDqBitDelay 00 00 15 01 00 -- -- 703 - - - - -- 0703 RxDqBitDelay 00 00 15 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 15 03 00 -- -- 943 - - - - -- 0943 RxDqBitDelay 00 00 16 00 00 -- -- 1007 - - - - -- 1007 RxDqBitDelay 00 00 16 01 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 16 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 16 03 00 -- -- 991 - - - - -- 0991 RxDqBitDelay 00 00 17 00 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 17 01 00 -- -- 863 - - - - -- 0863 RxDqBitDelay 00 00 17 02 00 -- -- 1023 - - - - -- 1023 RxDqBitDelay 00 00 17 03 00 -- -- 1023 - - - - -- 1023 S00 S01 S02 S03 S04 S05 S06 S07 S08 S09 S10 S11 S12 S13 S14 S15 S16 S17 R0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 elapsedTime: 44177981(us) CP 57 DnvNibbleTrainingHook CP 61 STOP_ReadTraining START_WriteTraining TXEQ Final Value = -1 bSweepFlags = 0x01 aSweepFlags = 0x13 bSweepFlags = 0x09 aSweepFlags = 0x1B Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly --------- -- -- -- -- -- --- --- --- - --- --- --- ---- ---- TxDqDelay 00 00 00 00 00 -- 04 10 - 3 - 4 0037 0330 TxDqDelay 00 00 01 00 00 -- 03 62 - 2 - 3 0038 0318 TxDqDelay 00 00 02 00 00 -- 03 48 - 2 - 3 0037 0304 TxDqDelay 00 00 03 00 00 -- 03 30 - 1 - 3 0039 0286 TxDqDelay 00 00 04 00 00 -- 02 60 - 2 - 2 0039 0252 TxDqDelay 00 00 05 00 00 -- 03 05 - 3 - 3 0039 0261 TxDqDelay 00 00 06 00 00 -- 03 30 - 1 - 3 0038 0286 TxDqDelay 00 00 07 00 00 -- 04 47 - 0 - 4 0038 0303 TxDqDelay 00 00 08 00 00 -- 03 12 - 3 - 3 0039 0268 TxDqDelay 00 00 09 00 00 -- 04 05 - 3 - 4 0038 0325 TxDqDelay 00 00 10 00 00 -- 03 57 - 2 - 3 0039 0313 TxDqDelay 00 00 11 00 00 -- 04 43 - 0 - 4 0039 0299 TxDqDelay 00 00 12 00 00 -- 03 23 - 1 - 3 0040 0279 TxDqDelay 00 00 13 00 00 -- 03 05 - 3 - 3 0040 0261 TxDqDelay 00 00 14 00 00 -- 03 05 - 3 - 3 0040 0261 TxDqDelay 00 00 15 00 00 -- 04 44 - 0 - 4 0038 0300 TxDqDelay 00 00 16 00 00 -- 03 55 - 2 - 3 0039 0311 TxDqDelay 00 00 17 00 00 -- 03 07 - 3 - 3 0039 0263 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------------ -- -- -- -- -- --- --- --- - --- --- --- ---- ---- TxDqDrvDelay 00 00 00 00 00 -- 04 10 - 3 - 4 -- 0330 TxDqDrvDelay 00 00 01 00 00 -- 03 62 - 2 - 3 -- 0318 TxDqDrvDelay 00 00 02 00 00 -- 03 48 - 2 - 3 -- 0304 TxDqDrvDelay 00 00 03 00 00 -- 03 30 - 1 - 3 -- 0286 TxDqDrvDelay 00 00 04 00 00 -- 02 60 - 2 - 2 -- 0252 TxDqDrvDelay 00 00 05 00 00 -- 03 05 - 3 - 3 -- 0261 TxDqDrvDelay 00 00 06 00 00 -- 03 30 - 1 - 3 -- 0286 TxDqDrvDelay 00 00 07 00 00 -- 04 47 - 0 - 4 -- 0303 TxDqDrvDelay 00 00 08 00 00 -- 03 12 - 3 - 3 -- 0268 TxDqDrvDelay 00 00 09 00 00 -- 04 05 - 3 - 4 -- 0325 TxDqDrvDelay 00 00 10 00 00 -- 03 57 - 2 - 3 -- 0313 TxDqDrvDelay 00 00 11 00 00 -- 04 43 - 0 - 4 -- 0299 TxDqDrvDelay 00 00 12 00 00 -- 03 23 - 1 - 3 -- 0279 TxDqDrvDelay 00 00 13 00 00 -- 03 05 - 3 - 3 -- 0261 TxDqDrvDelay 00 00 14 00 00 -- 03 05 - 3 - 3 -- 0261 TxDqDrvDelay 00 00 15 00 00 -- 04 44 - 0 - 4 -- 0300 TxDqDrvDelay 00 00 16 00 00 -- 03 55 - 2 - 3 -- 0311 TxDqDrvDelay 00 00 17 00 00 -- 03 07 - 3 - 3 -- 0263 Signal CH RK ST BT HZ 128 64 1 M CC0 CC1 CC2 Vref Dly ------------ -- -- -- -- -- --- --- --- - --- --- --- ---- ---- TxDqBitDelay 00 00 00 00 00 -- -- 559 - - - - -- 0559 TxDqBitDelay 00 00 00 01 00 -- -- 575 - - - - -- 0575 TxDqBitDelay 00 00 00 02 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 00 03 00 -- -- 1007 - - - - -- 1007 TxDqBitDelay 00 00 01 00 00 -- -- 639 - - - - -- 0639 TxDqBitDelay 00 00 01 01 00 -- -- 799 - - - - -- 0799 TxDqBitDelay 00 00 01 02 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 01 03 00 -- -- 1007 - - - - -- 1007 TxDqBitDelay 00 00 02 00 00 -- -- 719 - - - - -- 0719 TxDqBitDelay 00 00 02 01 00 -- -- 623 - - - - -- 0623 TxDqBitDelay 00 00 02 02 00 -- -- 799 - - - - -- 0799 TxDqBitDelay 00 00 02 03 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 03 00 00 -- -- 495 - - - - -- 0495 TxDqBitDelay 00 00 03 01 00 -- -- 255 - - - - -- 0255 TxDqBitDelay 00 00 03 02 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 03 03 00 -- -- 319 - - - - -- 0319 TxDqBitDelay 00 00 04 00 00 -- -- 271 - - - - -- 0271 TxDqBitDelay 00 00 04 01 00 -- -- 255 - - - - -- 0255 TxDqBitDelay 00 00 04 02 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 04 03 00 -- -- 575 - - - - -- 0575 TxDqBitDelay 00 00 05 00 00 -- -- 415 - - - - -- 0415 TxDqBitDelay 00 00 05 01 00 -- -- 319 - - - - -- 0319 TxDqBitDelay 00 00 05 02 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 05 03 00 -- -- 719 - - - - -- 0719 TxDqBitDelay 00 00 06 00 00 -- -- 319 - - - - -- 0319 TxDqBitDelay 00 00 06 01 00 -- -- 303 - - - - -- 0303 TxDqBitDelay 00 00 06 02 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 06 03 00 -- -- 783 - - - - -- 0783 TxDqBitDelay 00 00 07 00 00 -- -- 319 - - - - -- 0319 TxDqBitDelay 00 00 07 01 00 -- -- 271 - - - - -- 0271 TxDqBitDelay 00 00 07 02 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 07 03 00 -- -- 415 - - - - -- 0415 TxDqBitDelay 00 00 08 00 00 -- -- 847 - - - - -- 0847 TxDqBitDelay 00 00 08 01 00 -- -- 575 - - - - -- 0575 TxDqBitDelay 00 00 08 02 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 08 03 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 09 00 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 09 01 00 -- -- 559 - - - - -- 0559 TxDqBitDelay 00 00 09 02 00 -- -- 207 - - - - -- 0207 TxDqBitDelay 00 00 09 03 00 -- -- 255 - - - - -- 0255 TxDqBitDelay 00 00 10 00 00 -- -- 943 - - - - -- 0943 TxDqBitDelay 00 00 10 01 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 10 02 00 -- -- 303 - - - - -- 0303 TxDqBitDelay 00 00 10 03 00 -- -- 479 - - - - -- 0479 TxDqBitDelay 00 00 11 00 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 11 01 00 -- -- 655 - - - - -- 0655 TxDqBitDelay 00 00 11 02 00 -- -- 351 - - - - -- 0351 TxDqBitDelay 00 00 11 03 00 -- -- 351 - - - - -- 0351 TxDqBitDelay 00 00 12 00 00 -- -- 383 - - - - -- 0383 TxDqBitDelay 00 00 12 01 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 12 02 00 -- -- 287 - - - - -- 0287 TxDqBitDelay 00 00 12 03 00 -- -- 303 - - - - -- 0303 TxDqBitDelay 00 00 13 00 00 -- -- 927 - - - - -- 0927 TxDqBitDelay 00 00 13 01 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 13 02 00 -- -- 607 - - - - -- 0607 TxDqBitDelay 00 00 13 03 00 -- -- 607 - - - - -- 0607 TxDqBitDelay 00 00 14 00 00 -- -- 623 - - - - -- 0623 TxDqBitDelay 00 00 14 01 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 14 02 00 -- -- 383 - - - - -- 0383 TxDqBitDelay 00 00 14 03 00 -- -- 511 - - - - -- 0511 TxDqBitDelay 00 00 15 00 00 -- -- 703 - - - - -- 0703 TxDqBitDelay 00 00 15 01 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 15 02 00 -- -- 751 - - - - -- 0751 TxDqBitDelay 00 00 15 03 00 -- -- 911 - - - - -- 0911 TxDqBitDelay 00 00 16 00 00 -- -- 495 - - - - -- 0495 TxDqBitDelay 00 00 16 01 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 16 02 00 -- -- 351 - - - - -- 0351 TxDqBitDelay 00 00 16 03 00 -- -- 463 - - - - -- 0463 TxDqBitDelay 00 00 17 00 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 17 01 00 -- -- 1023 - - - - -- 1023 TxDqBitDelay 00 00 17 02 00 -- -- 335 - - - - -- 0335 TxDqBitDelay 00 00 17 03 00 -- -- 575 - - - - -- 0575 S00 S01 S02 S03 S04 S05 S06 S07 S08 S09 S10 S11 S12 S13 S14 S15 S16 S17 R0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 elapsedTime: 16103287(us) CP 57 DnvNibbleTrainingExitHook CP 63 STOP_WriteTraining START_CommandClockTraining Setting CMD GRP = 340 at 3N Setting CMD GRP = 340 at 3N Setting CMD GRP = 324 at 3N Setting CMD GRP = 308 at 3N Setting CMD GRP = 292 at 3N Setting CMD GRP = 276 at 3N Setting CMD GRP = 260 at 3N Setting CMD GRP = 244 at 3N Setting CMD GRP = 228 at 3N Setting CMD GRP = 212 at 3N Setting CMD GRP = 196 at 3N Setting CMD GRP = 180 at 3N Setting CMD GRP = 356 at 3N Setting CMD GRP = 372 at 3N Setting CMD GRP = 388 at 3N Setting CMD GRP = 404 at 3N Setting CMD GRP = 420 at 3N Setting CMD GRP = 436 at 3N Setting CMD GRP = 452 at 3N Setting CMD GRP = 468 at 3N Setting CMD GRP = 484 at 3N Setting CMD GRP = 340 at 3N **ReInitialize Setting CMD GRP = 500 at 3N Setting CMD GRP = 340 at 3N **ReInitialize Setting CMD GRP = 324 at 3N **Result L: -160 H:128 New Value = 324 Setting CMD GRP = 324 at 1N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 308 at 1N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 292 at 1N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 276 at 1N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 260 at 1N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 244 at 1N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 228 at 1N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 212 at 1N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 196 at 1N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 180 at 1N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 164 at 1N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 340 at 1N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 356 at 1N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 372 at 1N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 388 at 1N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 404 at 1N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 420 at 1N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 436 at 1N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 452 at 1N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 468 at 1N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 484 at 1N Setting CMD GRP = 324 at 3N **ReInitialize Margin not found at 1N Not Found any Margin at 1N. Trying 2N Setting CMD GRP = 324 at 2N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 308 at 2N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 292 at 2N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 276 at 2N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 260 at 2N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 244 at 2N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 228 at 2N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 212 at 2N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 196 at 2N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 180 at 2N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 164 at 2N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 340 at 2N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 356 at 2N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 372 at 2N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 388 at 2N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 404 at 2N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 420 at 2N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 436 at 2N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 452 at 2N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 468 at 2N Setting CMD GRP = 324 at 3N **ReInitialize Setting CMD GRP = 484 at 2N Setting CMD GRP = 324 at 3N **ReInitialize Margin not found at 2N elapsedTime: 3967932(us)