Nick: anonymous
E-mail: none
Board: ASUS PRIME H310M-C R2.0
Contents: 
coreboot-4.12-2114-g7628c42914-dirty Sun Sep 27 13:27:06 UTC 2020 bootblock starting (log level: 7)...
CPU: Intel(R) Pentium(R) Gold G5400 CPU @ 3.70GHz
CPU: ID 906ea, Unknown, ucode: 000000d5
CPU: AES supported, TXT NOT supported, VT supported
MCH: device id 3e0f (rev 07) is Unknown
PCH: device id a2ca (rev 00) is Unknown
IGD: device id 3e90 (rev 00) is Unknown
PMC: Using default GPE route.
FMAP: Found "FLASH" version 1.1 at 0xe10000.
FMAP: base = 0xff000000 size = 0x1000000 #areas = 4
FMAP: area COREBOOT found @ e10200 (2031104 bytes)
CBFS: Locating 'fallback/romstage'
CBFS: Found @ offset 80 size 9bfc
BS: bootblock times (exec / console): total (unknown) / 55 ms


coreboot-4.12-2114-g7628c42914-dirty Sun Sep 27 13:27:06 UTC 2020 romstage starting (log level: 7)...
pm1_sts: 8900 pm1_en: 4000 pm1_cnt: 00000000
gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000
TCO_STS:   0000 0000
GEN_PMCON: e0850200 00005043
GBLRST_CAUSE: 00000002 00000000
prev_sleep_state 0
FMAP: area COREBOOT found @ e10200 (2031104 bytes)
CBFS: Locating 'fspm.bin'
CBFS: Found @ offset 3cdc0 size 63000
FMAP: area RW_MRC_CACHE found @ e00000 (65536 bytes)
MRC: no data in 'RW_MRC_CACHE'
PRMRR disabled by config.
No memory dimm at address A2
No memory dimm at address A4
No memory dimm at address A6
SPD @ 0x50
SPD: module type is DDR4
SPD: module part number is 
SPD: banks 16, ranks 1, rows 16, columns 10, density 8192 Mb
SPD: device width 8 bits, bus width 64 bits
SPD: module size is 8192 MB (per channel)


coreboot-4.12-2114-g7628c42914-dirty Sun Sep 27 13:27:06 UTC 2020 bootblock starting (log level: 7)...
CPU: Intel(R) Pentium(R) Gold G5400 CPU @ 3.70GHz
CPU: ID 906ea, Unknown, ucode: 000000d5
CPU: AES supported, TXT NOT supported, VT supported
MCH: device id 3e0f (rev 07) is Unknown
PCH: device id a2ca (rev 00) is Unknown
IGD: device id 3e90 (rev 00) is Unknown
PMC: Using default GPE route.
FMAP: Found "FLASH" version 1.1 at 0xe10000.
FMAP: base = 0xff000000 size = 0x1000000 #areas = 4
FMAP: area COREBOOT found @ e10200 (2031104 bytes)
CBFS: Locating 'fallback/romstage'
CBFS: Found @ offset 80 size 9bfc
BS: bootblock times (exec / console): total (unknown) / 55 ms


coreboot-4.12-2114-g7628c42914-dirty Sun Sep 27 13:27:06 UTC 2020 romstage starting (log level: 7)...
pm1_sts: 8900 pm1_en: 4000 pm1_cnt: 00000000
gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000
TCO_STS:   0000 0000
GEN_PMCON: e0250200 00005243
GBLRST_CAUSE: 00000002 00000000
prev_sleep_state 0
FMAP: area COREBOOT found @ e10200 (2031104 bytes)
CBFS: Locating 'fspm.bin'
CBFS: Found @ offset 3cdc0 size 63000
FMAP: area RW_MRC_CACHE found @ e00000 (65536 bytes)
MRC: no data in 'RW_MRC_CACHE'
PRMRR disabled by config.
No memory dimm at address A2
No memory dimm at address A4
No memory dimm at address A6
SPD @ 0x50
SPD: module type is DDR4
SPD: module part number is 
SPD: banks 16, ranks 1, rows 16, columns 10, density 8192 Mb
SPD: device width 8 bits, bus width 64 bits
SPD: module size is 8192 MB (per channel)
CBMEM:
IMD: root @ 0x7afff000 254 entries.
IMD: root @ 0x7affec00 62 entries.
1 DIMMs found
SMM Memory Map
SMRAM       : 0x7b000000 0x800000
 Subregion 0: 0x7b000000 0x200000
 Subregion 1: 0x7b200000 0x200000
 Subregion 2: 0x7b400000 0x400000
top_of_ram = 0x7b000000
MTRR Range: Start=7a000000 End=7b000000 (Size 1000000)
MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
MTRR Range: Start=ff000000 End=0 (Size 1000000)
FMAP: area COREBOOT found @ e10200 (2031104 bytes)
CBFS: Locating 'fallback/postcar'
CBFS: Found @ offset cee00 size 3d30
Decompressing stage fallback/postcar @ 0x7abd1fc0 (32304 bytes)
Loading module at 0x7abd2000 with entry 0x7abd2000. filesize: 0x3b10 memsize: 0x7df0
Processing 113 relocs. Offset value of 0x78bd2000
BS: romstage times (exec / console): total (unknown) / 151 ms


coreboot-4.12-2114-g7628c42914-dirty Sun Sep 27 13:27:06 UTC 2020 postcar starting (log level: 7)...
FMAP: area COREBOOT found @ e10200 (2031104 bytes)
CBFS: Locating 'fallback/ramstage'
CBFS: Found @ offset 22d80 size 1685a
Decompressing stage fallback/ramstage @ 0x7ab19fc0 (749296 bytes)
Loading module at 0x7ab1a000 with entry 0x7ab1a000. filesize: 0x2deb0 memsize: 0xb6eb0
Processing 3218 relocs. Offset value of 0x79d1a000
BS: postcar times (exec / console): total (unknown) / 38 ms


coreboot-4.12-2114-g7628c42914-dirty Sun Sep 27 13:27:06 UTC 2020 ramstage starting (log level: 7)...
FMAP: area COREBOOT found @ e10200 (2031104 bytes)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 9d00 size 19000
microcode: sig=0x906ea pf=0x2 revision=0xd5
Skip microcode update
FMAP: area COREBOOT found @ e10200 (2031104 bytes)
CBFS: Locating 'fsps.bin'
CBFS: Found @ offset a0dc0 size 2e000
Detected 2 core, 4 thread CPU.
Setting up SMI for CPU
IED base = 0x7b400000
IED size = 0x00400000
Will perform SMM setup.
CPU: Intel(R) Pentium(R) Gold G5400 CPU @ 3.70GHz.
CPU count(4) exceeds CONFIG_MAX_CPUS(1)
ERROR: More cpus requested (4) than supported (1).
MP initialization failure.
BS: BS_DEV_INIT_CHIPS entry times (exec / console): 13 / 54 ms
gpio_pad_reset_config_override: Logical to Chipset mapping not found
gpio_pad_reset_config_override: Logical to Chipset mapping not found
gpio_pad_reset_config_override: Logical to Chipset mapping not found
gpio_pad_reset_config_override: Logical to Chipset mapping not found
gpio_pad_reset_config_override: Logical to Chipset mapping not found
gpio_pad_reset_config_override: Logical to Chipset mapping not found
gpio_pad_reset_config_override: Logical to Chipset mapping not found
gpio_pad_reset_config_override: Logical to Chipset mapping not found
gpio_pad_reset_config_override: Logical to Chipset mapping not found
ERROR: Unknown MCH (0x3e0f) in get_sku_icc_max
ERROR: Unknown MCH (0x3e0f) in get_sku_ac_dc_loadline
ERROR: Unknown MCH (0x3e0f) in get_sku_ac_dc_loadline
ERROR: Unknown MCH (0x3e0f) in get_sku_icc_max
ERROR: Unknown MCH (0x3e0f) in get_sku_ac_dc_loadline
ERROR: Unknown MCH (0x3e0f) in get_sku_ac_dc_loadline
ERROR: Unknown MCH (0x3e0f) in get_sku_icc_max
ERROR: Unknown MCH (0x3e0f) in get_sku_ac_dc_loadline
ERROR: Unknown MCH (0x3e0f) in get_sku_ac_dc_loadline
ERROR: Unknown MCH (0x3e0f) in get_sku_icc_max
ERROR: Unknown MCH (0x3e0f) in get_sku_ac_dc_loadline
ERROR: Unknown MCH (0x3e0f) in get_sku_ac_dc_loadline
ITSS IRQ Polarities Before:
IPC0: 0x00ff4000
IPC1: 0x00000007
IPC2: 0x00000000
IPC3: 0x00000000
ITSS IRQ Polarities After:
IPC0: 0x00ff4000
IPC1: 0x00000007
IPC2: 0x00000000
IPC3: 0x00000000
pcie_rp_update_dev: Couldn't find PCIe Root Port #17 (originally PCI: 00:1b.0) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #18 (originally PCI: 00:1b.1) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #19 (originally PCI: 00:1b.2) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #20 (originally PCI: 00:1b.3) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #21 (originally PCI: 00:1b.4) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #22 (originally PCI: 00:1b.5) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #23 (originally PCI: 00:1b.6) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #24 (originally PCI: 00:1b.7) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #2 (originally PCI: 00:1c.1) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #3 (originally PCI: 00:1c.2) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #4 (originally PCI: 00:1c.3) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #5 (originally PCI: 00:1c.4) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #6 (originally PCI: 00:1c.5) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #8 (originally PCI: 00:1c.7) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #9 (originally PCI: 00:1d.0) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #10 (originally PCI: 00:1d.1) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #12 (originally PCI: 00:1d.3) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #13 (originally PCI: 00:1d.4) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #14 (originally PCI: 00:1d.5) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #15 (originally PCI: 00:1d.6) which was enabled in devicetree, removing.
pcie_rp_update_dev: Couldn't find PCIe Root Port #16 (originally PCI: 00:1d.7) which was enabled in devicetree, removing.
BS: BS_DEV_INIT_CHIPS run times (exec / console): 28 / 397 ms
Enumerating buses...
Root Device scanning...
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/3e0f] enabled
PCI: 00:01.0 subordinate bus PCI Express
PCI: 00:01.0 [8086/1901] enabled
PCI: 00:02.0 [8086/3e90] enabled
PCI: 00:08.0 [8086/1911] enabled
PCI: Static device PCI: 00:12.0 not found, disabling it.
PCI: 00:14.0 [8086/a2af] enabled
PCI: 00:14.2 [8086/a2b1] enabled
PCI: 00:16.0 [8086/a2ba] enabled
PCI: 00:17.0 [8086/a282] enabled
PCI: 00:1f.0 [8086/a2ca] enabled
PCI: 00:1f.1 [8086/a2a0] disabled
PCI: 00:1f.2 [8086/a2a1] disabled
PCI: 00:1f.3 [8086/a2f0] enabled
PCI: 00:1f.4 [8086/a2a3] enabled
PCI: 00:1f.5 [8086/a2a4] enabled
PCI: Leftover static devices:
PCI: 00:12.0
PCI: 00:15.0
PCI: 00:15.1
PCI: 00:15.2
PCI: 00:15.3
PCI: 00:1f.6
PCI: Check your devicetree.cb.
PCI: 00:01.0 scanning...
PCI: pci_scan_bus for bus 01
scan_bus: bus PCI: 00:01.0 finished in 2 msecs
PCI: 00:14.0 scanning...
scan_bus: bus PCI: 00:14.0 finished in 0 msecs
scan_bus: bus DOMAIN: 0000 finished in 85 msecs
scan_bus: bus Root Device finished in 96 msecs
done
BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 105 ms
FMAP: area RW_MRC_CACHE found @ e00000 (65536 bytes)
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
MRC: no data in 'RW_MRC_CACHE'
MRC: cache data 'RW_MRC_CACHE' needs update.
SPI Transaction Error at Flash Offset e00000 HSFSTS = 0x01046003
REGF metadata allocation failed: 392 data blocks 4096 total blocks
MRC: failed to update 'RW_MRC_CACHE'.
MRC: Could not find region 'UNIFIED_MRC_CACHE'
FMAP: area RW_MRC_CACHE found @ e00000 (65536 bytes)
MRC: NOT enabling PRR for 'RW_MRC_CACHE'.
BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 52 ms
found VGA at PCI: 00:02.0
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
PNP: 002e.2 missing read_resources
Done reading resources.
==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
=== Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
 DOMAIN: 0000: Resource ranges:
 * Base: 0, Size: 3b0, Tag: 100
 * Base: 3e0, Size: fc20, Tag: 100
  PCI: 00:02.0 20 *  [0x0 - 0x3f] limit: 3f io
  PCI: 00:17.0 20 *  [0x40 - 0x5f] limit: 5f io
  PCI: 00:1f.4 20 *  [0x60 - 0x7f] limit: 7f io
  PCI: 00:17.0 18 *  [0x80 - 0x87] limit: 87 io
  PCI: 00:17.0 1c *  [0x88 - 0x8b] limit: 8b io
DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
 update_constraints: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)
 update_constraints: PCI: 00:00.0 01 base fed10000 limit fed17fff mem (fixed)
 update_constraints: PCI: 00:00.0 02 base fed18000 limit fed18fff mem (fixed)
 update_constraints: PCI: 00:00.0 03 base fed19000 limit fed19fff mem (fixed)
 update_constraints: PCI: 00:00.0 04 base fed84000 limit fed84fff mem (fixed)
 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
 update_constraints: PCI: 00:00.0 07 base fed91000 limit fed91fff mem (fixed)
 update_constraints: PCI: 00:00.0 08 base 00000000 limit 0009ffff mem (fixed)
 update_constraints: PCI: 00:00.0 09 base 000c0000 limit 7affffff mem (fixed)
 update_constraints: PCI: 00:00.0 0a base 7b000000 limit 7fffffff mem (fixed)
 update_constraints: PCI: 00:00.0 0b base 100000000 limit 27effffff mem (fixed)
 update_constraints: PCI: 00:00.0 0c base 000a0000 limit 000bffff mem (fixed)
 update_constraints: PCI: 00:00.0 0d base 000c0000 limit 000fffff mem (fixed)
 DOMAIN: 0000: Resource ranges:
 * Base: 80000000, Size: 60000000, Tag: 200
 * Base: f0000000, Size: ed10000, Tag: 200
 * Base: fed1a000, Size: 66000, Tag: 200
 * Base: fed85000, Size: b000, Tag: 200
 * Base: fed92000, Size: 126e000, Tag: 200
 * Base: 27f000000, Size: 7d81000000, Tag: 100200
  PCI: 00:02.0 18 *  [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
  PCI: 00:02.0 10 *  [0x90000000 - 0x90ffffff] limit: 90ffffff mem
  PCI: 00:14.0 10 *  [0x91000000 - 0x9100ffff] limit: 9100ffff mem
  PCI: 00:1f.3 20 *  [0x91010000 - 0x9101ffff] limit: 9101ffff mem
  PCI: 00:1f.3 10 *  [0x91020000 - 0x91023fff] limit: 91023fff mem
  PCI: 00:17.0 10 *  [0x91024000 - 0x91025fff] limit: 91025fff mem
  PCI: 00:08.0 10 *  [0x91026000 - 0x91026fff] limit: 91026fff mem
  PCI: 00:14.2 10 *  [0x91027000 - 0x91027fff] limit: 91027fff mem
  PCI: 00:16.0 10 *  [0x91028000 - 0x91028fff] limit: 91028fff mem
  PCI: 00:1f.5 10 *  [0x91029000 - 0x91029fff] limit: 91029fff mem
  PCI: 00:17.0 24 *  [0x9102a000 - 0x9102a7ff] limit: 9102a7ff mem
  PCI: 00:17.0 14 *  [0x9102b000 - 0x9102b0ff] limit: 9102b0ff mem
  PCI: 00:1f.4 10 *  [0x9102c000 - 0x9102c0ff] limit: 9102c0ff mem
DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
=== Resource allocator: DOMAIN: 0000 - resource allocation complete ===
PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00ffffffff - 0x00fffffffe] size 0x00000000 gran 0x14 bus 01 mem
PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
PCI: 00:02.0 20 <- [0x0000000000 - 0x000000003f] size 0x00000040 gran 0x06 io
PCI: 00:08.0 10 <- [0x0091026000 - 0x0091026fff] size 0x00001000 gran 0x0c mem64
PCI: 00:14.0 10 <- [0x0091000000 - 0x009100ffff] size 0x00010000 gran 0x10 mem64
PCI: 00:14.2 10 <- [0x0091027000 - 0x0091027fff] size 0x00001000 gran 0x0c mem64
PCI: 00:16.0 10 <- [0x0091028000 - 0x0091028fff] size 0x00001000 gran 0x0c mem64
PCI: 00:17.0 10 <- [0x0091024000 - 0x0091025fff] size 0x00002000 gran 0x0d mem
PCI: 00:17.0 14 <- [0x009102b000 - 0x009102b0ff] size 0x00000100 gran 0x08 mem
PCI: 00:17.0 18 <- [0x0000000080 - 0x0000000087] size 0x00000008 gran 0x03 io
PCI: 00:17.0 1c <- [0x0000000088 - 0x000000008b] size 0x00000004 gran 0x02 io
PCI: 00:17.0 20 <- [0x0000000040 - 0x000000005f] size 0x00000020 gran 0x05 io
PCI: 00:17.0 24 <- [0x009102a000 - 0x009102a7ff] size 0x00000800 gran 0x0b mem
PCI: 00:1f.3 10 <- [0x0091020000 - 0x0091023fff] size 0x00004000 gran 0x0e mem64
PCI: 00:1f.3 20 <- [0x0091010000 - 0x009101ffff] size 0x00010000 gran 0x10 mem64
PCI: 00:1f.4 10 <- [0x009102c000 - 0x009102c0ff] size 0x00000100 gran 0x08 mem64
PCI: 00:1f.4 20 <- [0x0000000060 - 0x000000007f] size 0x00000020 gran 0x05 io
PCI: 00:1f.5 10 <- [0x0091029000 - 0x0091029fff] size 0x00001000 gran 0x0c mem
Done setting resources.
Done allocating resources.
BS: BS_DEV_RESOURCES run times (exec / console): 1 / 474 ms
Enabling resources...
PCI: 00:00.0 subsystem <- 8086/3e0f
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 0013
PCI: 00:01.0 cmd <- 00
PCI: 00:02.0 subsystem <- 8086/3e90
PCI: 00:02.0 cmd <- 03
PCI: 00:08.0 subsystem <- 8086/1911
PCI: 00:08.0 cmd <- 06
PCI: 00:14.0 subsystem <- 8086/a2af
PCI: 00:14.0 cmd <- 02
PCI: 00:14.2 subsystem <- 8086/a2b1
PCI: 00:14.2 cmd <- 02
PCI: 00:16.0 subsystem <- 8086/a2ba
PCI: 00:16.0 cmd <- 02
PCI: 00:17.0 subsystem <- 8086/a282
PCI: 00:17.0 cmd <- 03
PCI: 00:1f.0 subsystem <- 8086/a2ca
PCI: 00:1f.0 cmd <- 07
PCI: 00:1f.3 subsystem <- 8086/a2f0
PCI: 00:1f.3 cmd <- 02
PCI: 00:1f.4 subsystem <- 8086/a2a3
PCI: 00:1f.4 cmd <- 03
PCI: 00:1f.5 subsystem <- 8086/a2a4
PCI: 00:1f.5 cmd <- 406
done.
BS: BS_DEV_ENABLE run times (exec / console): 0 / 69 ms
ME: Version: 11.8.55.3510
BS: BS_DEV_ENABLE exit times (exec / console): 28 / 2 ms
Initializing devices...
PCI: 00:00.0 init
CPU TDP = 58 Watts
CPU PL1 = 58 Watts
CPU PL2 = 72 Watts
PCI: 00:00.0 init finished in 6 msecs
PCI: 00:02.0 init
FMAP: area COREBOOT found @ e10200 (2031104 bytes)
CBFS: Locating 'pci8086,3e90.rom'
CBFS: 'pci8086,3e90.rom' not found.
PCI Option ROM loading disabled for PCI: 00:02.0
PCI: 00:02.0 init finished in 15 msecs
PCI: 00:08.0 init
PCI: 00:08.0 init finished in 0 msecs
PCI: 00:14.0 init
PCI: 00:14.0 init finished in 0 msecs
PCI: 00:14.2 init
PCI: 00:14.2 init finished in 0 msecs
PCI: 00:16.0 init
PCI: 00:16.0 init finished in 0 msecs
PCI: 00:17.0 init
PCI: 00:17.0 init finished in 0 msecs
PCI: 00:1f.0 init
PCI: 00:1f.0 init finished in 0 msecs
PCI: 00:1f.3 init
PCI: 00:1f.3 init finished in 0 msecs
PCI: 00:1f.4 init
PCI: 00:1f.4 init finished in 0 msecs
PCI: 00:1f.5 init
PCI: 00:1f.5 init finished in 0 msecs
Devices initialized
BS: BS_DEV_INIT run times (exec / console): 1 / 84 ms
Finalize devices...
Devices finalized
BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
FMAP: area COREBOOT found @ e10200 (2031104 bytes)
CBFS: Locating 'fallback/dsdt.aml'
CBFS: Found @ offset 39a00 size 293b
FMAP: area COREBOOT found @ e10200 (2031104 bytes)
CBFS: Locating 'fallback/slic'
CBFS: 'fallback/slic' not found.
ACPI: Writing ACPI tables at 7aabf000.
ACPI:    * FACS
ACPI:    * DSDT
ACPI:    * FADT
SCI is IRQ9
ACPI: added table 1/32, length now 40
ACPI:     * SSDT
Found 0 CPU(s) with 4 core(s) each.
FMAP: area COREBOOT found @ e10200 (2031104 bytes)
CBFS: Locating 'pci8086,3e90.rom'
CBFS: 'pci8086,3e90.rom' not found.
PCI Option ROM loading disabled for PCI: 00:02.0
PCI: 00:02.0: Missing PCI Option ROM
ACPI: added table 2/32, length now 44
ACPI:    * MCFG
ACPI: added table 3/32, length now 48
ACPI:    * MADT
SCI is IRQ9
ACPI: added table 4/32, length now 52
current = 7aac1e60
ACPI:    * DMAR
ACPI: added table 5/32, length now 56
ACPI: done.
ACPI tables: 12016 bytes.
smbios_write_tables: 7aabe000
SMBIOS firmware version is set to coreboot_version: '4.12-2114-g7628c42914-dirty'
Create SMBIOS type 16
Create SMBIOS type 17
SMBIOS tables: 767 bytes.
Writing table forward entry at 0x00000500
Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 5530
Writing coreboot table at 0x7aae3000
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000a0000-00000000000fffff: RESERVED
 3. 0000000000100000-000000007aabdfff: RAM
 4. 000000007aabe000-000000007ab19fff: CONFIGURATION TABLES
 5. 000000007ab1a000-000000007abd0fff: RAMSTAGE
 6. 000000007abd1000-000000007affffff: CONFIGURATION TABLES
 7. 000000007b000000-000000007fffffff: RESERVED
 8. 00000000e0000000-00000000efffffff: RESERVED
 9. 00000000fed10000-00000000fed19fff: RESERVED
10. 00000000fed80000-00000000fed84fff: RESERVED
11. 00000000fed90000-00000000fed91fff: RESERVED
12. 0000000100000000-000000027effffff: RAM
FMAP: area COREBOOT found @ e10200 (2031104 bytes)
Wrote coreboot table at: 0x7aae3000, 0x3cc bytes, checksum 1c12
coreboot table: 996 bytes.
IMD ROOT    0. 0x7afff000 0x00001000
IMD SMALL   1. 0x7affe000 0x00001000
FSP MEMORY  2. 0x7abfe000 0x00400000
CONSOLE     3. 0x7abde000 0x00020000
TIME STAMP  4. 0x7abdd000 0x00000910
MRC DATA    5. 0x7abdb000 0x00001878
ROMSTG STCK 6. 0x7abda000 0x00001000
AFTER CAR   7. 0x7abd1000 0x00009000
RAMSTAGE    8. 0x7ab19000 0x000b8000
REFCODE     9. 0x7aaeb000 0x0002e000
COREBOOT   10. 0x7aae3000 0x00008000
ACPI       11. 0x7aabf000 0x00024000
SMBIOS     12. 0x7aabe000 0x00000800
IMD small region:
  IMD ROOT    0. 0x7affec00 0x00000400
  FSP RUNTIME 1. 0x7affebe0 0x00000004
  FMAP        2. 0x7affeb00 0x000000e0
  POWER STATE 3. 0x7affeac0 0x00000040
  ROMSTAGE    4. 0x7affeaa0 0x00000004
  MEM INFO    5. 0x7affe8e0 0x000001c0
BS: BS_WRITE_TABLES run times (exec / console): 1 / 259 ms
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x000000007b000000 size 0x7af40000 type 6
0x000000007b000000 - 0x0000000080000000 size 0x05000000 type 0
0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
0x0000000100000000 - 0x000000027f000000 size 0x17f000000 type 6
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
CPU physical address size: 39 bits
MTRR: default type WB/UC MTRR counts: 6/6.
MTRR: UC selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
MTRR: 1 base 0x000000007b000000 mask 0x0000007fff000000 type 0
MTRR: 2 base 0x000000007c000000 mask 0x0000007ffc000000 type 0
MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
MTRR: 5 base 0x0000000200000000 mask 0x0000007f80000000 type 6

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

BS: BS_WRITE_TABLES exit times (exec / console): 1 / 137 ms
FMAP: area COREBOOT found @ e10200 (2031104 bytes)
CBFS: Locating 'fallback/payload'
CBFS: Found @ offset d2b80 size 10f38
Checking segment from ROM address 0xffee2db8
Payload being loaded at below 1MiB without region being marked as RAM usable.
Checking segment from ROM address 0xffee2dd4
Loading segment from ROM address 0xffee2db8
  code (compression=1)
  New segment dstaddr 0x000dfc60 memsize 0x203a0 srcaddr 0xffee2df0 filesize 0x10f00
Loading Segment: addr: 0x000dfc60 memsz: 0x00000000000203a0 filesz: 0x0000000000010f00
using LZMA
Loading segment from ROM address 0xffee2dd4
  Entry Point 0x000fd263
BS: BS_PAYLOAD_LOAD run times (exec / console): 26 / 57 ms
Finalizing chipset.
ME: Host Firmware Status Register 1 : 0x90000045
ME: Host Firmware Status Register 2 : 0x66000106
ME: Host Firmware Status Register 3 : 0x00000020
ME: Host Firmware Status Register 4 : 0x00084000
ME: Host Firmware Status Register 5 : 0x00000000
ME: Host Firmware Status Register 6 : 0x40000000
ME: FW Partition Table      : OK
ME: Bringup Loader Failure  : NO
ME: Firmware Init Complete  : NO
ME: Manufacturing Mode      : NO
ME: Boot Options Present    : NO
ME: Update In Progress      : NO
ME: D3 Support              : NO
ME: D0i3 Support            : YES
ME: Low Power State Enabled : NO
ME: CPU Replaced            : NO
ME: CPU Replacement Valid   : YES
ME: Current Working State   : Normal
ME: Current Operation State : M0 with UMA
ME: Current Operation Mode  : Normal
ME: Error Code              : No Error
ME: Progress Phase          : Host Communication
ME: Power Management Event  : Pseudo-global reset
ME: Progress Phase State    : Host communication established
ME: Power Down Mitigation   : NO
ME: FPF status              : fused
Finalizing SMM.
APMC done.
BS: BS_PAYLOAD_LOAD exit times (exec / console): 56 / 103 ms
mp_park_aps done after 0 msecs.
Jumping to boot code at 0x000fd263(0x7aae3000)
SeaBIOS (version rel-1.13.0-0-gf21b5a4)
BUILD: gcc: (coreboot toolchain vf2741aa632 2020-07-06) 8.3.0 binutils: (GNU Binutils) 2.33.1
SeaBIOS (version rel-1.13.0-0-gf21b5a4)
BUILD: gcc: (coreboot toolchain vf2741aa632 2020-07-06) 8.3.0 binutils: (GNU Binutils) 2.33.1
Found coreboot cbmem console @ 7abde000
Found mainboard ASUS PRIME H310M-C R2.0
Relocating init from 0x000e1340 to 0x7aa70d40 (size 53792)
Found CBFS header at 0xffe10238
multiboot: eax=7ab47940, ebx=7ab47904
Found 13 PCI devices (max PCI bus is 01)
Copying SMBIOS entry point from 0x7aabe000 to 0x000f6280
Copying ACPI RSDP from 0x7aabf000 to 0x000f6250
Using pmtimer, ioport 0x1808
Scan for VGA option rom
Turning on vga text mode console
SeaBIOS (version rel-1.13.0-0-gf21b5a4)
XHCI init on dev 00:14.0: regs @ 0x91000000, 20 ports, 64 slots, 32 byte contexts
XHCI    protocol USB  2.00, 10 ports (offset 1), def 3011
XHCI    protocol USB  3.00, 4 ports (offset 17), def 3000
XHCI    extcap 0xc0 @ 0x91008070
XHCI    extcap 0x1 @ 0x9100846c
XHCI    extcap 0xc6 @ 0x910084f4
XHCI    extcap 0xc7 @ 0x91008500
XHCI    extcap 0xc2 @ 0x91008600
XHCI    extcap 0xa @ 0x91008700
XHCI    extcap 0xc3 @ 0x91008740
XHCI    extcap 0xc4 @ 0x91008800
XHCI    extcap 0xc5 @ 0x91008900
WARNING - Timeout at i8042_flush:71!
AHCI controller at 00:17.0, iobase 0x9102a000, irq 0
Found 0 lpt ports
Found 1 serial ports
Searching bootorder for: /pci@i0cf8/*@17/drive@0/disk@0
AHCI/0: Set transfer mode to UDMA-6
Searching bios-geometry for: /pci@i0cf8/*@17/drive@0/disk@0
AHCI/0: registering: "AHCI/0: INTEL SSDSA2CW080G3 ATA-8 Hard-Disk (74 GiBytes)"
XHCI port #3: 0x00200a03, powered, enabled, pls 0, speed 2 [Low]
USB keyboard initialized
XHCI port #6: 0x00200a03, powered, enabled, pls 0, speed 2 [Low]
All threads complete.
Scan for option roms

Press ESC for boot menu.