Nick: hell__
E-mail: NULL
Board: google/parrot
Contents: 
usuario@bloodfest ~/coreboot $ git status
On branch master
Your branch is up to date with 'origin/master'.

Untracked files:
  (use "git add <file>..." to include in what will be committed)
	test.layout

nothing added to commit but untracked files present (use "git add" to track)
usuario@bloodfest ~/coreboot $ cat defconfig 
CONFIG_VENDOR_GOOGLE=y
CONFIG_BOARD_GOOGLE_PARROT=y
CONFIG_NO_DEFAULT_PAYLOAD=y
CONFIG_PAYLOAD_NONE=y
usuario@bloodfest ~/coreboot $ cp defconfig .config; make olddefconfig
#
# configuration written to /home/usuario/coreboot/.config
#
make olddefconfig  0.68s user 0.07s system 99% cpu 0.746 total
usuario@bloodfest ~/coreboot $ make BUILD_TIMELESS=1 -j4                                            
Skipping submodule '3rdparty/amd_blobs'
Skipping submodule '3rdparty/blobs'
Skipping submodule '3rdparty/cmocka'
Skipping submodule '3rdparty/fsp'
Skipping submodule '3rdparty/intel-microcode'
    HOSTCC     nvramtool/cli/nvramtool.o
    HOSTCC     nvramtool/cli/opts.o
    HOSTCC     nvramtool/cmos_lowlevel.o
    HOSTCC     nvramtool/cmos_ops.o
    HOSTCC     nvramtool/common.o
    HOSTCC     nvramtool/compute_ip_checksum.o
    HOSTCC     nvramtool/input_file.o
    HOSTCC     nvramtool/hexdump.o
    HOSTCC     nvramtool/layout.o
    HOSTCC     nvramtool/accessors/layout-common.o
    HOSTCC     nvramtool/accessors/layout-text.o
    HOSTCC     nvramtool/lbtable.o
    HOSTCC     nvramtool/accessors/layout-bin.o
    HOSTCC     nvramtool/reg_expr.o
    HOSTCC     nvramtool/cbfs.o
    HOSTCC     nvramtool/accessors/cmos-mem.o
    GEN        build.h
    HOSTCC     cbfstool/fmaptool.o
    HOSTCC     cbfstool/cbfs_sections.o
    HOSTCC     cbfstool/fmap_from_fmd.o
    HOSTCC     cbfstool/fmap.o
    HOSTCC     cbfstool/kv_pair.o
    HOSTCC     cbfstool/valstr.o
    GEN        generated/assembly.inc
    GCC        libgnat-x86_32/lib/gnat/a-unccon.o
    GCC        libgnat-x86_32/lib/gnat/ada.o
    GCC        libgnat-x86_32/lib/gnat/g-souinf.o
#
# configuration written to /home/usuario/coreboot/.config
#
    GCC        libgnat-x86_32/lib/gnat/gnat.o
    GCC        libgnat-x86_32/lib/gnat/i-c.o
    GCC        libgnat-x86_32/lib/gnat/interfac.o
    GCC        libgnat-x86_32/lib/gnat/s-atacco.o
    GCC        libgnat-x86_32/lib/gnat/s-imenne.o
    GCC        libgnat-x86_32/lib/gnat/s-maccod.o
    GCC        libgnat-x86_32/lib/gnat/s-parame.o
    GCC        libgnat-x86_32/lib/gnat/s-stoele.o
    GCC        libgnat-x86_32/lib/gnat/s-unstyp.o
    GCC        libgnat-x86_32/lib/gnat/system.o
    HOSTCC     cbfstool/rmodtool.o
    HOSTCC     cbfstool/rmodule.o
    HOSTCC     cbfstool/common.o
    HOSTCC     cbfstool/elfheaders.o
    HOSTCC     cbfstool/xdr.o
    CREATE     build/mainboard/google/parrot/cbfs-file.sMgY9U.out (from /home/usuario/coreboot/.config)
    MICROCODE  cpu_microcode_blob.bin
    HOSTCC     cbfstool/cbfstool.o
3rdparty/intel-microcode/intel-ucode/06-2a-07 3rdparty/intel-microcode/intel-ucode/06-3a-09
    HOSTCC     cbfstool/cbfs_image.o
    HOSTCC     cbfstool/cbfs-mkstage.o
    HOSTCC     cbfstool/cbfs-mkpayload.o
    HOSTCC     cbfstool/partitioned_file.o
    HOSTCC     cbfstool/cbfs.o
    HOSTCC     cbfstool/fsp_relocate.o
    HOSTCC     cbfstool/mem_pool.o
    HOSTCC     cbfstool/region.o
    HOSTCC     cbfstool/linux_trampoline.o
    HOSTCC     cbfstool/cbfs-payload-linux.o
    HOSTCC     cbfstool/compress.o
    HOSTCC     cbfstool/lz4.o
    HOSTCC     cbfstool/lz4hc.o
    HOSTCC     cbfstool/lz4frame.o
    HOSTCC     cbfstool/xxhash.o
    HOSTCC     cbfstool/lz4_wrapper.o
    HOSTCC     cbfstool/lzma.o
    HOSTCC     cbfstool/LzFind.o
    HOSTCC     cbfstool/LzmaDec.o
    HOSTCC     cbfstool/LzmaEnc.o
    MAKE       /home/usuario/coreboot/vboot_lib/libvboot_host.a
    HOSTCC     cbfstool/ifittool.o
    HOSTCC     cbfstool/fit.o
    Compile IFDTOOL
    HOSTCC     cbfstool/ifwitool.o
    HOSTCC     util/sconfig/lex.yy.o
    HOSTCC     util/sconfig/sconfig.tab.o
    HOSTCC     util/sconfig/main.o
    HOSTCC     nvramtool/nvramtool (link)
    CC         bootblock/arch/x86/bootblock_crt0.o
    CC         bootblock/arch/x86/id.o
    HOSTCC     cbfstool/fmd.o
    CC         bootblock/arch/x86/walkcbfs.o
    CC         bootblock/cpu/intel/car/non-evict/cache_as_ram.o
    CC         bootblock/cpu/intel/microcode/microcode_asm.o
    CC         bootblock/cpu/x86/early_reset.o
    CC         romstage/arch/x86/assembly_entry.o
    CC         romstage/arch/x86/gdt_init.o
    GENERATE   libhwbase/common/hw-config.ads
    AR         libgnat-x86_32/libgnat.a
vboot SHA256 built with tight loops (slower, smaller code size)
    GENERATE   libgfxinit/common/hw-gfx-gma-config.ads
    HOSTCC     cbfstool/rmodtool (link)
    CC            cgpt/cgpt_add.o
    CC         smmstub/cpu/x86/smm/smm_stub.o
    CC            cgpt/cgpt_boot.o
    CC         ramstage/cpu/x86/lapic/secondary.o
    CC         rmodules_x86_32/cpu/x86/sipi_vector.o
    CC            cgpt/cgpt_common.o
    CC         ramstage/arch/x86/c_start.o
    CC            cgpt/cgpt_create.o
    CC            cgpt/cgpt_edit.o
    CC         ramstage/arch/x86/idt.o
    CC            cgpt/cgpt_find.o
    CC         ramstage/arch/x86/wakeup.o
    IASL       build/dsdt.aml
    OPTION     cmos_layout.bin
    CC            cgpt/cgpt_nor.o
    CC         postcar/arch/x86/exit_car.o
    CC         postcar/arch/x86/gdt_init.o
    CC            cgpt/cgpt_prioritize.o
    CC         postcar/cpu/intel/car/non-evict/exit_car.o
    CC            cgpt/cgpt_show.o

Intel ACPI Component Architecture
ASL+ Optimizing Compiler/Disassembler version 20190703
Copyright (c) 2000 - 2019 Intel Corporation

coreboot toolchain vd70f5fae1c 2019-05-26
    HOSTCC     cbfstool/ifwitool (link)
    HOSTCC     util/sconfig/sconfig (link)
    CC            firmware/2lib/2common.o
dsdt.asl   1805:  Method (_CRS, 0, NotSerialized)
Remark   2120 -             ^ Control Method should be made Serialized (due to creation of named objects within)

ASL Input:     dsdt.asl -   42650 bytes   1075 keywords   2526 source lines
AML Output:    dsdt.aml -   12290 bytes    602 opcodes     473 named objects

Compilation successful. 0 Errors, 0 Warnings, 1 Remarks, 303 Optimizations, 6 Constants Folded
    CC            firmware/2lib/2context.o
    IASL       build/dsdt.aml disassembled correctly.
    OPTION     option_table.h
    HOSTCC     cbfstool/fmd_parser.o
    CC            firmware/2lib/2crc8.o
    HOSTCC     cbfstool/fmd_scanner.o
    CC            firmware/2lib/2crypto.o
    CC         smm/arch/x86/memcpy.o
    CC            firmware/2lib/2hmac.o
    CC         smm/arch/x86/memmove.o
    CC            firmware/2lib/2kernel.o

[*snip*]

    CP         bootblock/arch/x86/memlayout.ld
    CC         bootblock/lib/fmap.o
    CP         bootblock/lib/program.ld
    CP         romstage/arch/x86/memlayout.ld
    CC         romstage/lib/fmap.o
    CP         romstage/lib/program.ld
    GCC        ramstage/b__ramstage.o
    LINK       cbfs/fallback/postcar.debug
    LINK       cbfs/fallback/bootblock.debug
    LINK       cbfs/fallback/romstage.debug
    OBJCOPY    cbfs/fallback/bootblock.elf
    OBJCOPY    ramstage/cpu/x86/smm/smmstub.manual
    OBJCOPY    ramstage/cpu/x86/sipi_vector.manual
    OBJCOPY    ramstage/cpu/x86/smm/smm.manual
    CC         generated/ramstage.o
    OBJCOPY    cbfs/fallback/romstage.elf
    OBJCOPY    bootblock.raw.elf
    OBJCOPY    bootblock.raw.bin
    CC         cbfs/fallback/ramstage.debug
Created CBFS (capacity = 982488 bytes)
    CBFS       fallback/romstage
    CBFS       cpu_microcode_blob.bin
    CBFS       fallback/ramstage
    CBFS       config
    CBFS       revision
    CBFS       fallback/dsdt.aml
    CBFS       cmos_layout.bin
    CBFS       fallback/postcar
    DD         Adding Intel Firmware Descriptor
    IFDTOOL    me.bin -> coreboot.pre
File build/coreboot.pre is 8388608 bytes
File 3rdparty/blobs/mainboard/google/parrot/me.bin is 2093056 bytes
Adding 3rdparty/blobs/mainboard/google/parrot/me.bin as the Intel ME section of build/coreboot.pre
Writing new image to build/coreboot.pre
    IFDTOOL    Unlocking Management Engine
File build/coreboot.pre is 8388608 bytes
Writing new image to build/coreboot.pre
    CBFS       coreboot.rom
    CBFSLAYOUT  coreboot.rom

This image contains the following sections that can be manipulated with this tool:

'RW_MRC_CACHE' (size 65536, offset 7340032)
'COREBOOT' (CBFS, size 982528, offset 7406080)

It is possible to perform either the write action or the CBFS add/remove actions on every section listed above.
To see the image's read-only sections as well, rerun with the -w option.
    CBFSPRINT  coreboot.rom

FMAP REGION: COREBOOT
Name                           Offset     Type           Size   Comp
cbfs master header             0x0        cbfs header        32 none
fallback/romstage              0x80       stage           78380 none
cpu_microcode_blob.bin         0x13340    microcode       26624 none
fallback/ramstage              0x19bc0    stage          109447 none
config                         0x34780    raw               111 none
revision                       0x34840    raw               665 none
fallback/dsdt.aml              0x34b40    raw             12290 none
cmos_layout.bin                0x37bc0    cmos_layout      1188 none
fallback/postcar               0x380c0    stage           18452 none
(empty)                        0x3c940    null           668760 none
bootblock                      0xdfdc0    bootblock       65536 none

Built google/parrot (Parrot)
make BUILD_TIMELESS=1 -j4  13.27s user 3.53s system 278% cpu 6.024 total
usuario@bloodfest ~/coreboot $ cp build/coreboot.rom before.rom       
usuario@bloodfest ~/coreboot $ git fetch "ssh://Th3Fanbus@review.coreboot.org:29418/coreboot" refs/changes/84/42084/2 && git cherry-pick FETCH_HEAD
From ssh://review.coreboot.org:29418/coreboot
 * branch                  refs/changes/84/42084/2 -> FETCH_HEAD
[master 669441e4c9] southbridge/intel/common: Introduce ASL2.0 syntax
 Author: Alexey Buyanov <alexey.buyanov@intel.com>
 Date: Mon Jun 1 22:08:35 2020 -0700
 2 files changed, 47 insertions(+), 47 deletions(-)
usuario@bloodfest ~/coreboot $ make BUILD_TIMELESS=1 -j4 && diff -s -q build/coreboot.rom before.rom
Skipping submodule '3rdparty/amd_blobs'
Skipping submodule '3rdparty/blobs'
Skipping submodule '3rdparty/cmocka'
Skipping submodule '3rdparty/fsp'
Skipping submodule '3rdparty/intel-microcode'
    CREATE     build/mainboard/google/parrot/cbfs-file.5BzFAj.out (from /home/usuario/coreboot/.config)
    IASL       build/dsdt.aml

Intel ACPI Component Architecture
ASL+ Optimizing Compiler/Disassembler version 20190703
Copyright (c) 2000 - 2019 Intel Corporation

coreboot toolchain vd70f5fae1c 2019-05-26
dsdt.asl   1805:  Method (_CRS, 0, NotSerialized)
Remark   2120 -             ^ Control Method should be made Serialized (due to creation of named objects within)

ASL Input:     dsdt.asl -   42595 bytes   1075 keywords   2526 source lines
AML Output:    dsdt.aml -   12290 bytes    602 opcodes     473 named objects

Compilation successful. 0 Errors, 0 Warnings, 1 Remarks, 303 Optimizations, 6 Constants Folded
    IASL       build/dsdt.aml disassembled correctly.
Created CBFS (capacity = 982488 bytes)
    CBFS       fallback/romstage
    CBFS       cpu_microcode_blob.bin
    CBFS       fallback/ramstage
    CBFS       config
    CBFS       revision
    CBFS       fallback/dsdt.aml
    CBFS       cmos_layout.bin
    CBFS       fallback/postcar
    DD         Adding Intel Firmware Descriptor
    IFDTOOL    me.bin -> coreboot.pre
File build/coreboot.pre is 8388608 bytes
File 3rdparty/blobs/mainboard/google/parrot/me.bin is 2093056 bytes
Adding 3rdparty/blobs/mainboard/google/parrot/me.bin as the Intel ME section of build/coreboot.pre
Writing new image to build/coreboot.pre
    IFDTOOL    Unlocking Management Engine
File build/coreboot.pre is 8388608 bytes
Writing new image to build/coreboot.pre
    CBFS       coreboot.rom
    CBFSLAYOUT  coreboot.rom

This image contains the following sections that can be manipulated with this tool:

'RW_MRC_CACHE' (size 65536, offset 7340032)
'COREBOOT' (CBFS, size 982528, offset 7406080)

It is possible to perform either the write action or the CBFS add/remove actions on every section listed above.
To see the image's read-only sections as well, rerun with the -w option.
    CBFSPRINT  coreboot.rom

FMAP REGION: COREBOOT
Name                           Offset     Type           Size   Comp
cbfs master header             0x0        cbfs header        32 none
fallback/romstage              0x80       stage           78380 none
cpu_microcode_blob.bin         0x13340    microcode       26624 none
fallback/ramstage              0x19bc0    stage          109447 none
config                         0x34780    raw               111 none
revision                       0x34840    raw               665 none
fallback/dsdt.aml              0x34b40    raw             12290 none
cmos_layout.bin                0x37bc0    cmos_layout      1188 none
fallback/postcar               0x380c0    stage           18452 none
(empty)                        0x3c940    null           668760 none
bootblock                      0xdfdc0    bootblock       65536 none

Built google/parrot (Parrot)
make BUILD_TIMELESS=1 -j4  1.29s user 0.45s system 94% cpu 1.843 total
Files build/coreboot.rom and before.rom are identical
usuario@bloodfest ~/coreboot $