Nick: flyinfishfinger E-mail: flyingfishfinger@gmail.com Board: X210 Contents: flashrom v1.1-rc1-68-gea0c093 on Linux 5.0.0-37-generic (x86_64) flashrom was built with libpci 3.5.2, GCC 7.4.0, little endian Command line (6 args): flashrom -p internal -w ../../BIOS/bios_stock.bin -o log.txt Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Initializing internal programmer /sys/class/mtd/mtd0 does not exist Found candidate at: 00000500-00000510 Found coreboot table at 0x00000500. Found candidate at: 00000000-000003ec Found coreboot table at 0x00000000. coreboot table found at 0x7aae2000. coreboot header(24) checksum: 0352 table(1004) checksum: 66f4 entries: 32 Vendor ID: 51nb, part ID: X210 Using Internal DMI decoder. DMI string chassis-type: "Laptop" Laptop detected via DMI. DMI string system-manufacturer: "51nb" DMI string system-product-name: "X210" DMI string system-version: "3.0" DMI string baseboard-manufacturer: "51nb" DMI string baseboard-product-name: "X210" DMI string baseboard-version: "3.0" W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: fc. Found chipset "Intel Kaby Lake U w/ iHDCP2.2 Prem." with PCI ID 8086:9d4e. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom@flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... BIOS_SPI_BC = 0x28b: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (SPI) Top Swap: not enabled SPI Read Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x8b: BIOS Lock Enable: enabled, BIOS Write Enable: enabled Warning: Setting Bios Control at 0xdc from 0x8b to 0x89 failed. New value is 0x8b. SPIBAR = 0x00007f4f7a962000 (phys = 0xfe010000) 0x04: 0xe800 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, SCIP=0, PRR34_LOCKDN=0, WRSDIS=1, FDOPSS=1, FDV=1, FLOCKDN=1 SPI Configuration is locked down. Reading OPCODES... done OP Type Pre-OP op[0]: 0x01, write w/o addr, none op[1]: 0x02, write w/ addr, none op[2]: 0x03, read w/ addr, none op[3]: 0x05, read w/o addr, none op[4]: 0x20, write w/ addr, none op[5]: 0x9f, read w/o addr, none op[6]: 0xd8, write w/ addr, none op[7]: 0x0b, read w/ addr, none Pre-OP 0: 0x06, Pre-OP 1: 0x50 0x06: 0x3f00 (HSFC) HSFC: FGO=0, HSFC=0, WET=0, FDBC=63, SME=0 0x08: 0x007fffc0 (FADDR) 0x0c: 0x00001f00 (DLOCK) DLOCK: BMWAG_LOCKDN=0, BMRAG_LOCKDN=0, SBMWAG_LOCKDN=0, SBMRAG_LOCKDN=0, PR0_LOCKDN=1, PR1_LOCKDN=1, PR2_LOCKDN=1, PR3_LOCKDN=1, PR4_LOCKDN=1, SSEQ_LOCKDN=0 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write. 0x58: 0x07ff0200 FREG1: BIOS region (0x00200000-0x007fffff) is read-write. 0x5C: 0x01ff0001 FREG2: Management Engine region (0x00001000-0x001fffff) is read-write. 0x60: 0x00007fff FREG3: Gigabit Ethernet region is unused. 0x64: 0x00007fff FREG4: Platform Data region is unused. 0x68: 0x00007fff FREG5: Device Expansion region is unused. 0x6C: 0x00007fff FREG6: BIOS2 region is unused. 0x70: 0x00007fff FREG7: unknown region is unused. 0x74: 0x00007fff FREG8: EC/BMC region is unused. 0x78: 0x00007fff FREG9: unknown region is unused. 0x84: 0x00000000 (PR0 is unused) 0x88: 0x00000000 (PR1 is unused) 0x8C: 0x00000000 (PR2 is unused) 0x90: 0x00000000 (PR3 is unused) 0x94: 0x00000000 (PR4 is unused) 0x98: 0x00000000 (GPR0 is unused) 0xa0: 0x00 (SSFS) SSFS: SCIP=0, FDONE=0, FCERR=0, AEL=0 0xa1: 0xfe0000 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=6 0xa4: 0x5006 (PREOP) 0xa6: 0xb32d (OPTYPE) 0xa8: 0x05030201 (OPMENU) 0xac: 0x0bd89f20 (OPMENU+4) 0xc4: 0xf3d82044 (LVSCC) LVSCC: BES=0x0, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xc8: 0x00002000 (UVSCC) UVSCC: BES=0x0, WG=0, WSR=0, WEWS=0, EO=0x20 Reading flash descriptors mapped by the chipset via FDOC/FDOD... done. === Content Section === FLVALSIG 0x0ff0a55a FLMAP0 0x00040003 FLMAP1 0x42100208 FLMAP2 0x00310330 --- Details --- NR (Number of Regions): 10 FRBA (Flash Region Base Address): 0x040 NC (Number of Components): 1 FCBA (Flash Component Base Address): 0x030 ISL (ICH/PCH/SoC Strap Length): 66 FISBA/FPSBA (Flash ICH/PCH/SoC Strap Base Addr): 0x100 NM (Number of Masters): 3 FMBA (Flash Master Base Address): 0x080 MSL/PSL (MCH/PROC Strap Length): 3 FMSBA (Flash MCH/PROC Strap Base Address): 0x300 === Component Section === FLCOMP 0x324c00f4 FLILL 0xad604221 FLILL1 0xc7c4b9b7 --- Details --- Component 1 density: 8 MB Component 2 is not used. Read Clock Frequency: 17 MHz Read ID and Status Clock Freq.: 17 MHz Write and Erase Clock Freq.: 48 MHz Fast Read is not supported. Dual Output Fast Read Support: enabled Invalid instruction 0: 0x21 Invalid instruction 1: 0x42 Invalid instruction 2: 0x60 Invalid instruction 3: 0xad Invalid instruction 4: 0xb7 Invalid instruction 5: 0xb9 Invalid instruction 6: 0xc4 Invalid instruction 7: 0xc7 === Region Section === FLREG0 0x00000000 FLREG1 0x07ff0200 FLREG2 0x01ff0001 FLREG3 0x00007fff FLREG4 0x00007fff FLREG5 0x00007fff FLREG6 0x00007fff FLREG7 0x00007fff FLREG8 0x00007fff FLREG9 0x00007fff --- Details --- Region 0 (Descr. ) 0x00000000 - 0x00000fff Region 1 (BIOS ) 0x00200000 - 0x007fffff Region 2 (ME ) 0x00001000 - 0x001fffff Region 3 (GbE ) is unused. Region 4 (Platf. ) is unused. Region 5 (DevExp ) is unused. Region 6 (BIOS2 ) is unused. Region 7 (unknown) is unused. Region 8 (EC/BMC ) is unused. Region 9 (unknown) is unused. === Master Section === FLMSTR1 0xffffff00 FLMSTR2 0xffffff00 FLMSTR3 0xffffff00 --- Details --- FD BIOS ME GbE Pltf Reg5 Reg6 Reg7 EC Reg9 BIOS rw rw rw rw rw rw rw rw rw rw ME rw rw rw rw rw rw rw rw rw rw GbE rw rw rw rw rw rw rw rw rw rw Enabling hardware sequencing by default for 100+ series PCH. OK. No board enable found matching coreboot IDs vendor="51nb", model="X210". The following protocols are supported: Programmer-specific. Probing for Programmer Opaque flash chip, 0 kB: Hardware sequencing reports 1 attached SPI flash chip with a density of 8192 kB. There is only one partition containing the whole address space (0x000000 - 0x7fffff). There are 2048 erase blocks with 4096 B each. Found Programmer flash chip "Opaque flash chip" (8192 kB, Programmer-specific) mapped at physical address 0x0000000000000000. Found Programmer flash chip "Opaque flash chip" (8192 kB, Programmer-specific). Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... Reading 8388608 bytes starting at 0x000000. done. Erasing and writing flash chip... Trying erase function 0... 0x000000-0x000fff:EErasing 4096 bytes starting at 0x000000. HSFC used for block erasing: HSFC: FGO=1, HSFC=3, WET=0, FDBC=63, SME=0 Reading 4096 bytes starting at 0x000000. FAILED at 0x0000000f! Expected=0xff, Found=0x5a, failed byte count from 0x00000000-0x00000fff: 0x8d0 ERASE FAILED! Reading current flash chip contents... Reading 8388608 bytes starting at 0x000000. done. Looking for another erase function. Trying erase function 1... not defined. Looking for another erase function. Trying erase function 2... not defined. Looking for another erase function. Trying erase function 3... not defined. Looking for another erase function. Trying erase function 4... not defined. Looking for another erase function. Trying erase function 5... not defined. Looking for another erase function. Trying erase function 6... not defined. Looking for another erase function. Trying erase function 7... not defined. No usable erase functions left. FAILED! Uh oh. Erase/write failed. Checking if anything has changed. Reading current flash chip contents... Reading 8388608 bytes starting at 0x000000. done. Good, writing to the flash chip apparently didn't do anything. This means we have to add special support for your board, programmer or flash chip. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom@flashrom.org, thanks! ------------------------------------------------------------------------------- You may now reboot or simply leave the machine running. Restoring PCI config space for 00:1f:5 reg 0xdc