Nick: GNUtoo E-mail: none Board: Asus M4A785T-M Contents: picocom -b 115200 /dev/ttyUSB0 picocom v3.1 port is : /dev/ttyUSB0 flowcontrol : none baudrate is : 115200 parity is : none databits are : 8 stopbits are : 1 escape is : C-a local echo is : no noinit is : no noreset is : no hangup is : no nolock is : no send_cmd is : sz -vv receive_cmd is : rz -vv -E imap is : omap is : emap is : crcrlf,delbs, logfile is : none initstring : none exit_after is : not set exit is : no Type [C-a] [C-h] to see available commands Terminal ready coreboot-4.9-193-g0185b8b82a Sun Jan 6 15:48:29 UTC 2019 romstage starting... BSP Family_Model: 00100f62 *sysinfo range: [000c4e20,000cf38c] bsp_apicid = 00 cpu_init_detectedx = 00000000 CBFS @ 200 size ffe00 CBFS: 'Master Header Locator' located CBFS at [200:100000) CBFS: Locating 'microcode_amd.bin' CBFS: 'microcode_amd.bin' not found. [microcode] microcode file not found. Skipping updates. cpuSetAMDMSR done Enter amd_ht_init FMAP: Found "FLASH" version 1.1 at 0. FMAP: base = fff00000 size = 100000 #areas = 3 FMAP: area COREBOOT found @ 200 (1048064 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 398c0 size 48c No CMOS option 'hypertransport_speed_limit'. Exit amd_ht_init cpuSetAMDPCI 00 done Prep FID/VID Node:00 F3x80: e600e681 F3x84: 80e641e6 F3xD4: c8810f24 F3xD8: 03001016 F3xDC: 0000532a core0 started: start_other_cores() NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead. init node: 00 cores: 01 pass 1 Start other core - nodeid: 00 cores: 01 started ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead. get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started rs780_early_setup() fam10_optimization() rs780_por_init sb700_early_setup() FMAP: area COREBOOT found @ 200 (1048064 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 398c0 size 48c No CMOS option 'sata_ahci_mode'. sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 found SMBUS controller on 00:00.0 SMBus controller enabled, sb revision is A14 sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 FMAP: area COREBOOT found @ 200 (1048064 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 398c0 size 48c No CMOS option 'cpu_c_states'. sb700_pmio_por_init() Begin FIDVID MSR 0xc0010071 0x30bc0073 0x44035440 FIDVID on BSP, APIC_id: 00 BSP fid = 10600 NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instad. get_boot_apic_id: using 0 as APIC ID for node 0, core 0 get_boot_apic_id: using 1 as APIC ID for node 0, core 1 Wait for AP stage 1: ap_apicid = 1 init_fidvid_bsp_stage1: timed out reading from ap 01 common_fid = 10600 FID Change Node:00, F3xD4: c8810f26 End FIDVIDMSR 0xc0010071 0x30bc0073 0x3c005440 rs780_htinit cpu_ht_freq=b. rs780_htinit: HT3 mode ...WARM RESET... soft_reset() called! coreboot-4.9-193-g0185b8b82a Sun Jan 6 15:48:29 UTC 2019 romstage starting... BSP Family_Model: 00100f62 *sysinfo range: [000c4e20,000cf38c] bsp_apicid = 00 cpu_init_detectedx = 00000000 CBFS @ 200 size ffe00 CBFS: 'Master Header Locator' located CBFS at [200:100000) CBFS: Locating 'microcode_amd.bin' CBFS: 'microcode_amd.bin' not found. [microcode] microcode file not found. Skipping updates. cpuSetAMDMSR done Enter amd_ht_init FMAP: Found "FLASH" version 1.1 at 0. FMAP: base = fff00000 size = 100000 #areas = 3 FMAP area COREBOOT found @ 200 (1048064 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 398c0 size 48c No CMOS option 'hypertransport_speed_limit'. Exit amd_ht_init cpuSetAMDPCI 00 done Prep FID/VID Node:00 F3x80: e600e681 F3x84: 80e641e6 F3xD4: c8810f26 F3xD8: 03001016 F3xDC: 0000532a core0 started: start_other_cores() NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead. init node: 00 cores: 01 pass 1 Start other core - nodeid: 00 cores: 01 started ap apicid: NOTICE: read_option() used to access CMOS from non-ROMCC code, please use get_option() instead. get_boot_apic_id: using 1 as APIC ID for node 0, core 1 * AP 01started rs780_early_setup() fam10_optimization() rs780_por_init sb700_early_setup() FMAP: area COREBOOT found @ 200 (1048064 bytes)CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 398c0 size 48c No CMOS option 'sata_ahci_mode'. sb700_devices_por_init() sb700_devices_por_init(): SMBus Device, BDF:0-20-0 found SMBUS controller on 00:00.0 SMBus controller enabled, sb revision is A14 sb700_devices_por_init(): IDE Device, BDF:0-20-1 sb700_devices_por_init(): LPC Device, BDF:0-20-3 sb700_devices_por_init(): P2P Bridge, BDF:0-20-4 sb700_devices_por_init(): SATA Device, BDF:0-17-0 FMAP: area COREBOOT found @ 200 (1048064 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 398c0 size 48c No CMOS option 'cpu_c_states'. sb700_pmio_por_init() Begin FIDVID MSR 0xc0010071 0x30bc0073 0x3c005440 End FIDVIDMSR 0xc0010071 0x30bc0073 0x3c001c0e rs780_htinit cpu_ht_freq=b. rs780_htinit: HT3 mode fill_mem_ctrl() Timestamp - before ram initialization: 979243323 raminit_amdmct() raminit_amdmct begin: FMAP: area COREBOOT found @ 200 (1048064 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 398c0 size 48c mctAutoInitMCT_D: mct_init Node 0 mtAutoInitMCT_D: mct_InitialMCT_D mct_InitialMCT_D: clear_legacy_Mode mctAutoInitMCT_D: mctSMBhub_Init mctAutoInitMCT_D: mct_preInitDCT FMAP: area COREBOOT found @ 200 (1048064 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 398c0 size 48c No CMOS option 'dimm_spd_checksum'. DIMMPresence: DIMMValid=1 DIMMPresence: DIMMPresent=1 DIMMPresence: RegDIMMPresent=0 DIMMPresence: LRDIMMPresent=0 DIMMPresence: DimmECCPresent=0 DIMMPresence: DimmPARPresent=0 DIMMPresence: Dimmx4Present=0 DIMMPresence: Dimmx8Present=1 DIMMPresence: Dimmx16Present=0 DIMMPresence: DimmPlPresent=0 DIMMPresence: DimmDRPresent=0 DIMMPresence: DimmQRPresent=0 DIMMPresence: DATAload[0]=1 DIMMPresence: MAload[0]=8 DIMMPresence: MAdimms[0]=1 DIMMPresence: DATAload[1]=0 DIMMPresence: MAload[1]=0 DIMMPresence: MAdimms[1]=0 DIMMPresence: Status 2000 DIMMPresence: ErrStatus 0 DIMMPresence: ErrCode 0 DIMMPresence Done DCTPreInit_D: mct_DIMMPresence Done FMAP: area COREBOOT found @ 200 (1048064 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 398c0 size 48c No CMOS option 'allow_spd_nvram_cache_restore'. mctAutoInitMCT_D: mct_init Node 1 mctAutoInitMCT_D: mct_init Node 2 mctAutoInitMCT_D: mct_init Node 3 mctAutoInitMCT_D: mct_init Node 4 mctAutoInitMCT_D: mct_init Node 5 mctAutoInitMCT_D: mct_init Node 6 mctAutoInitMCT_D: mct_init Node 7 FMAP: area COREBOOT found @ 200 (1048064 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 398c0 size 48c WARNING: No CMOS option 'allow_spd_nvram_cache_restore'. mctAutoInitMCT_D: mctSMBhub_Init mctAutoInitMCT_D: mct_initDCT SPDCalcWidth: Status 2000 SPDCalcWidth: ErrStatus 0 SPDCalcWidth: ErrCode 0 SPDCalcWidth: Done DCTInit_D: mct_SPDCalcWidth Done AutoCycTiming_D: Start FMAP: area COREBOOT found @ 200 (1048064 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 398c0 size 48c mctGet_MaxLoadFreq: Channel 1: 1 DIMM(s) detected mctGet_MaxLoadFre: Channel 2: 0 DIMM(s) detected mct_MaxLoadFreq: unbuffered DIMMs on 1500mV channel; limiting to DDR3-1333 GetPresetmaxF_D: Start GetPresetmaxF_D: Done SPDGetTCL_D: Start SPDGetTCL_D: DIMMCASL 6 SPDGetTCL_D: DIMMAutoSpeed 4 SPDGetTCL_D: Status 2000 SPDGetTCL_D: ErrStatus 0 SPDGetTCL_D: ErrCode 0 SPDGetTCL_D: Done SPD2ndTiming: Start SPD2ndTiming: Done AutoCycTiming: Status 2000 AutoCycTiming: ErrStatus 0 AutoCycTiming: ErrCode 0 AutoCycTiming: Done DCTInit_D: AutoCycTiming_D Done SPDSetBanks: CSPresent 1 SPDSetBanks: Status 2000 SPDSetBanks: ErrStatus 0 SPDSetBanks: ErrCode 0 SPDSetBanks: Done AfterStitch pDCTstat->NodeSysBase = 0 mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7fffff StitchMemory: Status 2000 titchMemory: ErrStatus 0 StitchMemory: ErrCode 0 StitchMemory: Done FMAP: area COREBOOT found @ 200 (1048064 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 398c0 size 48c InterleaveBanks_D: Status 2000 InterleaveBanks_D: ErrStatus 80 InterleaveBanks_D: ErrCode 0 InterleaveBanks_D: Done AutoConfig_D: DramControl: 00002a06 AutoConfig_D: DramTimingLo: 00090092 AutoConfig_D: DramConfigMisc: 00000000 AutoConfig_D: DramConfigMisc2: 00000040 AutoConfig_D: DramConfigLo: 08010000 AutoConfig_D: DramConfigHi: 0f48000b mct_SetDramConfigHi_D: Start mct_SetDramConfigHi_D: DramConfigHi: 1f48010b mct_SetDramConfigHi_D: Done mct_EarlyArbEn_D: Start mct_EarlyArbEn_D: Done AutoConfig: Status 2000 AutoConfig: ErrStatus 80 AutoConfig: ErrCode 0 AutoConfig: Done DCTInit_D: AutoConfig_D Done set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlatformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 20113222 ct_PlatformSpec: Done InitPhyCompensation: DCT 0: Start InitPhyCompensation: DCT 0: Done DCTInit_D: PlatformSpec_D Done DCTFinalInit_D: StartupDCT_D Start mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start mct_DCTAccessDone: Start mct_DCTAccessDone: Done Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00020040 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 0 rank 0 MR3 control word 00030000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00010006 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00000528 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_SendZQCmd: Start mct_SendZQCmd: Done mct_DCTAccessDone: Start mct_DCTAccessDone: Done mct_DramInit_Sw_D: Done DCTFinaInit_D: StartupDCT_D Done mctAutoInitMCT_D: SyncDCTsReady_D mctAutoInitMCT_D: HTMemMapInit_D Node: 00 base: 00 limit: 7fffff BottomIO: a00000 Node: 00 base: 03 limit: 7fffff Node: 01 base: 00 limit: 00 Node: 02 base: 00 limit: 00 Node: 03 base: 00 limit: 00 Node: 04 base: 00 limit: 00 Node: 05 base: 00 limit: 00 Node: 06 base: 00 limit: 00 Node: 07 base: 00 limit: 00 mctAutoInitMCT_D: CPUMemTyping_D CPUMemTyping: Cache32bTOP:800000 CPUMemTyping: Bottom32bIO:800000 CPUMemTyping: Bottom40bIO:0 mctAutoInitMCT_D: mctHookAfterCPU mctAutoInitMCT_D: DQSTiming_D phyAssistedMemFnceTraining: Start phyAssistedMemFnceTraining: Done AgesaHwWlPhase1: training nibble 0 Programmed DCT 0 write levelling ODT pattern 00000001 from DIMM 0 data Lane 00 initial seed: 000d Lane 01 initial seed: 000d Lane 02 initial seed: 000d Lane 03 initial seed: 000d Lane 04 initial seed: 000d Lane 05 initial seed: 000d Lae 06 initial seed: 000d Lane 07 initial seed: 000d Lane 00 nibble 0 raw readback: 0008 Lane 00 nibble 0 adjusted value (pre nibble): 0008 Lane 00 nibble 0 adjusted value (post nibble): 0008 Lane 01 nibble 0 raw readback: 000d Lane 01 nibble 0 adjusted value (pre nibble): 000d Lane 01 nibble 0 adjusted value (post nibble): 000d Lane 02 nibble 0 raw readback: 0010 Lane 02 nibble 0 adjusted value (pre nibble): 0010 Lane 02 nibble 0 adjusted value (post nibble): 0010 Lane 03 nibble 0 raw readback: 0016 Lane 03 nibble 0 adjusted value (pre nibble): 0016 Lane 03 nibble 0 adjusted value (post nibble): 0016 Lane 04 nibble 0 raw readback: 001c Lane 04 nibble 0 adjusted value (pre nibble): 001c Lane 04 nibble 0 adjusted value (post nibble): 001c Lane 05 nibble 0 raw readback: 001d Lane 05 nibble 0 adjusted value (pre nibble): 001d Lane 05 nibble 0 adjusted value (post nibble): 001d Lane 06 nibble 0 raw readback: 001f Lane 06 nibble 0 adjusted value (pre nibble): 001f Lane 06 nibble 0 adjusted value (post nibble): 001f Lane 07 nibble 0 raw readback: 0020 Lane 07 nibble 0 adjusted value (pre nibble): 0020 Lane 07 nibble 0 adjusted value (post nibble): 0020 SetTargetFreq: Start SetTargetFreq: Node 0: New frequency code: 0006 ChangeMemClk: Start ChangeMemClk: Done SetTargetFreq: Done SPD2ndTiming: Start SPD2ndTiming: Done set_2t_configuration: Start set_2t_configuration: Done mct_BeforePlatformSpec: Start mct_BeforePlatformSpec: Done mct_PlaformSpec: Start Programmed DCT 0 timing/termination pattern 00000000 20113222 mct_PlatformSpec: Done mct_BeforeDramInit_Prod_D: Start mct_ProgramODT_D: Start mct_ProgramODT_D: Done mct_BeforeDramInit_Prod_D: Done mct_DramInit_Sw_D: Start Going to send DCT 0 DIMM 0 rank 0 MR2 control word 00020050 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 0 rank 0 MR3 control word 00030000 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 0 rank 0 MR1 control word 00010006 mct_SendMrsCmd: Start mct_SendMrsCmd: Done Going to send DCT 0 DIMM 0 rank 0 MR0 control word 00000b58 mct_SendMrsCmd: Start mct_SendMrsCmd: Done mct_DramInit_Sw_D: Done AgesaHwWlPhase1: training nibble 0 Programmed DCT 0 write levelling ODT pattern 00000001 from DIMM 0 data Lane 00 new seed: 000d Lane 01 new seed: 0015 Lane 02 new seed: 001a Lane 03 new seed: 0024 Lane 04 new seed: 002e Lane 05 new seed: 0030 Lane 06 new seed: 0033 Lane 07 new seed: 0035 Lane 00 nibble 0 raw readback: 0012 Lane 00 nibble 0 adjusted value (pre nibble): 0012 Lane 00 nibble 0 adjusted value (post nibble): 0012 Lane 01 nibble 0 raw readback: 0019 Lane 01 nibble 0 adjusted value (pre nibble): 0019 Lane 01 nibble 0 adjusted value (post nibble): 0019 Lane 02 nibble 0 raw readback: 001e Lane 02 nibble 0 adjusted value (pre nibble): 001e Lane 02 nibble 0 adjusted value (post nibble): 001e Lane 03 nibble 0 raw readback: 0025 Lane 03 nibble 0 adjusted value (pre nibble): 0025 Lane 03 nibble 0 adjusted value (post nibble): 0025 Lane 04 nibble 0 raw readback: 002c Lane 04 nibble 0 adjusted value (pre nibble): 002c Lane 04 nibble 0 adjusted value (post nibble): 002c Lane 05 nibble 0 raw readback: 002f Lane 05 nibble 0 adjusted value (pre nibble): 002f Lane 05 nibble 0 adjusted value (post nibbe): 002f Lane 06 nibble 0 raw readback: 0035 Lane 06 nibble 0 adjusted value (pre nibble): 0035 Lane 06 nibble 0 adjusted value (post nibble): 0035 Lane 07 nibble 0 raw readback: 0038 Lane 07 nibble 0 adjusted value (pre nibble): 0038 Lane 07 nibble 0 adjusted value (post nibble): 0038 TrainRcvrEn: Status 2000 TrainRcvrEn: ErrStatus 80 TrainRcvrEn: ErrCode 0 TrainRcvrEn: Done TrainDQSRdWrPos: Status 2000 TrainDQSRdWrPos: TrainErrors 0 TrainDQSRdWrPos: ErrStatus 80 TrainDQSRdWrPos: ErrCode 0 TrainDQSRdWrPos: Done mctAutoInitMCT_D: UMAMemTyping_D mctAutoInitMCT_D: :OtherTiming FMAP: area COREBOOT found @ 200 (1048064 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 398c0 size 48c No CMOS option 'interleave_nodes'. InterleaveNodes_D: Status 2000 InterleaveNodes_D: ErrStatus 80 InterleaveNodes_D: ErrCode 0 InterleaveNodes_D: Done InterleaveChannels_D: Node 0 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 80 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 1 InterleaveChanels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 2 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 3 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 4 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 5 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 6 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Node 7 InterleaveChannels_D: Status 2000 InterleaveChannels_D: ErrStatus 0 InterleaveChannels_D: ErrCode 0 InterleaveChannels_D: Done mctAutoInitMCT_D Done: Global Status: 0 raminit_amdmct end: Timestamp - after ram nitialization: 7897339949 CBMEM: IMD: root @ 6ffff000 254 entries. IMD: root @ 6fffec00 62 entries. Timestamp - start of romstage: 2533637 Timestamp - before ram initialization: 791350256 Timestamp - after ram initialization: 7709446882 amdmct_cbmem_store_info: Storing AMDMCT configuration in CBMEM FMAP: area COREBOOT found @ 200 (1048064 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 398c0 size 48c No CMOS option 'ecc_scrub_rate'. BSP overran lower stack boundary. Undefined behaviour may result! Timestamp - end of romstage: 8051516238 CBFS @ 200 size ffe00 CBFS: 'Master Header Locator' located CBFS at [200:100000) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 27b00 size 1170a Timestamp - starting to load ramstage: 8117802998 Timestamp - starting LZMA decompress (ignore for x86): 8131654485 Timestamp - finished LZMA decompress (ignore for x86): 8295442662 Timestamp - finished loading ramstage: 8313806819 coreboot-4.9-193-g0185b8b82a Sun Jan 6 15:48:29 UTC 2019 ramstage starting... Enumerating buses... Mainboard enable. dev=0x00e232a0 Init adt7461end, status 0x02 fd setup_bsp_ramtop, TOP MEM: msr.lo = 0x80000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x00000000, msr.hi = 0x00000000 setup_uma_memory: uma size 0x10000000, memory start 0x70000000 CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 398c0 size 48c CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 398c0 size 48c rs780_enable: dev=00e24e40, VID_DID=0x96011022 Bus-0, Dev-0, Fun-0. get_pbus: dev is NULL!