Nick: stefanct
E-mail: none
Board: ichspi flag clear
Contents: 
diff --git a/ichspi.c b/ichspi.c
index e1395ee..809d007 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -754,9 +754,9 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset,
 
 	/* Assemble SPIS */
 	temp16 = REGREAD16(ICH7_REG_SPIS);
-	/* keep reserved bits */
+	/* keep reserved bits only */
 	temp16 &= SPIS_RESERVED_MASK;
-	/* clear error status registers */
+	/* clear error status registers (by writing 1 to them) */
 	temp16 |= (SPIS_CDS | SPIS_FCERR);
 	REGWRITE16(ICH7_REG_SPIS, temp16);
 
@@ -825,9 +825,11 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset,
 	temp16 = REGREAD16(ICH7_REG_SPIS);
 	if (temp16 & SPIS_FCERR) {
 		msg_perr("Transaction error!\n");
-		/* keep reserved bits */
+		/* keep reserved bits only */
 		temp16 &= SPIS_RESERVED_MASK;
-		REGWRITE16(ICH7_REG_SPIS, temp16 | SPIS_FCERR);
+		/* clear error status registers (by writing 1 to them) */
+		temp16 |= (SPIS_CDS | SPIS_FCERR);
+		REGWRITE16(ICH7_REG_SPIS, temp16);
 		return 1;
 	}
 
@@ -874,7 +876,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
 	temp32 = REGREAD32(ICH9_REG_SSFS);
 	/* Keep reserved bits only */
 	temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
-	/* Clear cycle done and cycle error status registers */
+	/* Clear cycle done and cycle error status registers (by writing 1 to them) */
 	temp32 |= (SSFS_FDONE | SSFS_FCERR);
 	REGWRITE32(ICH9_REG_SSFS, temp32);
 
@@ -949,10 +951,11 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
 		msg_perr("Transaction error!\n");
 		prettyprint_ich9_reg_ssfs(temp32);
 		prettyprint_ich9_reg_ssfc(temp32);
-		/* keep reserved bits */
+		/* keep reserved bits only*/
 		temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
-		/* Clear the transaction error. */
-		REGWRITE32(ICH9_REG_SSFS, temp32 | SSFS_FCERR);
+		/* Clear cycle done and cycle error status registers (by writing 1 to them) */
+		temp32 |= (SSFS_FDONE | SSFS_FCERR);
+		REGWRITE32(ICH9_REG_SSFS, temp32);
 		return 1;
 	}
 
@@ -1275,7 +1278,7 @@ static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr,
 	msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr);
 	ich_hwseq_set_addr(addr);
 
-	/* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
+	/* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
 	REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
 
 	hsfc = REGREAD16(ICH9_REG_HSFC);