Nick: MaZePallas
E-mail: zenczykowski@mail.com
Board: http://www.jetwaycomputer.com/download/BIOS/NC9B/BC9BAA06.zi
Contents: 
BC9BAA06.BIN.descs 
The flash image has a size of 4194304 [0x400000] bytes.
=== Content Section ===
FLVALSIG 0x0ff0a55a
FLMAP0   0x03040003
FLMAP1   0x12100206
FLMAP2   0x00210120

--- Details ---
NR          (Number of Regions):                     4
FRBA        (Flash Region Base Address):         0x040
NC          (Number of Components):                  1
FCBA        (Flash Component Base Address):      0x030
ISL         (ICH/PCH Strap Length):                 18
FISBA/FPSBA (Flash ICH/PCH Strap Base Address):  0x100
NM          (Number of Masters):                     3
FMBA        (Flash Master Base Address):         0x060
MSL/PSL     (MCH/PROC Strap Length):                 1
FMSBA       (Flash MCH/PROC Strap Base Address): 0x200

=== Component Section ===
FLCOMP   0x09300023
FLILL    0x00000000

--- Details ---
Component 1 density:             4 MB
Component 2 is not used.
Read Clock Frequency:           20 MHz
Read ID and Status Clock Freq.: 33 MHz
Write and Erase Clock Freq.:    33 MHz
Fast Read is supported.
Fast Read Clock Frequency:      33 MHz
No forbidden opcodes.

=== Region Section ===
FLREG0   0x00000000
FLREG1   0x03ff0200
FLREG2   0x01ff0003
FLREG3   0x00020001
FLREG4   0x00001fff

--- Details ---
Region 0 (Descr.) 0x00000000 - 0x00000fff
Region 1 (BIOS  ) 0x00200000 - 0x003fffff
Region 2 (ME    ) 0x00003000 - 0x001fffff
Region 3 (GbE   ) 0x00001000 - 0x00002fff
Region 4 (Platf.) is unused.

=== Master Section ===
FLMSTR1  0x0a0b0000
FLMSTR2  0x0c0d0000
FLMSTR3  0x08080118

--- Details ---
      Descr. BIOS ME GbE Platf.
BIOS    r     rw      rw     
ME      r         rw  rw     
GbE                   rw     

=== Upper Map Section ===
FLUMAP1  0x000010df

--- Details ---
VTL (length in DWORDS) = 16
VTBA (base address)    = 0x000df0

VSCC Table: 8 entries
  JID0  = 0x0000471f
  VSCC0 = 0x20152015
    Manufacturer ID 0x1f, Device ID 0x4700
    BES=0x1, WG=1, WSR=0, WEWS=1, EO=0x20, VCL=0
  JID1  = 0x001740ef
  VSCC1 = 0x20052005
    Manufacturer ID 0xef, Device ID 0x4017
    BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0
  JID2  = 0x001720c2
  VSCC2 = 0x20052005
    Manufacturer ID 0xc2, Device ID 0x2017
    BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0
  JID3  = 0x001620c2
  VSCC3 = 0x20052005
    Manufacturer ID 0xc2, Device ID 0x2016
    BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0
  JID4  = 0x0016701c
  VSCC4 = 0x20052005
    Manufacturer ID 0x1c, Device ID 0x7016
    BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0
  JID5  = 0x001740c8
  VSCC5 = 0x20052005
    Manufacturer ID 0xc8, Device ID 0x4017
    BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0
  JID6  = 0x0017311c
  VSCC6 = 0x20052005
    Manufacturer ID 0x1c, Device ID 0x3117
    BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0
  JID7  = 0x001640c8
  VSCC7 = 0x20052005
    Manufacturer ID 0xc8, Device ID 0x4016
    BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0

=== Softstraps ===
--- North/MCH/PROC (1 entries) ---
STRP0  = 0x00000000

ISL (18) is greater than the current maximum of 16 entries.
Only the first 16 entries will be printed.
--- South/ICH/PCH (16 entries) ---
STRP0  = 0x0810d782
STRP1  = 0x0000010f
STRP2  = 0x00560000
STRP3  = 0x00000000
STRP4  = 0x00c8e102
STRP5  = 0x00000000
STRP6  = 0x00000000
STRP7  = 0x00000000
STRP8  = 0x00000000
STRP9  = 0x30000d80
STRP10 = 0x00c10044
STRP11 = 0x99000097
STRP12 = 0x00000000
STRP13 = 0x00000000
STRP14 = 0x00000000
STRP15 = 0x0000037e

Detailed South/ICH/PCH information is probably not reliable, printing anyway.
--- PCH ---
Chipset configuration Softstrap 1: 1
Intel ME SMBus Select is enabled.
SMLink0 segment is enabled.
SMLink1 segment is enabled.
SMLink1 Frequency: 100 kHz
Intel ME SMBus Frequency: 100 kHz
SMLink0 Frequency: reserved
GPIO12 is used as LAN_PHY_PWR_CTRL.
LinkSec is disabled.
DMI RequesterID Checks are disabled.
BIOS Boot-Block size (BBBS): 64 kB.
Chipset configuration Softstrap 3: 0xf
Chipset configuration Softstrap 2: 0x1
ME SMBus ASD address is disabled.
ME SMBus Controller ASD Target address: 0x00
ME SMBus MCTP Address is disabled.
ME SMBus MCTP target address: 0x00
ME SMBus I2C address is disabled.
ME SMBus I2C target address: 0x00
Intel PHY is connected.
GbE MAC SMBus address is enabled.
GbE MAC SMBus address: 0x70
GbE PHY SMBus address: 0x64
Intel ME SMBus Subsystem Vendor ID: 0x0000
Intel ME SMBus Subsystem Device ID: 0x0000
PCI Express Port Configuration Strap 1: 4x1 Ports 1-4 (x1)
PCI Express Port Configuration Strap 2: 4x1 Ports 5-8 (x1)
PCIe Lane Reversal 1: PCIe Lanes 0-3 are not reserved.
PCIe Lane Reversal 2: PCIe Lanes 4-7 are not reserved.
DMI Lane Reversal: DMI Lanes 0-3 are not reserved.
ME Debug status writes over SMBUS are disabled.
ME Debug SMBus Emergency Mode address: 0x00 (raw)
Default PHY PCIe Port is 6.
Integrated MAC/PHY communication over PCIe is enabled.
PCIe ports Subtractive Decode Agent is disabled.
GPIO74 is used as PCHHOT#.
Management Engine will boot from ROM, then flash.
ME Debug SMBus Emergency Mode is disabled.
ME Debug SMBus Emergency Mode Address: 0x00
Integrated Clocking Configuration used: 0
PCH Signal CL_RST1# does not assert when Intel ME performs a reset.
ICC Profile is selected by BIOS.
Deep SX is supported on the platform.
ME Debug LAN Emergency Mode is enabled.
SMLink1 GP Address is enabled.
SMLink1 controller General Purpose Target address: 0x4b
SMLink1 I2C Target address is enabled.
SMLink1 I2C Target address: 0x4c
Chipset configuration Softstrap 6: 0
Integrated wired LAN is disabled.
Chipset configuration Softstrap 5: 0
SMLink1 provides temperature from the CPU, PCH and DIMMs.
GPIO29 is used as SLP_LAN#.
Integrated Clock: Full Integrated Clock Mode

The MAC address might be at offset 0x1000: 88:88:88:88:87:88